4 Commits (c2f5db6fca0c9fc7ea05bcf80d134d1e455406d0)

Author	SHA1	Message	Date
Paul Mackerras	0cdaa2778f	xilinx-mult: Move some registers later in the data flow ... This changes s0 to use the P register rather than the A/B/C input registers, thus improving the timing of the multiplier output. The m00, m02 and m03 multipliers now use their P registers rather than the M registers, moving the addition they do from the second cycle to the first. Also, the XOR that inverts the 32 LSBs is moved before the output register. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	4 years ago
Paul Mackerras	f1238299bd	execute1: Take an extra cycle for OE=1 multiply instructions ... We now expect the overflow signal from the multiplier to come along one cycle later than the product. This breaks up a long combinatorial path and improves timing. This also changes some uses of v.<field> to r.<field> in the slow op logic, which should help timing as well. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	5 years ago
Paul Mackerras	535341961d	multiplier: Generalize interface to the multiplier ... This makes the interface to the multiplier more general so an instance of it can be used in the FPU. It now has a 128-bit addend that is added on to the product. Instead of an input to negate the output, it now has a "not_result" input to complement the output. Execute1 uses not_result=1 and addend=-1 to get the effect of negating the output. The interface is defined this way because this is what can be done easily with the Xilinx DSP slices in xilinx-mult.vhdl. This also adds clock enable signals to the DSP slices, mostly for the sake of reducing power consumption. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	5 years ago
Paul Mackerras	0809bc898b	multiply: Use DSP48 slices for multiplication on Xilinx FPGAs ... This adds a custom implementation of the multiplier which uses 16 DSP48E1 slices to do a 64x64 bit multiplication in 2 cycles. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	5 years ago