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fpu-init
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dcache-unused-sig
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divider-init
loadstore-pmu-init
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
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jtag-port-2
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nia-debug
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2 Commits (bee0c94fb4a5a8c798c9a7ae5810b966c4e0beae)

Author SHA1 Message Date
Paul Mackerras bee0c94fb4 tests/privileged: Update for instruction translation 
Since setting MSR[PR] = 1 forces instruction translation on, we need
to set up translations for the problem state code to use.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago
Paul Mackerras 10f4be4309 tests: Add a test for privileged instruction interrupts 
This adds a test that tries to execute various privileged instructions
with MSR[PR] = 1.  This also incidentally tests some of the MSR bit
manipulations.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago