matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
1,002 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'b29c58f3d1'
${ noResults }
Commit Graph

1002 Commits (b29c58f3d14e29bf1c61ab1a54e19f4303ee7de8)
 

Author SHA1 Message Date
Anton Blanchard 5d82af5204 Silence some loadstore related debug 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 04eb9583e6 Clean up register read debug output 
Right now we continually print all 3 possible GPRs an instruction
may be using. Add signals so we only print GPRs when they are
actually read. This should hopefully optimise away when synthesized.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 9fbaea6f08 Rework CR file and add forwarding 
Handle the CR as a single field with per nibble enables. Forward any
writes in the same cycle.

If this proves to be an issue for timing, we may want to revisit
this in the future. For now, it keeps things simple.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 7c2a2b7414
Merge pull request #19 from antonblanchard/cmod-a7 
Cmod A7-35 support
 5 years ago
Anton Blanchard 270d7b1b9a Cmod A7-35 support 
This adds support for the Digilane Cmod A7-35.

I had to use the MMCM because the clock (12 MHz) is below the PLL
minimum of 19 MHz.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 14da542d4a
Merge pull request #20 from antonblanchard/reset-rework2 
Rework reset code
 5 years ago
Anton Blanchard 0832fed06c
Merge pull request #22 from antonblanchard/store-fix 
Stores need to wait for wishbone write ack
 5 years ago
Anton Blanchard 021d427d3f Stores need to wait for wishbone write ack 
I wasn't waiting to get a wishbone ack back on stores before continuing.
This creates all sorts of problems when we add pipelining and send
loads and stores down the pipe faster.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard c64bf23c1a
Merge pull request #21 from antonblanchard/xdc-update 
Add CONFIG_VOLTAGE and CFGBVS entries
 5 years ago
Anton Blanchard 63295526ad Add CONFIG_VOLTAGE and CFGBVS entries 
Remove a couple of warnings from Vivado.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 03fd06deaf Rework SOC reset 
The old reset code was overly complicated and never worked properly.
Replace it with a simpler sequence that uses a couple of shift registers
to assert resets:

- Wait a number of external clock cycles before removing reset from
  the PLL.

- After the PLL locks and the external reset button isn't pressed,
  wait a number of PLL clock cycles before removing reset from the SOC.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard a53ad60014 Rename a few reset signals 
clk -> ext_clk
reset_n -> ext_rst
reset -> rst

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard e39400681b
Merge pull request #18 from mikey/verific 
Fix verific script with new VHDL files
 5 years ago
Michael Neuling 83d773090e Fix verific script with new VHDL files 
This really needs to be auto generated, but here we are.

Signed-off-by: Michael Neuling <mikey@neuling.org>
 5 years ago
Anton Blanchard a15eb4e28d
Merge pull request #17 from antonblanchard/writeback-signal 
Use a better input signal in writeback
 5 years ago
Anton Blanchard 147b259691 Use a better input signal in writeback 
w_in comes from the execution unit, it makes more sense to call
it e_in.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 3f59396907
Merge pull request #16 from antonblanchard/decode2_rework2 
Rework decode2
 5 years ago
Anton Blanchard 5e140298a5 Rework decode2 
The decode2 stage was spaghetti code and needed cleaning up.
Create a series of functions to pull fields from a ppc instruction
and also a series of helpers to extract values for the execution
units.

As suggested by Paul, we should pass all signals to the execution
units and only set the valid signal conditionally, which should
use less resources.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard d1fdc286c4
Merge pull request #13 from mikey/dynamic-ranges 
Remove dynamic ranges from code
 5 years ago
Michael Neuling 4d5abfb430 Remove dynamic ranges from code 
Some VHDL compilers like verific [1] don't like these, so let's remove
them. Lots of random code changes, but passes make check.

Also add basic script to run verific and generate verilog.

1. https://www.verific.com/

Signed-off-by: Michael Neuling <mikey@neuling.org>
 5 years ago
Anton Blanchard 7a85e3877d
Merge pull request #10 from antonblanchard/arty-fix 
Arty A7 reset pin is C2
 5 years ago
Anton Blanchard 5379b805ec Arty A7 reset pin is C2 
Use C2 for reset, and fix up a few whitespace issues.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 3819768d2a
Merge pull request #7 from riktw/fusesoc_arty_a7 
Fusesoc arty a7
 5 years ago
Anton Blanchard 5aba4e7346
Merge pull request #9 from antonblanchard/travis-fix 
A few Travis CI fixes
 5 years ago
Anton Blanchard 6c8d28a642 A few Travis CI fixes 
- Switch to using ghdl/vunit:llvm, it's a smaller container
- We need to "apt update" before installing packages

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
riktw 4ebd6fc1f7 Added support for building for Arty A7 boards 5 years ago
Anton Blanchard f98370f9e6
Merge pull request #5 from antonblanchard/travis-test 
Add an initial travis.yml
 5 years ago
Anton Blanchard 2ee269abdb Add an initial travis.yml 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 0fd18c2455 Add srd and srw 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 73daacbcd4 Add sim only divw 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 95b9f19882 Fix ghdl build error with pp_soc_memory 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 1fa0b332ca micropython only requires 512kB of BRAM 
Mikey points out that our stack grows down from 512kB and our
heap is below that too, so we can reduce our BRAM requirements,
which allowing some smaller FPGA boards to work. Not sure why
I thought we were using memory between 512kB and 1MB.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 1aadee281d
Merge pull request #6 from mikey/gif 
Add pretty gif demo of MicroPython on Microwatt to README.md
 5 years ago
Anton Blanchard 96787091a6 Add -Wall to CFLAGS 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Michael Neuling d618171d13 Add pretty gif demo of MicroPython on Microwatt to README.md 
Signed-off-by: Michael Neuling <mikey@neuling.org>
 5 years ago
Anton Blanchard 7277c6b5ab Add missing argument to fprintf warning 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 77f1588a7f Add some initial FPGA synthesis instructions 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 0a0ad9b384 Rebuild hello world assuming a 50MHz clock 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard c036363d8f
Merge pull request #3 from olofk/plle2 
Add and use plle2 primitive for nexys boards
 5 years ago
Olof Kindgren 12327034d6 Add and use plle2 primitive for nexys boards 5 years ago
Anton Blanchard 5b2984a15d
Merge pull request #4 from sharkcz/build 
don't cross compile when on Power
 5 years ago
Dan Horák 2d7994dc12 don't cross compile when on Power 5 years ago
Anton Blanchard 8bc3e8ea0a Add a simple hello_world example that also echos input 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 01e6b8f583
Merge pull request #2 from olofk/fusesoc_nexys_a7 
Fusesoc nexys a7
 5 years ago
Olof Kindgren b9bf19f912 Added synthesis target 
The synth target can be used to analyze the core after synthesis
without running P&R. Currently, the only edalize backends that
support synthesis without P&R are vivado and icestorm, and icestorm
needs yosys built with verific support to parse vhdl.

To run synthesis only for a part, run

fusesoc run --target=synth --tool=vivado microwatt --part=<part>

where part is a valid Xilinx part such as xc7a100tcsg324-1
 5 years ago
Olof Kindgren 250d09ed2d Add Nexys Video support 5 years ago
Olof Kindgren 5e56b14125 Add FuseSoC core description file with Nexys A7 support 5 years ago
Olof Kindgren abca85b034 Add constraint file for Nexys A7 5 years ago
Olof Kindgren e8ad9bed10 Expose ram init file and memory size through toplevel 5 years ago
Olof Kindgren b5bccc4c13 Add dummy clock generator 5 years ago