This moves the data formatting for read data to after a register,
instead of before, in order to improve timing. The data formatting
is now effectively combinational logic on the input side of the
writeback stage.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
We are seeing some timing issues with the second cycle of loadstore,
and we aren't doing much in the first cycle, so move it here.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
We only need two write ports for load with update instructions.
Having two write ports just for this instruction is expensive.
For now we will force them to be the only instruction in the
pipeline, and take two cycles of writeback.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
I wasn't waiting to get a wishbone ack back on stores before continuing.
This creates all sorts of problems when we add pipelining and send
loads and stores down the pipe faster.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Some VHDL compilers like verific [1] don't like these, so let's remove
them. Lots of random code changes, but passes make check.
Also add basic script to run verific and generate verilog.
1. https://www.verific.com/
Signed-off-by: Michael Neuling <mikey@neuling.org>
Paul Mackerras
Anton Blanchard
Michael Neuling