matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
650 Commits
31 Branches
0 Tags
65 MiB
Commit Graph

2 Commits (aebd915f8f465f66f33703164f9fdec419a53aa6)

Author SHA1 Message Date
Anton Blanchard 04c56a0c52 Pass clock frequency to UART sim wrapper 
The UART sim wrapper is currently hard wired to 50 MHz.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 3e8a6a8fc2 Add yosys/verilator support 
Add a microwatt-verilator target that simulates the
ghdl -> yosys -> verilog -> verilator path. A good test of
ghdl/yosys synthesis.

Because the everything is run through synthesis, the instruction
image is baked into the build via the RAM_INIT_FILE generic.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>