Commit Graph

612 Commits (a93d9e77c9cdc69e6e98ceaf12d2c73dcd22230e)
 

Author SHA1 Message Date
Anton Blanchard 5b2984a15d
Merge pull request from sharkcz/build
don't cross compile when on Power
Dan Horák 2d7994dc12 don't cross compile when on Power
Anton Blanchard 8bc3e8ea0a Add a simple hello_world example that also echos input
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 01e6b8f583
Merge pull request from olofk/fusesoc_nexys_a7
Fusesoc nexys a7
Olof Kindgren b9bf19f912 Added synthesis target
The synth target can be used to analyze the core after synthesis
without running P&R. Currently, the only edalize backends that
support synthesis without P&R are vivado and icestorm, and icestorm
needs yosys built with verific support to parse vhdl.

To run synthesis only for a part, run

fusesoc run --target=synth --tool=vivado microwatt --part=<part>

where part is a valid Xilinx part such as xc7a100tcsg324-1
Olof Kindgren 250d09ed2d Add Nexys Video support
Olof Kindgren 5e56b14125 Add FuseSoC core description file with Nexys A7 support
Olof Kindgren abca85b034 Add constraint file for Nexys A7
Olof Kindgren e8ad9bed10 Expose ram init file and memory size through toplevel
Olof Kindgren b5bccc4c13 Add dummy clock generator
Anton Blanchard 37fe8b954c Add a few more FPGA related files
Add a temporary gcc patch to remove hardware divide instructions.

Also add a firmware.hex file built with a gcc with the above patch.

Right now micropython assumes 1MB of BRAM, which limits the FPGAs
we can run on. We should be able to cut it down somewhat.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 5a29cb4699 Initial import of microwatt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>