2 Commits (a750365ffa5f07046256d2824520817a6f704214)

Author	SHA1	Message	Date
Raptor Engineering Development Team	fcb783a0fb	Extend LiteDRAM VHDL wrapper to allow more than one clock line ... This is necessary for the upcoming Arctic Tern system enablement, since Arctic Tern uses two DRAM devices and a separate clock line is routed to each device. LiteX handles this behavior correctly, therefore we assume other hardware exists that uses a similar DRAM clock design. Updates from Mikey to fix some compile issues. Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Michael Neuling <mikey@neuling.org>	3 years ago
Benjamin Herrenschmidt	6fe077910b	litedram: Add simulation support ... This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago