matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
502 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'a658766fcf'
${ noResults }
Commit Graph

2 Commits (a658766fcf415bd40aa12cc26d34ec2a686188f8)

Author SHA1 Message Date
Paul Mackerras bee0c94fb4 tests/privileged: Update for instruction translation 
Since setting MSR[PR] = 1 forces instruction translation on, we need
to set up translations for the problem state code to use.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago
Paul Mackerras 10f4be4309 tests: Add a test for privileged instruction interrupts 
This adds a test that tries to execute various privileged instructions
with MSR[PR] = 1.  This also incidentally tests some of the MSR bit
manipulations.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago