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microwatt
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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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5 Commits (9fe8d211eba24eb92273c03f098be2ccc1517565)

Author SHA1 Message Date
Anton Blanchard 92a7152370 Rework pipeline, add stall and flush signals 
This adds stall and flush signals to the pipeline.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 9687034d78 Add a decode bit to mark an instruction as single through the pipeline 
This is used by the pipelining patches. Mark everyone as single through
the pipeline to start.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Benjamin Herrenschmidt b0ade2857f decode1 array fix header 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Anton Blanchard 9fbaea6f08 Rework CR file and add forwarding 
Handle the CR as a single field with per nibble enables. Forward any
writes in the same cycle.

If this proves to be an issue for timing, we may want to revisit
this in the future. For now, it keeps things simple.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago