5 Commits (8cdb00652b1693d1c4fefd20c9de3d2900cc0ecc)

Author	SHA1	Message	Date
Anton Blanchard	af462f0ca9	Reformat spi_flash_ctrl ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Anton Blanchard	c870040a20	Fix an issue in flash controller when BOOT_CLOCKS is false ... If BOOT_CLOCKS is false we currently get stuck in the flash state machine. This patch from Ben fixes it. Also fix an x state issue I see in icarus verilog where we need to reset auto_state. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Anton Blanchard	7c8bc85e44	Fix a few reset issues in flash controller ... Our flash controller fails when simulating with iverilog. Looking closer, both wb_stash and auto_last_addr are X state, and things fall apart after they get used. Initialise them both fixes the iverilog issue. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Benjamin Herrenschmidt	3c2739e10a	spi: Send dummy clocks at boot ... When using an FPGA which routes the SPI clock via STARTUPE2 as is done on the Nexys Video (or optionally on Arty), the HW needs at least 3 beats of that clock to complete the switch from the internal config clock to the one we provide. This works around it by having the SPI controller send 8 dummy clocks at boot time with CS held high. Without this, flash identification will fail those boards Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	4 years ago
Benjamin Herrenschmidt	cc4dcb3597	spi: Add SPI Flash controller ... This adds an SPI flash controller which supports direct memory-mapped access to the flash along with a manual mode to send commands. The direct mode can be set via generic to default to single wire or quad mode. The controller supports normal, dual and quad accesses with configurable commands, clock divider, dummy clocks etc... The SPI clock can be an even divider of sys_clk starting at 2 (so max 50Mhz with our typical Arty designs). A flash offset is carried via generics to syscon to tell SW about which portion of the flash is reserved for the FPGA bitfile. There is currently no plumbing to make the CPU reset past that address (TBD). Note: Operating at 50Mhz has proven unreliable without adding some delay to the sampling of the input data. I'm working in improving this, in the meantime, I'm leaving the default set at 25 Mhz. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago