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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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12 Commits (8b55fc4d9e2acbedcdde0e143744b5847dabee6e)

Author SHA1 Message Date
Anton Blanchard b57325ce29 Merge branch 'divider' of https://github.com/paulusmack/microwatt 5 years ago
Anton Blanchard 5a6f8d26d1 Rename OP_SUBFC -> OP_SUBFE, OP_ADDC -> OP_ADDE 
These were somewhat badly named.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Paul Mackerras d5bc6c8824 Add a divider unit and a testbench for it 
This adds a divider unit, connected to the core in much the same way
that the multiplier unit is connected.  The division algorithm is
very simple-minded, taking 64 clock cycles for any division (even
32-bit division instructions).

The decoding is simplified by making use of regularities in the
instruction encoding for div* and mod* instructions.  Instead of
having PPC_* encodings from the first-stage decoder for each of the
different div* and mod* instructions, we now just have PPC_DIV and
PPC_MOD, and the inputs to the divider that indicate what sort of
division operation to do are derived from instruction word bits.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago
Anton Blanchard 6d85920068 execute1 no longer needs sim_console 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Michael Neuling 1e1b799382 Remove FIXME comment 
This was mistakenly left behind in 4d5abfb430 ("Remove dynamic
ranges from code")

Signed-off-by: Michael Neuling <mikey@neuling.org>
 5 years ago
Anton Blanchard a2df2a10a2 Remove sim console 
We can force all existing code to use the UART console
by passing 0 in bit zero of the sim config register.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard a8f8c54b77 Move debug execute output into decode2 
This covers all units, and we avoid double printing.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 92a7152370 Rework pipeline, add stall and flush signals 
This adds stall and flush signals to the pipeline.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Michael Neuling 4d5abfb430 Remove dynamic ranges from code 
Some VHDL compilers like verific [1] don't like these, so let's remove
them. Lots of random code changes, but passes make check.

Also add basic script to run verific and generate verilog.

1. https://www.verific.com/

Signed-off-by: Michael Neuling <mikey@neuling.org>
 5 years ago
Anton Blanchard 0fd18c2455 Add srd and srw 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 73daacbcd4 Add sim only divw 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago