microwatt

Commit Graph

Author	SHA1	Message	Date
Anton Blanchard	c8328cdf84	Remove gcc software divide patch We have a divider, thanks to Paul. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	6cbf456388	SOC memory wishbone should clear ACK regardless of STB The memory wishbone doesn't clear ACK and move the state machine on until STB is de-asserted. This seems like it isn't compliant with the spec and results in a maximum throughput of 1 transfer every 3 cycles. Fixing this improves the situation to one transfer every 2 cycles. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	d89a9929fd	Fix clk_gen_bypass I broke clk_gen_bypass when updating the SOC reset code. Fixes `03fd06deaf` ("Rework SOC reset") Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	142a722ce4	Remove names from end record statements These are optional, and vhdlpp from iverilog barfs on them. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Benjamin Herrenschmidt	3ac1dbc737	Share soc.vhdl between FPGA and sim Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	d21ef5836d	Pass wishbone record to bram memory module (And rename it to mw_soc_memory). This makes soc.vhdl simpler and provides the same interface as the simulated memory, which will help when sharing soc.vhdl with sim later Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	1d66e1f981	Rework wishbone slave address decoding Don't make it synchronous, no latches Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	c97b080d8c	Move wishbone arbiter out of the core Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	310a56c076	Re-indent and reformat soc.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	a69a93b466	Split FPGA toplevel from soc This will be useful when we start needing different toplevels for different boards. We keep the reset and clock generators in the toplevel as they will eventually be taken over by litedram when we integrate it, and they are more likely to change on different system types. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Anton Blanchard	270d7b1b9a	Cmod A7-35 support This adds support for the Digilane Cmod A7-35. I had to use the MMCM because the clock (12 MHz) is below the PLL minimum of 19 MHz. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	14da542d4a	Merge pull request #20 from antonblanchard/reset-rework2 Rework reset code	5 years ago
Anton Blanchard	63295526ad	Add CONFIG_VOLTAGE and CFGBVS entries Remove a couple of warnings from Vivado. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	03fd06deaf	Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	a53ad60014	Rename a few reset signals clk -> ext_clk reset_n -> ext_rst reset -> rst Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	5379b805ec	Arty A7 reset pin is C2 Use C2 for reset, and fix up a few whitespace issues. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
riktw	4ebd6fc1f7	Added support for building for Arty A7 boards	5 years ago
Anton Blanchard	95b9f19882	Fix ghdl build error with pp_soc_memory Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	1fa0b332ca	micropython only requires 512kB of BRAM Mikey points out that our stack grows down from 512kB and our heap is below that too, so we can reduce our BRAM requirements, which allowing some smaller FPGA boards to work. Not sure why I thought we were using memory between 512kB and 1MB. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	0a0ad9b384	Rebuild hello world assuming a 50MHz clock Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Olof Kindgren	12327034d6	Add and use plle2 primitive for nexys boards	5 years ago
Anton Blanchard	8bc3e8ea0a	Add a simple hello_world example that also echos input Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Olof Kindgren	abca85b034	Add constraint file for Nexys A7	5 years ago
Olof Kindgren	e8ad9bed10	Expose ram init file and memory size through toplevel	5 years ago
Olof Kindgren	b5bccc4c13	Add dummy clock generator	5 years ago
Anton Blanchard	37fe8b954c	Add a few more FPGA related files Add a temporary gcc patch to remove hardware divide instructions. Also add a firmware.hex file built with a gcc with the above patch. Right now micropython assumes 1MB of BRAM, which limits the FPGAs we can run on. We should be able to cut it down somewhat. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	5a29cb4699	Initial import of microwatt Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago

27 Commits (8af2b004c389aeb65e12621eb59f5416706268f1)