8 Commits (85062793b1f25054379cfc066aed4050ff803030)

Author	SHA1	Message	Date
Anton Blanchard	acdb2ea157	No need to gate nia or insn in decode1 ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	b9e28598b4	Explicitly check against '1' in if statements ... nvc doesn't like what I think is a VHDL 2008 construct. Lets just check against '1' explicitly. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	a2df2a10a2	Remove sim console ... We can force all existing code to use the UART console by passing 0 in bit zero of the sim config register. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	92a7152370	Rework pipeline, add stall and flush signals ... This adds stall and flush signals to the pipeline. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	9687034d78	Add a decode bit to mark an instruction as single through the pipeline ... This is used by the pipelining patches. Mark everyone as single through the pipeline to start. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Benjamin Herrenschmidt	b0ade2857f	decode1 array fix header ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Anton Blanchard	9fbaea6f08	Rework CR file and add forwarding ... Handle the CR as a single field with per nibble enables. Forward any writes in the same cycle. If this proves to be an issue for timing, we may want to revisit this in the future. For now, it keeps things simple. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	5a29cb4699	Initial import of microwatt ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago