6 Commits (7f44980611c0b0ad06d45732a9f5b2b2179164da)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	cc4dcb3597	spi: Add SPI Flash controller ... This adds an SPI flash controller which supports direct memory-mapped access to the flash along with a manual mode to send commands. The direct mode can be set via generic to default to single wire or quad mode. The controller supports normal, dual and quad accesses with configurable commands, clock divider, dummy clocks etc... The SPI clock can be an even divider of sys_clk starting at 2 (so max 50Mhz with our typical Arty designs). A flash offset is carried via generics to syscon to tell SW about which portion of the flash is reserved for the FPGA bitfile. There is currently no plumbing to make the CPU reset past that address (TBD). Note: Operating at 50Mhz has proven unreliable without adding some delay to the sampling of the input data. I'm working in improving this, in the meantime, I'm leaving the default set at 25 Mhz. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	5ae5f76558	arty/nexys-video: Update XDC ... The DRAM related pins have some small changes in LiteX, so resync and add the false path information as well. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	2cef3005cd	fpga: Hookup nexys-video to litedram ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	6 years ago
Anton Blanchard	20674e0d65	Add SPI configuration to Xilinx constraint files ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago
Anton Blanchard	a53ad60014	Rename a few reset signals ... clk -> ext_clk reset_n -> ext_rst reset -> rst Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago
Anton Blanchard	5a29cb4699	Initial import of microwatt ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago