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2 Commits (7aaed5abd512897fc47eef8d0624cc3d4de6cb93)

Author SHA1 Message Date
Benjamin Herrenschmidt 3ac1dbc737 Share soc.vhdl between FPGA and sim 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt 48b689b665 Add simulated UART design 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>