4 Commits (7aaed5abd512897fc47eef8d0624cc3d4de6cb93)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	9961d70dfb	Improve PLL/MMCM clocks configuration ... We can now pass both the input clock and target clock frequency via generics. Add support for both 50Mhz and 100Mhz target freqs for both cases. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	6 years ago
Benjamin Herrenschmidt	79b0b9a046	Fix PLL reset signal name in toplevel ... It shouldn't have a _n suffix, it's active positive. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	6 years ago
Benjamin Herrenschmidt	3ac1dbc737	Share soc.vhdl between FPGA and sim ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	6 years ago
Benjamin Herrenschmidt	a69a93b466	Split FPGA toplevel from soc ... This will be useful when we start needing different toplevels for different boards. We keep the reset and clock generators in the toplevel as they will eventually be taken over by litedram when we integrate it, and they are more likely to change on different system types. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	6 years ago