895 Commits (74254bf11a5b523a3f48c2473e387dc7c8a52c32)

 

All Branches   

Search

Author	SHA1	Message	Date
Anton Blanchard	021d427d3f	Stores need to wait for wishbone write ack ... I wasn't waiting to get a wishbone ack back on stores before continuing. This creates all sorts of problems when we add pipelining and send loads and stores down the pipe faster. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	c64bf23c1a	Merge pull request #21 from antonblanchard/xdc-update ... Add CONFIG_VOLTAGE and CFGBVS entries	5 years ago
Anton Blanchard	63295526ad	Add CONFIG_VOLTAGE and CFGBVS entries ... Remove a couple of warnings from Vivado. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	03fd06deaf	Rework SOC reset ... The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	a53ad60014	Rename a few reset signals ... clk -> ext_clk reset_n -> ext_rst reset -> rst Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	e39400681b	Merge pull request #18 from mikey/verific ... Fix verific script with new VHDL files	5 years ago
Michael Neuling	83d773090e	Fix verific script with new VHDL files ... This really needs to be auto generated, but here we are. Signed-off-by: Michael Neuling <mikey@neuling.org>	5 years ago
Anton Blanchard	a15eb4e28d	Merge pull request #17 from antonblanchard/writeback-signal ... Use a better input signal in writeback	5 years ago
Anton Blanchard	147b259691	Use a better input signal in writeback ... w_in comes from the execution unit, it makes more sense to call it e_in. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	3f59396907	Merge pull request #16 from antonblanchard/decode2_rework2 ... Rework decode2	5 years ago
Anton Blanchard	5e140298a5	Rework decode2 ... The decode2 stage was spaghetti code and needed cleaning up. Create a series of functions to pull fields from a ppc instruction and also a series of helpers to extract values for the execution units. As suggested by Paul, we should pass all signals to the execution units and only set the valid signal conditionally, which should use less resources. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	d1fdc286c4	Merge pull request #13 from mikey/dynamic-ranges ... Remove dynamic ranges from code	5 years ago
Michael Neuling	4d5abfb430	Remove dynamic ranges from code ... Some VHDL compilers like verific [1] don't like these, so let's remove them. Lots of random code changes, but passes make check. Also add basic script to run verific and generate verilog. 1. https://www.verific.com/ Signed-off-by: Michael Neuling <mikey@neuling.org>	5 years ago
Anton Blanchard	7a85e3877d	Merge pull request #10 from antonblanchard/arty-fix ... Arty A7 reset pin is C2	5 years ago
Anton Blanchard	5379b805ec	Arty A7 reset pin is C2 ... Use C2 for reset, and fix up a few whitespace issues. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	3819768d2a	Merge pull request #7 from riktw/fusesoc_arty_a7 ... Fusesoc arty a7	5 years ago
Anton Blanchard	5aba4e7346	Merge pull request #9 from antonblanchard/travis-fix ... A few Travis CI fixes	5 years ago
Anton Blanchard	6c8d28a642	A few Travis CI fixes ... - Switch to using ghdl/vunit:llvm, it's a smaller container - We need to "apt update" before installing packages Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
riktw	4ebd6fc1f7	Added support for building for Arty A7 boards	5 years ago
Anton Blanchard	f98370f9e6	Merge pull request #5 from antonblanchard/travis-test ... Add an initial travis.yml	5 years ago
Anton Blanchard	2ee269abdb	Add an initial travis.yml ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	0fd18c2455	Add srd and srw ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	73daacbcd4	Add sim only divw ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	95b9f19882	Fix ghdl build error with pp_soc_memory ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	1fa0b332ca	micropython only requires 512kB of BRAM ... Mikey points out that our stack grows down from 512kB and our heap is below that too, so we can reduce our BRAM requirements, which allowing some smaller FPGA boards to work. Not sure why I thought we were using memory between 512kB and 1MB. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	1aadee281d	Merge pull request #6 from mikey/gif ... Add pretty gif demo of MicroPython on Microwatt to README.md	5 years ago
Anton Blanchard	96787091a6	Add -Wall to CFLAGS ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Michael Neuling	d618171d13	Add pretty gif demo of MicroPython on Microwatt to README.md ... Signed-off-by: Michael Neuling <mikey@neuling.org>	5 years ago
Anton Blanchard	7277c6b5ab	Add missing argument to fprintf warning ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	77f1588a7f	Add some initial FPGA synthesis instructions ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	0a0ad9b384	Rebuild hello world assuming a 50MHz clock ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	c036363d8f	Merge pull request #3 from olofk/plle2 ... Add and use plle2 primitive for nexys boards	5 years ago
Olof Kindgren	12327034d6	Add and use plle2 primitive for nexys boards	5 years ago
Anton Blanchard	5b2984a15d	Merge pull request #4 from sharkcz/build ... don't cross compile when on Power	5 years ago
Dan Horák	2d7994dc12	don't cross compile when on Power	5 years ago
Anton Blanchard	8bc3e8ea0a	Add a simple hello_world example that also echos input ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	01e6b8f583	Merge pull request #2 from olofk/fusesoc_nexys_a7 ... Fusesoc nexys a7	5 years ago
Olof Kindgren	b9bf19f912	Added synthesis target ... The synth target can be used to analyze the core after synthesis without running P&R. Currently, the only edalize backends that support synthesis without P&R are vivado and icestorm, and icestorm needs yosys built with verific support to parse vhdl. To run synthesis only for a part, run fusesoc run --target=synth --tool=vivado microwatt --part=<part> where part is a valid Xilinx part such as xc7a100tcsg324-1	5 years ago
Olof Kindgren	250d09ed2d	Add Nexys Video support	5 years ago
Olof Kindgren	5e56b14125	Add FuseSoC core description file with Nexys A7 support	5 years ago
Olof Kindgren	abca85b034	Add constraint file for Nexys A7	5 years ago
Olof Kindgren	e8ad9bed10	Expose ram init file and memory size through toplevel	5 years ago
Olof Kindgren	b5bccc4c13	Add dummy clock generator	5 years ago
Anton Blanchard	37fe8b954c	Add a few more FPGA related files ... Add a temporary gcc patch to remove hardware divide instructions. Also add a firmware.hex file built with a gcc with the above patch. Right now micropython assumes 1MB of BRAM, which limits the FPGAs we can run on. We should be able to cut it down somewhat. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	5a29cb4699	Initial import of microwatt ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago