Commit Graph

980 Commits (71af8016da0c8183ddc63b1ea77ed87f436b3591)
 

Author SHA1 Message Date
Anton Blanchard 3819768d2a
Merge pull request from riktw/fusesoc_arty_a7
Fusesoc arty a7
Anton Blanchard 5aba4e7346
Merge pull request from antonblanchard/travis-fix
A few Travis CI fixes
Anton Blanchard 6c8d28a642 A few Travis CI fixes
- Switch to using ghdl/vunit:llvm, it's a smaller container
- We need to "apt update" before installing packages

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
riktw 4ebd6fc1f7 Added support for building for Arty A7 boards
Anton Blanchard f98370f9e6
Merge pull request from antonblanchard/travis-test
Add an initial travis.yml
Anton Blanchard 2ee269abdb Add an initial travis.yml
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 0fd18c2455 Add srd and srw
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 73daacbcd4 Add sim only divw
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 95b9f19882 Fix ghdl build error with pp_soc_memory
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 1fa0b332ca micropython only requires 512kB of BRAM
Mikey points out that our stack grows down from 512kB and our
heap is below that too, so we can reduce our BRAM requirements,
which allowing some smaller FPGA boards to work. Not sure why
I thought we were using memory between 512kB and 1MB.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 1aadee281d
Merge pull request from mikey/gif
Add pretty gif demo of MicroPython on Microwatt to README.md
Anton Blanchard 96787091a6 Add -Wall to CFLAGS
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling d618171d13 Add pretty gif demo of MicroPython on Microwatt to README.md
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard 7277c6b5ab Add missing argument to fprintf warning
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 77f1588a7f Add some initial FPGA synthesis instructions
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 0a0ad9b384 Rebuild hello world assuming a 50MHz clock
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard c036363d8f
Merge pull request from olofk/plle2
Add and use plle2 primitive for nexys boards
Olof Kindgren 12327034d6 Add and use plle2 primitive for nexys boards
Anton Blanchard 5b2984a15d
Merge pull request from sharkcz/build
don't cross compile when on Power
Dan Horák 2d7994dc12 don't cross compile when on Power
Anton Blanchard 8bc3e8ea0a Add a simple hello_world example that also echos input
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 01e6b8f583
Merge pull request from olofk/fusesoc_nexys_a7
Fusesoc nexys a7
Olof Kindgren b9bf19f912 Added synthesis target
The synth target can be used to analyze the core after synthesis
without running P&R. Currently, the only edalize backends that
support synthesis without P&R are vivado and icestorm, and icestorm
needs yosys built with verific support to parse vhdl.

To run synthesis only for a part, run

fusesoc run --target=synth --tool=vivado microwatt --part=<part>

where part is a valid Xilinx part such as xc7a100tcsg324-1
Olof Kindgren 250d09ed2d Add Nexys Video support
Olof Kindgren 5e56b14125 Add FuseSoC core description file with Nexys A7 support
Olof Kindgren abca85b034 Add constraint file for Nexys A7
Olof Kindgren e8ad9bed10 Expose ram init file and memory size through toplevel
Olof Kindgren b5bccc4c13 Add dummy clock generator
Anton Blanchard 37fe8b954c Add a few more FPGA related files
Add a temporary gcc patch to remove hardware divide instructions.

Also add a firmware.hex file built with a gcc with the above patch.

Right now micropython assumes 1MB of BRAM, which limits the FPGAs
we can run on. We should be able to cut it down somewhat.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 5a29cb4699 Initial import of microwatt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>