microwatt

Commit Graph

Author	SHA1	Message	Date
Anton Blanchard	6cbf456388	SOC memory wishbone should clear ACK regardless of STB The memory wishbone doesn't clear ACK and move the state machine on until STB is de-asserted. This seems like it isn't compliant with the spec and results in a maximum throughput of 1 transfer every 3 cycles. Fixing this improves the situation to one transfer every 2 cycles. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago
Benjamin Herrenschmidt	d21ef5836d	Pass wishbone record to bram memory module (And rename it to mw_soc_memory). This makes soc.vhdl simpler and provides the same interface as the simulated memory, which will help when sharing soc.vhdl with sim later Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	6 years ago

Author

SHA1

Message

Date

Anton Blanchard

6cbf456388

SOC memory wishbone should clear ACK regardless of STB

The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

Benjamin Herrenschmidt

d21ef5836d

Pass wishbone record to bram memory module

(And rename it to mw_soc_memory).

This makes soc.vhdl simpler and provides the same interface as
the simulated memory, which will help when sharing soc.vhdl
with sim later

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

2 Commits (6cae10eebd043979a0b1cec0db0f1024e979abd4)