3 Commits (63f10450a6e04d57c8cb3e11a9ddc7d7f95a21ac)

Author	SHA1	Message	Date
Paul Mackerras	2843c99a71	MMU: Implement reading of the process table ... This adds the PID register and repurposes SPR 720 as the PRTBL register, which points to the base of the process table. There doesn't seem to be any point to implementing the partition table given that we don't have hypervisor mode. The MMU caches entry 0 of the process table internally (in pgtbl3) plus the entry indexed by the value in the PID register (pgtbl0). Both caches are invalidated by a tlbie[l] with RIC=2 or by a move to PRTBL. The pgtbl0 cache is invalidated by a move to PID. The dTLB and iTLB are cleared by a move to either PRTBL or PID. Which of the two page table root pointers is used (pgtbl0 or pgtbl3) depends on the MSB of the address being translated. Since the segment checking ensures that address(63) = address(62), this is sufficient to map quadrants 0 and 3. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	5 years ago
Paul Mackerras	bee0c94fb4	tests/privileged: Update for instruction translation ... Since setting MSR[PR] = 1 forces instruction translation on, we need to set up translations for the problem state code to use. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	5 years ago
Paul Mackerras	10f4be4309	tests: Add a test for privileged instruction interrupts ... This adds a test that tries to execute various privileged instructions with MSR[PR] = 1. This also incidentally tests some of the MSR bit manipulations. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	5 years ago