4 Commits (60e5f7b9587cc3fd48716236153d3272fae70b25)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	ecaa5e2fb2	dcache: Rework RAM wrapper to synthetize better on Xilinx ... The global wr_en signal is causing Vivado to generate two TDP (True Dual Port) block RAMs instead of one SDP (Simple Dual Port) for each cache way. Remove it and instead apply a AND to the individual byte write enables. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	174378b190	dcache: Introduce an extra cycle latency to make timing ... This makes the BRAMs use an output buffer, introducing an extra cycle latency. Without this, Vivado won't make timing at 100Mhz. We stash all the necessary response data in delayed latches, the extra cycle is NOT a state in the state machine, thus it's fully pipelined and doesn't involve stalling. This introduces an extra non-pipelined cycle for loads with update to avoid collision on the writeback output between the now delayed load data and the register update. We could avoid it by moving the register update in the pipeline bubble created by the extra update state, but it's a bit trickier, so I leave that for a latter optimization. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	a38ae503ff	cache_ram: Add write-enables ... They will be needed by the dcache Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	b56b46b7d1	icache: Set associative icache ... This adds support for set associativity to the icache. It can still be direct mapped by setting NUM_WAYS to 1. The replacement policy uses a simple tree-PLRU for each set. This is only lightly tested, tests pass but I have to double check that we are using the ways effectively and not creating duplicates. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago