4 Commits (5e90133b61c8a07fd0ccf7dac864daa8500c0f3a)

Author	SHA1	Message	Date
Anton Blanchard	3f1e2b3a4f	Merge pull request #265 from antonblanchard/another-spi-rxtx-reset-issu ... Fix another reset issue in spi_rxtx	4 years ago
Anton Blanchard	a0eb4eec17	Fix another reset issue in spi_rxtx ... counter was X state after reset, initialize it. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Anton Blanchard	bf9a446e3f	Reset cmd_ready_o in spi_txrx ... Initialize bit_count so that cmd_ready_o isn't X state immediately after reset. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Benjamin Herrenschmidt	cc4dcb3597	spi: Add SPI Flash controller ... This adds an SPI flash controller which supports direct memory-mapped access to the flash along with a manual mode to send commands. The direct mode can be set via generic to default to single wire or quad mode. The controller supports normal, dual and quad accesses with configurable commands, clock divider, dummy clocks etc... The SPI clock can be an even divider of sys_clk starting at 2 (so max 50Mhz with our typical Arty designs). A flash offset is carried via generics to syscon to tell SW about which portion of the flash is reserved for the FPGA bitfile. There is currently no plumbing to make the CPU reset past that address (TBD). Note: Operating at 50Mhz has proven unreliable without adding some delay to the sampling of the input data. I'm working in improving this, in the meantime, I'm leaving the default set at 25 Mhz. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	4 years ago