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5 Commits (560a6f6b18586b73986bca9dcb3cb305b182bc6e)

Author SHA1 Message Date
Benjamin Herrenschmidt bf1b98b958 litedram: Add support for booting without BRAM 
This adds an option to disable the main BRAM and instead copy a
payload stashed along with the init code in the secondary BRAM
into DRAM and boot from there

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt 573b6b4bc4 soc: Rework interconnect 
This changes the SoC interconnect such that the main 64-bit wishbone out
of the processor is first split between only 3 slaves (BRAM, DRAM and a
general "IO" bus) instead of all the slaves in the SoC.

The IO bus leg is then latched and down-converted to 32 bits data width,
before going through a second address decoder for the various IO devices.

This significantly reduces routing and timing pressure on the main bus,
allowing to get rid of frequent timing violations when synthetizing on
small'ish FPGAs such as the Artix-7 35T found on the original Arty board.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt 8d64090a68 sw: Add full memory map to .h and use it for litedram .lds 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt c19b5b8cc7 litedram: Update to new LiteX/LiteDRAM version 
Things have changed a bit in upstream LiteX. LiteDRAM now exposes a
wishbone for the CSRs for example.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt 33de131384 Add microwatt_soc.h and io.h include file 
This contains C definitions for various Microwatt internal MMIOs
and a set of accessors.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago