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microwatt
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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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6 Commits (559b3bcf2d700cb189f5fa3a78639c09baae88ff)

Author SHA1 Message Date
Benjamin Herrenschmidt 1a63c39704 Make it possible to change wishbone address size 
All that needs to be changed now is the size in wishbone_types.vhdl
and the address decoder in soc.vhdl

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Anton Blanchard 1d5e8c2eb4 Reformat simple_ram_behavioural 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Benjamin Herrenschmidt 3ac1dbc737 Share soc.vhdl between FPGA and sim 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Anton Blanchard dce2e06f4c Don't send out X state from the memory behavioural 
Just send out all 1s.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 5d82af5204 Silence some loadstore related debug 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago