3 Commits (4ad5ab92038412d46ef0dc2477e079219b8d7ced)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	9b458a9aa6	dmi: Add ASYNC_REG attribute on synchronizers (#200) ... This tells Vivado to keep them close among other things Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	5f28109957	Don't reset JTAG request register asynchronously ... There's no point and it causes Vivado to spew a pile of warnings Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	ee52fd4d80	Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs ... This adds a simple bus that can be mastered from an external system via JTAG, which will be used to hookup various debug modules. It's loosely based on the RiscV model (hence the DMI name). The module currently only supports hooking up to a Xilinx BSCANE2 but it shouldn't be too hard to adapt it to support different TAPs if necessary. The JTAG protocol proper is not exactly the RiscV one at this point, though I might still change it. This comes with some sim variants of Xilinx BSCANE2 and BUFG and a test bench. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago