8 Commits (48f260761b72924030abc8ff6bc1a727f2dbf331)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	365f60b693	simple_ram: Turn on pipelining ... With a 1 cycle delay Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	37acb35773	simple_ram: Add pipelining support ... The generic PIPELINE_DEPTH can be set to 0 to keep it operating as a non-pipelined slave, or a larger value indicating the amount of extra cycles between requests and acks. It will always generate a valid stall signal, so it can be used in either mode with a pipelined master (but only in non-pipelined mode with a non-pipelined master). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	1a63c39704	Make it possible to change wishbone address size ... All that needs to be changed now is the size in wishbone_types.vhdl and the address decoder in soc.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Anton Blanchard	1d5e8c2eb4	Reformat simple_ram_behavioural ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Benjamin Herrenschmidt	3ac1dbc737	Share soc.vhdl between FPGA and sim ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Anton Blanchard	dce2e06f4c	Don't send out X state from the memory behavioural ... Just send out all 1s. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	5d82af5204	Silence some loadstore related debug ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	5a29cb4699	Initial import of microwatt ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago