3 Commits (39220be311939149062ca2f0570ce9564c4cc5cd)

Author	SHA1	Message	Date
Anton Blanchard	a750365ffa	Remove some FPGA style signal inits ... These don't work on the ASIC flow, so remove them and initialise them explicitly where required. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	3 years ago
Paul Mackerras	ca4eb46aea	Make wishbone addresses be in units of doublewords or words ... This makes the 64-bit wishbone buses have the address expressed in units of doublewords (64 bits), and similarly for the 32-bit buses the address is in units of words (32 bits). This is to comply with the wishbone spec. Previously the addresses on the wishbone buses were in units of bytes regardless of the bus data width, which is not correct and caused problems with interfacing with externally-generated logic. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	3 years ago
Paul Mackerras	f06ffcf9b7	Add a GPIO controller and use it to drive the shield I/O pins on the Arty ... This adds a GPIO controller which provides 32 bits of I/O. The registers are modelled on the set used by the gpio-ftgpio010.c driver in the Linux kernel. Currently there is no interrupt capability implemented, though an interrupt line from the GPIO subsystem to the XICS has been connected. For the Arty A7 board, GPIO lines 0 to 13 are connected to the pins labelled IO0 to IO13 on the "shield" connector, GPIO lines 14 to 29 connect to IO26 to IO41, GPIO line 30 connects to the pin labelled A (aka IO42), and GPIO line 31 is connected to LED 7. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	4 years ago