matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
737 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '2cb1d7671e'
${ noResults }
Commit Graph

3 Commits (2cb1d7671ed5e4909b3d810a0e4461fdc22db12a)

Author SHA1 Message Date
Jordan Niethe 737ebd92f5 tests: Add tests for the PVR 
The PVR is a privileged read-only SPR. Test reading and writing in both
supervisor and problem state. In supervisor state reading returns
microwatt's assigned PVR number and writing is a noop. In problem state
both reading and writing cause privileged instruction interrupts.

Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
 5 years ago
Benjamin Herrenschmidt e3941109af console: Cleanup console API 
Use a more generic console_init() instead of potato_uart_init(),
and do the same for interrupt control. There should be no
change in behaviour.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Shawn Anastasio 8b161c6dc6 Add a new misc test suite with addpcis tests 
The two tests obtain NIA with bl+mflr+addi and then compare it
against addpcis with the minimum and maximum immediate operand values.

They were also tested on a real POWER9 system (in userspace) for good
measure.

Signed-off-by: Shawn Anastasio <shawn@anastas.io>
 6 years ago