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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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4 Commits (1d66e1f981b4447f58e4506718740b1219d96644)

Author SHA1 Message Date
Benjamin Herrenschmidt 1d66e1f981 Rework wishbone slave address decoding 
Don't make it synchronous, no latches

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt c97b080d8c Move wishbone arbiter out of the core 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt 310a56c076 Re-indent and reformat soc.vhdl 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt a69a93b466 Split FPGA toplevel from soc 
This will be useful when we start needing different toplevels for
different boards.

We keep the reset and clock generators in the toplevel as they will
eventually be taken over by litedram when we integrate it, and they
are more likely to change on different system types.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago