matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
998 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '18eb029f0a'
${ noResults }
Commit Graph

3 Commits (18eb029f0a6f4df27d9c83de53014514b51dd4d2)

Author SHA1 Message Date
Anton Blanchard c0f7f54276 litedram: Regenerate from upstream litex 
This adds Joel's sdcard feature reporting to the firmware.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 780d6c754c litedram: Regenerate from upstream litex 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Benjamin Herrenschmidt dbb137437c acorn: Add support for the Acorn CLE 215+ 
This is a NiteFury based PCIe M2 form-factor board originally
used for mining. It contains a speed grade 2 Artix 7 200T,
1GB of DDR3 and 32MB of flash.

The serial port is routed to pin 2 (RX) and 3 (TX) of the P2
connector (pin 1 is GND).

Note: Only 16MB of flash is currently usable until code is added
to configure the flash controller to use 4-bytes address commands
on that part.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago