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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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3 Commits (0fb89672902bbe7c56c419b57a5e96fc1d5cb202)

Author SHA1 Message Date
Benjamin Herrenschmidt 9b458a9aa6
dmi: Add ASYNC_REG attribute on synchronizers (#200) 
This tells Vivado to keep them close among other things

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt 5f28109957 Don't reset JTAG request register asynchronously 
There's no point and it causes Vivado to spew a pile of warnings

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt ee52fd4d80 Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs 
This adds a simple bus that can be mastered from an external
system via JTAG, which will be used to hookup various debug
modules.

It's loosely based on the RiscV model (hence the DMI name).

The module currently only supports hooking up to a Xilinx BSCANE2
but it shouldn't be too hard to adapt it to support different TAPs
if necessary.

The JTAG protocol proper is not exactly the RiscV one at this point,
though I might still change it.

This comes with some sim variants of Xilinx BSCANE2 and BUFG and a
test bench.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago