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fpu-init
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dcache-unused-sig
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divider-init
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
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dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
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1 Commits (0cb0f7877744851f2efc0ddcb45a031603173da6)

Author SHA1 Message Date
Paul Mackerras 24a4a796ce execute: Consolidate count-leading/trailing-zeroes implementations 
This adds combinatorial logic that does 32-bit and 64-bit count
leading and trailing zeroes in one unit, and consolidates the
four instructions under a single OP_CNTZ opcode.

This saves 84 slice LUTs on the Arty A7-100.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago