Commit Graph

1083 Commits (0b39947f8d9bcca1143207ecb0789c90198170d3)
 

Author SHA1 Message Date
Lars Asplund 0865704e21 Run VUnit tests in CI
Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
3 years ago
Lars Asplund 0940b8a9d3 Organized VUnit testbenches into test cases.
Several of the testbenches have stimuli code divided into sections preceded with a header comment explaining
what is being tested. These sections have been made into VUnit test cases. The default behavior of VUnit is
to run each test case in a separate simulation which comes with a number of benefits:

* A failing test case doesn't prevent other test cases to be executed
* Test cases are independent. A test case cannot fail as a side-effect to a problem with another test case
* Test execution can be more parallelized and the overall test execution time reduced

Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
3 years ago
Lars Asplund 08c0c4c1b4 Make core testbenches recognized by VUnit
This commit also removes the dependencies these testbenches have on VHPIDIRECT.
The use of VHPIDIRECT limits the number of available simulators for the project. Rather than using
foreign functions the testbenches can be implemented entirely in VHDL where equivalent functionality exists.
For these testbenches the VHPIDIRECT-based randomization functions were replaced with VHDL-based functions.

The testbenches recognized by VUnit can be executed in parallel threads for better simulation performance using
the -p option to the run.py script

Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
3 years ago
Lars Asplund 41d57e6148 Added VUnit run script.
The VUnit run script will find all VHDL files based on given search patterns, figure out their dependencies, and support incremental compile based on the dependencies.
The same script is used for all VUnit supported simulators. Supporting several simulators simplifies the adoption of this project.

At this point only compilation is performed. Coming commits will enable simulation of VHDL testbenches.

Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
3 years ago
Michael Neuling 84473eda1b Merge pull request #277 from paulus/gpio
A few cleanups. GPIO IRQ number is now 4 as 3 is now taken by the SD card.
4 years ago
Michael Neuling 7f44980611
Merge pull request #287 from paulusmack/master
Add SD card interface
4 years ago
Paul Mackerras d8ea64675a
Merge pull request #278 from shenki/openocd-v0.11
Add files for openocd v0.11
4 years ago
Joel Stanley 0d4a0bab6e openocd: Fix verify command for v0.10
v0.11 uses verify_image, which is not supported by v0.11. Use the old
verify_bank for v0.10.

Signed-off-by: Joel Stanley <joel@jms.id.au>
4 years ago
Paul Mackerras 21ed730514 arty_a7: Add litesdcard interface
This adds litesdcard.v generated from the litex/litesdcard project,
along with logic in top-arty.vhdl to connect it into the system.
There is now a DMA wishbone coming in to soc.vhdl which is narrower
than the other wishbone masters (it has 32-bit data rather than
64-bit) so there is a widening/narrowing adapter between it and the
main wishbone master arbiter.

Also, litesdcard generates a non-pipelined wishbone for its DMA
connection, which needs to be converted to a pipelined wishbone.  We
have a latch on both the incoming and outgoing sides of the wishbone
in order to help make timing (at the cost of two extra cycles of
latency).

litesdcard generates an interrupt signal which is wired up to input 3
of the ICS (IRQ 19).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 231003f7c7 icache: Snoop writes to memory by other agents
This makes the icache snoop writes to memory in the same way that the
dcache does, thus making DMA cache-coherent for the icache as well as
the dcache.

This also simplifies the logic for the WAIT_ACK state by removing the
stbs_done variable, since is_last_row(r.store_row, r.end_row_ix) can
only be true when stbs_done is true.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 4c11c9c661 dcache: Simplify logic in RELOAD_WAIT_ACK state
Since the expression is_last_row(r1.store_row, r1.end_row_ix) can only
be true when stbs_done is true, there is no need to include stbs_done
in the expression for the reload being completed, and hence no need to
compute stbs_done in the RELOAD_WAIT_ACK state.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras eb7eba2d92 dcache: Snoop writes to memory by other agents
This adds a path where the wishbone that goes out to memory and I/O
also gets fed back to the dcache, which looks for writes that it
didn't initiate, and invalidates any cache line that gets written to.

This involves a second read port on the cache tag RAM for looking up
the snooped writes, and effectively a second write port on the cache
valid bit array to clear bits corresponding to snoop hits.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 4a8ab3331c
Merge pull request #283 from antonblanchard/whitespace
Fix a few whitespace issues.  Only changes whitespace and comments.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Antony Vennard d9a398dc81
Update documentation. (#280)
Update documentation to reference fusesoc init for Xilinx boards, for
those like me who have never used fusesoc before. Add a reference to the
board files for Digilent boards and comment on perhaps installing them
for other boards as appropriate.

Signed-off-by: Antony Vennard <antony@vennard.ch>
4 years ago
Anton Blanchard 6d827b9358
Merge pull request #286 from antonblanchard/Makefile-cleanup-3
A few more Makefile cleanups
4 years ago
Anton Blanchard be11ebbf6d Remove unused GHDL_TARGET_GENERICS
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 33c78f9282 Move verilator --trace flag into VERILATOR_FLAGS
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 0af906232f
Merge pull request #285 from antonblanchard/Makefile-cleanup-2
A few Makefile cleanups
4 years ago
Anton Blanchard 5cc5d8f030
Merge pull request #281 from antonblanchard/cache-tlb-parameters
Pass icache/dcache/tlb parameters down from soc
4 years ago
Anton Blanchard 4ab36517ec Remove -frelaxed
We don't appear to need this any more, so remove it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 561d6af6f0 Use VERILATOR_FLAGS/VERILATOR_CFLAGS on all verilator targets
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 75da4156fe Remove core_files from soc_files and fpga_files
We were already including the core_files at the same time as the
soc_files in many targets.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard ef01fa32bd
Merge pull request #284 from antonblanchard/boot-clocks
Allow SPI BOOT_CLOCKS to be overridden by top level
4 years ago
Anton Blanchard af462f0ca9 Reformat spi_flash_ctrl
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 2db89628ab Reformat control
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 21f482f967 Reformat testbenches
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 0d86580ac7 Reformat writeback
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard f67b143165 Reformat plru
Also fix a typo

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard c76e638a77 Reformat rotator
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 601f3211be Reformat divider
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard bf96279ff1 Reformat countzero
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard af7e330d69 Reformat cr_file
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 9208276aa2 Reformat register_file
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 74254bf11a Reformat cache_ram
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 91a53d8001 Allow SPI BOOT_CLOCKS to be overridden by top level
Our SPI controller sends 8 dummy clocks at boot which Ben
added for some Xilinx boards. This should be harmless but
it is confusing the flash testbench in the Caravel project.

Add a parameter so it can be overridden at the top level.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 2d21b95f87 Pass icache/dcache/tlb parameters down from soc
We want much smaller caches and tlbs when building for sky130, so
allow the toplevel file to override the defaults.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Paul Mackerras f06a0f4e5a arty: Update GPIOs for Boxarty BMC
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Joel Stanley 24a34899b4 Add files for openocd v0.11
The protocol used by the spi bridge firmware changed as of openocd
v0.11. As this is the version packaged by Debian Bullseye, add the
firmware for convince.

Signed-off-by: Joel Stanley <joel@jms.id.au>
4 years ago
Paul Mackerras f06ffcf9b7 Add a GPIO controller and use it to drive the shield I/O pins on the Arty
This adds a GPIO controller which provides 32 bits of I/O.  The
registers are modelled on the set used by the gpio-ftgpio010.c driver
in the Linux kernel.  Currently there is no interrupt capability
implemented, though an interrupt line from the GPIO subsystem to the
XICS has been connected.

For the Arty A7 board, GPIO lines 0 to 13 are connected to the pins
labelled IO0 to IO13 on the "shield" connector, GPIO lines 14 to 29
connect to IO26 to IO41, GPIO line 30 connects to the pin labelled A
(aka IO42), and GPIO line 31 is connected to LED 7.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Michael Neuling 6523acc743
Merge pull request #274 from mikey/read-sprs
Fix reading DSISR/DAR before writing and add a test to read from all SPRs
4 years ago
Anton Blanchard d26a157cd7 Add a test to read from all SPRs
Make sure the SPRs are initialized and we can't read X state.

(Mikey: rebased and added console/bin file for testing)

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 4c21587c4d Fix DAR/DSISR reading before they are written
If the DAR and DSISR are read before they are written, we assert with:

  register_file.vhdl:55:25:@60195ns:(report note): Writing GPR 09 00000000XXXXXXXX
  register_file.vhdl:61:17:@60195ns:(assertion failure): Assertion violation

This initialises DAR/DSISR to avoid this.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 6c7689052d
Merge pull request #269 from paulusmack/pipeline
Rework load/store pipeline to achieve one load/store per cycle throughput
4 years ago
Michael Neuling 9a6a7e9fe5
Merge pull request #268 from paulusmack/btc
Implement branch target cache
4 years ago
Michael Neuling 7652452367
Merge pull request #273 from antonblanchard/wishbone-checking
Add some wishbone checking
4 years ago
Michael Neuling c4e3ade4ed
Merge pull request #267 from paulusmack/master
Improve architecture compliance and other miscellaneous changes
4 years ago
Anton Blanchard 481f3cdfea Add some wishbone checking
Check that stb, cyc and ack are never undefined. While not really needed
here, this also tests if --pragma synthesis_off/--pragma synthesis_on
works on all the tools we use.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Paul Mackerras 17fd069640 core: Allow multiple loadstore instructions to be in flight
The idea here is that we can have multiple instructions in progress at
the same time as long as they all go to the same unit, because that
unit will keep them in order.  If we get an instruction for a
different unit, we wait for all the previous instructions to finish
before executing it.  Since the loadstore unit is the only one that is
currently pipelined, this boils down to saying that loadstore
instructions can go ahead while l_in.in_progress = 1 but other
instructions have to wait until it is 0.

This gives a 2% increase on coremark performance on the Arty A7-100
(from ~190 to ~194).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras f583d088b7 loadstore: Convert to 3-stage pipeline
This makes loadstore use a 3-stage pipeline.  For now, only one
instruction goes through the pipe at a time.  Completion and writeback
are still combinatorial off the valid signal back from the dcache, so
performance should be the same as before.  In future it should be able
to sustain one load or store per cycle provided they hit in the
dcache.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras f636bb7c39 dcache: Fix bugs in pipelined operation
This fixes two bugs which show up when multiple operations are in
flight in the dcache, and adds a 'hold' input which will be needed
when loadstore1 is pipelined.

The first bug is that dcache needs to sample the data for a store on
the cycle after the store request comes in even if the store request
is held up because of a previous request (e.g. if the previous request
is a load miss or a dcbz).

The second bug is that a load request coming in for a cache line being
refilled needs to be handled immediately in the case where it is for
the row whose data arrives on the same cycle.  If it is not, then it
will be handled as a separate cache miss and the cache line will be
refilled again into a different way, leading to two ways both being
valid for the same tag.  This can lead to data corruption, in the
scenario where subsequent writes go to one of the ways and then that
way gets displaced but the other way doesn't.  This bug could in
principle show up even without having multiple operations in flight in
the dcache.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago