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fpu-init
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divider-init
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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remove-potato-uart
cache-tlb-parameters-2
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2 Commits (remove-potato-uart)

Author SHA1 Message Date
Paul Mackerras 18120f153d MMU: Implement a vestigial partition table 
This implements a 1-entry partition table, so that instead of getting
the process table base address from the PRTBL SPR, the MMU now reads
the doubleword pointed to by the PTCR register plus 8 to get the
process table base address.  The partition table entry is cached.

Having the PTCR and the vestigial partition table reduces the amount
of software change required in Linux for Microwatt support.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago
Anton Blanchard d26a157cd7 Add a test to read from all SPRs 
Make sure the SPRs are initialized and we can't read X state.

(Mikey: rebased and added console/bin file for testing)

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
 5 years ago