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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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3 Commits (cache-tlb-parameters-2)

Author SHA1 Message Date
Anton Blanchard ab86b58d95 Exit cleanly from testbench on success 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Paul Mackerras e08ca4ab8e countzero: Add a register to help make timing 
This adds a register in the middle of the countzero computation,
so that we now have two cycles to count leading or trailing zeroes
instead of just one.  Execute1 now outputs a one-cycle stall signal
when it encounters a cntlz* or cnttz* instruction.  With this,
the countzero path no longer fails timing on the Artix-7 at 100MHz.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago
Paul Mackerras 4396eddc31 countzero: Add a testbench 
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago