microwatt

Commit Graph

Author	SHA1	Message	Date
Anton Blanchard	bc0f7cf236	Rename 'do' signal to avoid verilator System Verilog warning Experimenting with using ghdl to do VHDL to Verilog conversion (instead of ghdl+yosys), verilator complains that a signal is a SystemVerilog keyword: %Error: microwatt.v:15013:18: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language. We could probably make this go away by disabling SystemVerilog, but it's easy to rename the signal in question. Rename di at the same time. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	3 years ago
Anton Blanchard	7994b98404	Fix some whitespace issues Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	3 years ago
Benjamin Herrenschmidt	8e0389b973	ram: Rework main RAM interface This replaces the simple_ram_behavioural and mw_soc_memory modules with a common wishbone_bram_wrapper.vhdl that interfaces the pipelined WB with a lower-level RAM module, along with an FPGA and a sim variants of the latter. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago

Author

SHA1

Message

Date

Anton Blanchard

bc0f7cf236

Rename 'do' signal to avoid verilator System Verilog warning

Experimenting with using ghdl to do VHDL to Verilog conversion (instead
of ghdl+yosys), verilator complains that a signal is a SystemVerilog
keyword:

%Error: microwatt.v:15013:18: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.
        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.

We could probably make this go away by disabling SystemVerilog, but
it's easy to rename the signal in question. Rename di at the same
time.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

Anton Blanchard

7994b98404

Fix some whitespace issues

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

Benjamin Herrenschmidt

8e0389b973

ram: Rework main RAM interface

This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

3 Commits (boxarty-20211011)