flash-arty: Re-add support for running from any path

The changes in d3c274d01e ("flash-arty: Add support for specifying the file type")
added a local jtagspi.cfg, which meant openocd must be run from the root
of the microwatt directory.

This puts the content into the xilinx-xc7.cfg so the script can be used
from any path again.

Signed-off-by: Joel Stanley <joel@jms.id.au>

openocd/jtagspi.cfg

@@ -1,48 +1 @@
-set _USER1 0x02
 
-if { [info exists JTAGSPI_IR] } {
-	set _JTAGSPI_IR $JTAGSPI_IR
-} else {
-	set _JTAGSPI_IR $_USER1
-}
-
-if { [info exists DR_LENGTH] } {
-	set _DR_LENGTH $DR_LENGTH
-} else {
-	set _DR_LENGTH 1
-}
-
-if { [info exists TARGETNAME] } {
-	set _TARGETNAME $TARGETNAME
-} else {
-	set _TARGETNAME $_CHIPNAME.proxy
-}
-
-if { [info exists FLASHNAME] } {
-	set _FLASHNAME $FLASHNAME
-} else {
-	set _FLASHNAME $_CHIPNAME.spi
-}
-
-target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
-flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR $_DR_LENGTH
-
-proc jtagspi_init {chain_id proxy_bit} {
-	# load proxy bitstream $proxy_bit and probe spi flash
-	global _FLASHNAME
-	pld load $chain_id $proxy_bit
-	reset halt
-	flash probe $_FLASHNAME
-}
-
-proc jtagspi_program {bin addr {type ""} } {
-	# write and verify binary file $bin at offset $addr
-	global _FLASHNAME
-	if { $type eq "" } {
-		flash write_image erase $bin $addr
-		flash verify_bank $_FLASHNAME $bin $addr
-	} else {
-		flash write_image erase $bin $addr $type
-		flash verify_bank $_FLASHNAME $bin $addr $type
-	}
-}

openocd/xilinx-xc7.cfg

@@ -3,10 +3,61 @@ ftdi_vid_pid 0x0403 0x6010
 ftdi_channel 0
 ftdi_layout_init 0x00e8 0x60eb
 reset_config none
+adapter_khz 25000
 
 source [find cpld/xilinx-xc7.cfg]
-source openocd/jtagspi.cfg
-adapter_khz 25000
+
+# From jtagspi.cfg with modification to support
+# specifying file type
+set _USER1 0x02
+
+if { [info exists JTAGSPI_IR] } {
+	set _JTAGSPI_IR $JTAGSPI_IR
+} else {
+	set _JTAGSPI_IR $_USER1
+}
+
+if { [info exists DR_LENGTH] } {
+	set _DR_LENGTH $DR_LENGTH
+} else {
+	set _DR_LENGTH 1
+}
+
+if { [info exists TARGETNAME] } {
+	set _TARGETNAME $TARGETNAME
+} else {
+	set _TARGETNAME $_CHIPNAME.proxy
+}
+
+if { [info exists FLASHNAME] } {
+	set _FLASHNAME $FLASHNAME
+} else {
+	set _FLASHNAME $_CHIPNAME.spi
+}
+
+target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
+flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR $_DR_LENGTH
+
+proc jtagspi_init {chain_id proxy_bit} {
+	# load proxy bitstream $proxy_bit and probe spi flash
+	global _FLASHNAME
+	pld load $chain_id $proxy_bit
+	reset halt
+	flash probe $_FLASHNAME
+}
+
+proc jtagspi_program {bin addr {type ""} } {
+	# write and verify binary file $bin at offset $addr
+	global _FLASHNAME
+	if { $type eq "" } {
+		flash write_image erase $bin $addr
+		flash verify_bank $_FLASHNAME $bin $addr
+	} else {
+		flash write_image erase $bin $addr $type
+		flash verify_bank $_FLASHNAME $bin $addr $type
+	}
+}
+# end jtagspi.cfg
 
 proc fpga_program {} {
     global _CHIPNAME