forked from cores/microwatt
				
			PMU: Fix PMC5/6 behaviour when MMCR0[PMCC] = 11
The architecture states that when MMCR0[PMCC] = 0b11, PMC5 and PMC6 are not part of the Performance Monitor, meaning that they are not controlled by bits in MMCRs, and counter negative conditions in PMCs 5 and 6 don't generate Performance Monitor alerts, exceptions or interrupts. It doesn't say that PMC5 and PMC6 are frozen in this case, so presumably they should continue to count run instructions and run cycles. This implements that behaviour. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>dcache-nc-fix
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