Merge pull request #229 from ozbenh/litedram

Litedram: Misc improvements and support for different DRAM geometries

core_dram_tb.vhdl

@@ -120,6 +120,8 @@ begin
         generic map(
             DRAM_ABITS => 24,
             DRAM_ALINES => 1,
+            DRAM_DLINES => 16,
+            DRAM_PORT_WIDTH => 128,
             PAYLOAD_FILE => DRAM_INIT_FILE,
             PAYLOAD_SIZE => ROM_SIZE
             )

dram_tb.vhdl

@@ -43,6 +43,8 @@ begin
         generic map(
             DRAM_ABITS => 24,
             DRAM_ALINES => 1,
+            DRAM_DLINES => 16,
+            DRAM_PORT_WIDTH => 128,
             PAYLOAD_FILE => DRAM_INIT_FILE,
             PAYLOAD_SIZE => DRAM_INIT_SIZE
             )
@@ -293,6 +295,43 @@ begin
             check_data(make_pattern(i));
         end loop;
 
+        report "Pre-fill a line";
+        a(11) := '1';
+        clr_acks;
+        wb_write(add_off(a,  0), x"1111111100000000", x"ff");
+        wb_write(add_off(a,  8), x"3333333322222222", x"ff");
+        wb_write(add_off(a, 16), x"5555555544444444", x"ff");
+        wb_write(add_off(a, 24), x"7777777766666666", x"ff");
+        wb_write(add_off(a, 32), x"9999999988888888", x"ff");
+        wb_write(add_off(a, 40), x"bbbbbbbbaaaaaaaa", x"ff");
+        wb_write(add_off(a, 48), x"ddddddddcccccccc", x"ff");
+        wb_write(add_off(a, 56), x"ffffffffeeeeeeee", x"ff");
+        wb_write(add_off(a, 64), x"1111111100000000", x"ff");
+        wb_write(add_off(a, 72), x"3333333322222222", x"ff");
+        wb_write(add_off(a, 80), x"5555555544444444", x"ff");
+        wb_write(add_off(a, 88), x"7777777766666666", x"ff");
+        wb_write(add_off(a, 96), x"9999999988888888", x"ff");
+        wb_write(add_off(a,104), x"bbbbbbbbaaaaaaaa", x"ff");
+        wb_write(add_off(a,112), x"ddddddddcccccccc", x"ff");
+        wb_write(add_off(a,120), x"ffffffffeeeeeeee", x"ff");
+        wait_acks(16);
+
+        report "Scattered from middle of line...";
+        clr_acks;
+        wb_read(add_off(a,24));
+        wb_read(add_off(a,32));
+        wb_read(add_off(a, 0));
+        wb_read(add_off(a,16));
+        wait_acks(4);
+        read_data(d);
+        assert d = x"7777777766666666" report "bad data (24), got " & to_hstring(d) severity failure;
+        read_data(d);
+        assert d = x"9999999988888888" report "bad data (32), got " & to_hstring(d) severity failure;
+        read_data(d);
+        assert d = x"1111111100000000" report "bad data (0), got " & to_hstring(d) severity failure;
+        read_data(d);
+        assert d = x"5555555544444444" report "bad data (16), got " & to_hstring(d) severity failure;
+
         std.env.finish;
     end process;
 end architecture;

fpga/top-arty.vhdl

@@ -341,6 +341,8 @@ begin
             generic map(
                 DRAM_ABITS => 24,
                 DRAM_ALINES => 14,
+                DRAM_DLINES => 16,
+                DRAM_PORT_WIDTH => 128,
                 PAYLOAD_FILE => RAM_INIT_FILE,
                 PAYLOAD_SIZE => PAYLOAD_SIZE
                 )

fpga/top-nexys-video.vhdl

@@ -258,6 +258,8 @@ begin
 	    generic map(
 		DRAM_ABITS => 25,
 		DRAM_ALINES => 15,
+                DRAM_DLINES => 16,
+                DRAM_PORT_WIDTH => 128,
                 PAYLOAD_FILE => RAM_INIT_FILE,
                 PAYLOAD_SIZE => PAYLOAD_SIZE
 		)

litedram/extras/litedram-wrapper-l2.vhdl

@@ -10,8 +10,10 @@ use work.helpers.all;
 
 entity litedram_wrapper is
     generic (
-	DRAM_ABITS     : positive;
-	DRAM_ALINES    : positive;
+	DRAM_ABITS      : positive;
+	DRAM_ALINES     : natural;
+	DRAM_DLINES     : natural;
+	DRAM_PORT_WIDTH : positive;
 
         -- Pseudo-ROM payload
         PAYLOAD_SIZE      : natural;    
@@ -63,10 +65,10 @@ entity litedram_wrapper is
         ddram_cas_n   : out std_ulogic;
         ddram_we_n    : out std_ulogic;
         ddram_cs_n    : out std_ulogic;
-        ddram_dm      : out std_ulogic_vector(1 downto 0);
-        ddram_dq      : inout std_ulogic_vector(15 downto 0);
-        ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
-        ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
+        ddram_dm      : out std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
+        ddram_dq      : inout std_ulogic_vector(DRAM_DLINES-1 downto 0);
+        ddram_dqs_p   : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
+        ddram_dqs_n   : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
         ddram_clk_p   : out std_ulogic;
         ddram_clk_n   : out std_ulogic;
         ddram_cke     : out std_ulogic;
@@ -87,10 +89,10 @@ architecture behaviour of litedram_wrapper is
         ddram_cas_n                    : out std_ulogic;
         ddram_we_n                     : out std_ulogic;
         ddram_cs_n                     : out std_ulogic;
-        ddram_dm                       : out std_ulogic_vector(1 downto 0);
-        ddram_dq                       : inout std_ulogic_vector(15 downto 0);
-        ddram_dqs_p                    : inout std_ulogic_vector(1 downto 0);
-        ddram_dqs_n                    : inout std_ulogic_vector(1 downto 0);
+        ddram_dm                       : out std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
+        ddram_dq                       : inout std_ulogic_vector(DRAM_DLINES-1 downto 0);
+        ddram_dqs_p                    : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
+        ddram_dqs_n                    : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
         ddram_clk_p                    : out std_ulogic;
         ddram_clk_n                    : out std_ulogic;
         ddram_cke                      : out std_ulogic;
@@ -117,11 +119,11 @@ architecture behaviour of litedram_wrapper is
         user_port_native_0_cmd_addr    : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
         user_port_native_0_wdata_valid : in std_ulogic;
         user_port_native_0_wdata_ready : out std_ulogic;
-        user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
-        user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
+        user_port_native_0_wdata_we    : in std_ulogic_vector(DRAM_PORT_WIDTH/8-1 downto 0);
+        user_port_native_0_wdata_data  : in std_ulogic_vector(DRAM_PORT_WIDTH-1 downto 0);
         user_port_native_0_rdata_valid : out std_ulogic;
         user_port_native_0_rdata_ready : in std_ulogic;
-        user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
+        user_port_native_0_rdata_data  : out std_ulogic_vector(DRAM_PORT_WIDTH-1 downto 0)
         );
     end component;
     
@@ -131,11 +133,11 @@ architecture behaviour of litedram_wrapper is
     signal user_port0_cmd_addr          : std_ulogic_vector(DRAM_ABITS-1 downto 0);
     signal user_port0_wdata_valid       : std_ulogic;
     signal user_port0_wdata_ready       : std_ulogic;
-    signal user_port0_wdata_we          : std_ulogic_vector(15 downto 0);
-    signal user_port0_wdata_data        : std_ulogic_vector(127 downto 0);
+    signal user_port0_wdata_we          : std_ulogic_vector(DRAM_PORT_WIDTH/8-1 downto 0);
+    signal user_port0_wdata_data        : std_ulogic_vector(DRAM_PORT_WIDTH-1 downto 0);
     signal user_port0_rdata_valid       : std_ulogic;
     signal user_port0_rdata_ready       : std_ulogic;
-    signal user_port0_rdata_data        : std_ulogic_vector(127 downto 0);
+    signal user_port0_rdata_data        : std_ulogic_vector(DRAM_PORT_WIDTH-1 downto 0);
 
     signal wb_ctrl_adr                  : std_ulogic_vector(29 downto 0);
     signal wb_ctrl_dat_w                : std_ulogic_vector(31 downto 0);
@@ -150,14 +152,24 @@ architecture behaviour of litedram_wrapper is
     signal wb_init_out                  : wb_io_slave_out;
 
     -- DRAM data port width
-    constant DRAM_DBITS                 : natural := 128;
+    constant DRAM_DBITS                 : natural := DRAM_PORT_WIDTH;
+    -- DRAM data port sel bits
     constant DRAM_SBITS                 : natural := (DRAM_DBITS / 8);
 
+    -- WB geometry (just a few shortcuts)
+    constant WBL                        : positive := wb_in.dat'length;
+    constant WBSL                       : positive := wb_in.sel'length;
+
+    -- Select a WB word inside DRAM port width
+    constant WB_WORD_COUNT              : positive := DRAM_DBITS/WBL;
+    constant WB_WSEL_BITS               : positive := log2(WB_WORD_COUNT);
+    constant WB_WSEL_RIGHT              : positive := log2(WBL/8);
+
     -- BRAM organisation: We never access more than wishbone_data_bits at
     -- a time so to save resources we make the array only that wide, and
     -- use consecutive indices for to make a cache "line"
     --
-    -- ROW_SIZE is the width in bytes of the BRAM (based on litedram, so 128-bits)
+    -- ROW_SIZE is the width in bytes of the BRAM, ie, litedram port width
     constant ROW_SIZE      : natural := DRAM_DBITS / 8;
     -- ROW_PER_LINE is the number of row (litedram transactions) in a line
     constant ROW_PER_LINE  : natural := LINE_SIZE / ROW_SIZE;
@@ -184,11 +196,12 @@ architecture behaviour of litedram_wrapper is
     -- TAG_BITS is the number of bits of the tag part of the address
     constant TAG_BITS      : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
     -- WAY_BITS is the number of bits to select a way
-    constant WAY_BITS     : natural := log2(NUM_WAYS);
+    constant WAY_BITS      : natural := log2(NUM_WAYS);
 
     subtype row_t is integer range 0 to BRAM_ROWS-1;
     subtype index_t is integer range 0 to NUM_LINES-1;
     subtype way_t is integer range 0 to NUM_WAYS-1;
+    subtype row_in_line_t is unsigned(ROW_LINEBITS-1 downto 0);
 
     -- The cache data BRAM organized as described above for each way
     subtype cache_row_t is std_ulogic_vector(DRAM_DBITS-1 downto 0);
@@ -207,6 +220,9 @@ architecture behaviour of litedram_wrapper is
     subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
     type cache_valids_t is array(index_t) of cache_way_valids_t;
 
+    -- "Temporary" valid bits for the rows of the currently refilled line
+    type row_per_line_valid_t is array(0 to ROW_PER_LINE - 1) of std_ulogic;
+
     -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
     signal cache_tags   : cache_tags_array_t;
     signal cache_valids : cache_valids_t;
@@ -217,10 +233,10 @@ architecture behaviour of litedram_wrapper is
     --
     -- Store queue signals
     --
-    -- We store a single wishbone dword per entry (64-bit) but all
-    -- 16 sel bits for the DRAM.
-    -- XXX Investigate storing only AD3 and 8 sel bits if it's better
-    constant STOREQ_BITS  : positive := wishbone_data_bits + DRAM_SBITS;
+    -- We store a single wishbone dword per entry (64-bit)
+    -- along with the wishbone sel bits and the necessary address
+    -- bits to select which part of DRAM port to write to.
+    constant STOREQ_BITS  : positive := WBL + WBSL + WB_WSEL_BITS;
 
     signal storeq_rd_ready : std_ulogic;
     signal storeq_rd_valid : std_ulogic;
@@ -233,7 +249,7 @@ architecture behaviour of litedram_wrapper is
     -- Cache management signals
     --
 
-     -- Cache state machine
+    -- Cache state machine
     type state_t is (IDLE,             -- Normal load hit processing
                      REFILL_CLR_TAG,   -- Cache refill clear tag
                      REFILL_WAIT_ACK); -- Cache refill wait ack
@@ -247,8 +263,8 @@ architecture behaviour of litedram_wrapper is
     -- Read pipeline (to handle cache RAM latency)
     signal read_ack_0  : std_ulogic := '0';
     signal read_ack_1  : std_ulogic := '0';
-    signal read_ad3_0  : std_ulogic;
-    signal read_ad3_1  : std_ulogic;
+    signal read_wsl_0  : std_ulogic_vector(WB_WSEL_BITS-1 downto 0) := (others => '0');
+    signal read_wsl_1  : std_ulogic_vector(WB_WSEL_BITS-1 downto 0) := (others => '0');
     signal read_way_0  : way_t;
     signal read_way_1  : way_t;
 
@@ -261,7 +277,8 @@ architecture behaviour of litedram_wrapper is
                       OP_LOAD_HIT,
                       OP_LOAD_MISS,
                       OP_STORE_HIT,
-                      OP_STORE_MISS);
+                      OP_STORE_MISS,
+                      OP_STORE_DELAYED);
 
     signal req_index    : index_t;
     signal req_row      : row_t;
@@ -269,10 +286,9 @@ architecture behaviour of litedram_wrapper is
     signal req_tag      : cache_tag_t;
     signal req_op       : req_op_t;
     signal req_laddr    : std_ulogic_vector(REAL_ADDR_BITS-1 downto 0);
-    signal req_ad3      : std_ulogic;
+    signal req_wsl      : std_ulogic_vector(WB_WSEL_BITS-1 downto 0);
     signal req_we       : std_ulogic_vector(DRAM_SBITS-1 downto 0);
     signal req_wdata    : std_ulogic_vector(DRAM_DBITS-1 downto 0);
-    signal accept_store : std_ulogic;
     signal stall        : std_ulogic;
 
     -- Line refill command signals and latches
@@ -281,6 +297,8 @@ architecture behaviour of litedram_wrapper is
     signal refill_way       : way_t;
     signal refill_index     : index_t;
     signal refill_row       : row_t;
+    signal refill_end_row   : row_in_line_t;
+    signal refill_rows_vlid : row_per_line_valid_t;
 
     -- Cache RAM interface
     type cache_ram_out_t is array(way_t) of cache_row_t;
@@ -306,21 +324,25 @@ architecture behaviour of litedram_wrapper is
         return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)));
     end;
 
+    -- Return the index of a row within a line
+    function get_row_of_line(row: row_t) return row_in_line_t is
+	variable row_v : unsigned(ROW_BITS-1 downto 0);
+    begin
+	row_v := to_unsigned(row, ROW_BITS);
+        return row_v(ROW_LINEBITS-1 downto 0);
+    end;
     -- Returns whether this is the last row of a line. It takes a DRAM address
-    function is_last_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS))
+    function is_last_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS);
+                              last: row_in_line_t)
         return boolean is
-        constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
     begin
-        return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones;
+        return unsigned(addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)) = last;
     end;
 
     -- Returns whether this is the last row of a line
-    function is_last_row(row: row_t) return boolean is
-        variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
-        constant ones  : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
+    function is_last_row(row: row_t; last: row_in_line_t) return boolean is
     begin
-        row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
-        return row_v(ROW_LINEBITS-1 downto 0) = ones;
+        return get_row_of_line(row) = last;
     end;
 
     -- Return the address of the next row in the current cache line. It takes a
@@ -387,8 +409,6 @@ begin
         report "geometry bits don't add up" severity FAILURE;
     assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
         report "geometry bits don't add up" severity FAILURE;
-    assert (128 = DRAM_DBITS)
-        report "Can't yet handle a DRAM width that isn't 128-bits" severity FAILURE;
 
     -- alternate core reset address set when DRAM is not initialized.
     core_alt_reset <= not init_done;
@@ -493,7 +513,7 @@ begin
             --
             -- Write mux: cache refills from DRAM or writes from Wishbone
             --
-            if state = IDLE then
+            if req_op = OP_STORE_HIT and req_hit_way = i then
                 -- Write from wishbone
                 wr_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
                 wr_data <= req_wdata;
@@ -570,7 +590,7 @@ begin
     end generate;
 
     --
-    -- Wishbone interface:
+    -- Wishbone request interface:
     --
     --  - Incoming wishbone request latch (to help with timing)
     --  - Read response pipeline (to match BRAM output buffer delay)
@@ -632,16 +652,15 @@ begin
     --
     -- Read response pipeline
     --
-    -- XXX Might have to put store acks in there too (see comment in wb_response)
     read_pipe: process(system_clk)
     begin
         if rising_edge(system_clk) then
             read_ack_0 <= '1' when req_op = OP_LOAD_HIT else '0';
-            read_ad3_0 <= req_ad3;
+            read_wsl_0 <= req_wsl;
             read_way_0 <= req_hit_way;
 
             read_ack_1 <= read_ack_0;
-            read_ad3_1 <= read_ad3_0;
+            read_wsl_1 <= read_wsl_0;
             read_way_1 <= read_way_0;
 
             if TRACE then
@@ -670,58 +689,54 @@ begin
         end if;
     end process;
 
-    wb_reponse: process(all)
-        variable rdata      : std_ulogic_vector(DRAM_DBITS-1 downto 0);
-        variable store_done : std_ulogic;
+    --
+    -- Wishbone response generation
+    --
+
+    wb_rseponse: process(all)
+        variable rdata        : std_ulogic_vector(DRAM_DBITS-1 downto 0);
+        variable store_done   : std_ulogic;
+        variable accept_store : std_ulogic;
+        variable wsel         : natural range 0 to WB_WORD_COUNT-1;
     begin
-        -- Can we accept a store ? This is set when IDLE and the store
-        -- queue & command queue are not full.
+        -- Can we accept a store ? This is set when the store queue & command
+        -- queue are not full.
         --
-        -- Note: This is only used to control the WB request latch, stall
-        -- and store "early complete". We don't want to use this to control
-        -- cmd_valid to DRAM as this would create a circular dependency inside
-        -- LiteDRAM as cmd_ready I think is driven from cmd_valid.
+        -- This does *not* mean that we will accept the store, there are other
+        -- reasons to delay them (see OP_STORE_DELAYED).
         --
-        -- The state machine that controls the command queue must thus
-        -- reproduce this logic at least partially.
+        -- A store is fully accepted when *both* req_op is not OP_STORE_DELAYED
+        -- and accept_store is '1'.
         --
-        -- Note also that user_port0_cmd_ready from LiteDRAM is combinational
-        -- from user_port0_cmd_valid. IE. we won't know that LiteDRAM cannot
-        -- accept a command until we try to send one.
+        -- The reason for this split is to avoid a circular dependency inside
+        -- LiteDRAM, since cmd_ready from litedram is driven from cmd_valid (*)
+        -- we don't want to generate cmd_valid from cmd_ready. So we generate
+        -- it instead from all the *other* conditions that make a store valid.
         --
-        if state = IDLE then
-            accept_store <= user_port0_cmd_ready and storeq_wr_ready;
-
-            -- Corner case !!! The read acks pipeline takes two extra cycles
-            -- which means a store ack can collide with a previous load hit
-            -- ack. Thus we stall stores if we have a load ack pending.
-            if read_ack_0 = '1' or read_ack_1 = '1' then
-                accept_store <= '0';
-            end if;
+        -- (*) It's my understanding that user_port0_cmd_ready from LiteDRAM is
+        -- ombinational from user_port0_cmd_valid along with a bunch of other
+        -- internal signals. IE. we won't know that LiteDRAM cannot accept a
+        -- command until we try to send one.
+        --
+        accept_store := user_port0_cmd_ready and storeq_wr_ready;
+
+        -- Generate stalls. For stores we stall if we can't accept it.
+        -- For loads, we stall if we are going to take a load miss or
+        -- are in the middle of a refill and it isn't a partial hit.
+        if req_op = OP_STORE_MISS or req_op = OP_STORE_HIT then
+            stall <= not accept_store;
+        elsif req_op = OP_LOAD_MISS or req_op = OP_STORE_DELAYED then
+            stall <= '1';
         else
-            accept_store <= '0';
+            stall <= '0';
         end if;
-
-        -- Generate stalls. For loads, we stall if we are going to take a load
-        -- miss or are in the middle of a refill. For stores, if we can't
-        -- accept it.
-        case state is
-        when IDLE =>
-            case req_op is
-            when OP_LOAD_MISS =>
-                stall <= '1';
-            when OP_STORE_MISS | OP_STORE_HIT =>
-                stall <= not accept_store;
-            when others =>
-                stall <= '0';
-            end case;
-        when others =>
-            stall <= '1';
-        end case;
         
         -- Data out mux
         rdata := cache_out(read_way_1);
-        wb_out.dat <= rdata(127 downto 64) when read_ad3_1 = '1' else rdata(63 downto 0);
+
+        -- Hard wired for 64-bit wishbone
+        wsel := to_integer(unsigned(read_wsl_1));
+        wb_out.dat <= rdata((wsel+1)*WBL-1 downto wsel*WBL);
 
         -- Early-complete stores on wishbone.
         if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then
@@ -736,7 +751,8 @@ begin
         -- Generate Wishbone ACKs on read hits and store complete
         --
         -- This can happen on store right behind loads ! This is why
-        -- we don't accept a new store right behind a load ack above.
+        -- we delay a store when a load ack is in the pipeline in the
+        -- request decoder below.
         --
         wb_out.ack <= read_ack_1 or store_ack_1;
         assert read_ack_1 = '0' or store_ack_1 = '0' report
@@ -748,60 +764,99 @@ begin
     -- Cache request decode
     --
     request_decode: process(all)
-        variable valid   : std_ulogic;
-        variable is_hit  : std_ulogic;
-        variable hit_way : way_t;
+        variable valid       : boolean;
+        variable is_hit      : boolean;
+        variable store_delay : boolean;
+        variable hit_way     : way_t;
     begin
         -- Extract line, row and tag from request
         req_index <= get_index(wb_req.adr);
         req_row <= get_row(wb_req.adr(REAL_ADDR_BITS-1 downto 0));
         req_tag <= get_tag(wb_req.adr);
 
-        -- Calculate address of beginning of cache line, will be
+        -- Calculate address of beginning of cache row, will be
         -- used for cache miss processing if needed
-        req_laddr <= wb_req.adr(REAL_ADDR_BITS - 1 downto LINE_OFF_BITS) &
-                     (LINE_OFF_BITS-1 downto 0 => '0');
+        req_laddr <= wb_req.adr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS) &
+                     (ROW_OFF_BITS-1 downto 0 => '0');
 
 
         -- Do we have a valid request in the WB latch ?
-        if state = IDLE then
-            valid := wb_req.cyc and wb_req.stb;
-        else
-            valid := '0';
-        end if;
+        valid := wb_req.cyc = '1' and wb_req.stb = '1';
 
-        -- Store signals
-        req_ad3      <= wb_req.adr(3);
-        req_wdata    <= wb_req.dat & wb_req.dat;
-        req_we       <= wb_req.sel & "00000000" when req_ad3 = '1' else
-                        "00000000" & wb_req.sel;
+        -- Store signals (hard wired for 64-bit wishbone at the moment)
+        req_wsl <= wb_req.adr(WB_WSEL_RIGHT+WB_WSEL_BITS-1 downto WB_WSEL_RIGHT);
+        for i in 0 to WB_WORD_COUNT-1 loop
+            if to_integer(unsigned(req_wsl)) = i then
+                req_we(WBSL*(i+1)-1 downto WBSL*i) <= wb_req.sel;
+            else
+                req_we(WBSL*(i+1)-1 downto WBSL*i) <= x"00";
+            end if;
+            req_wdata(WBL*(i+1)-1 downto WBL*i) <= wb_req.dat;
+        end loop;
 
         -- Test if pending request is a hit on any way
         hit_way := 0;
-        is_hit := '0';
+        is_hit := false;
         for i in way_t loop
-            if valid = '1' and cache_valids(req_index)(i) = '1' then
+            if valid and
+                (cache_valids(req_index)(i) = '1' or
+                 (state = REFILL_WAIT_ACK and
+                  req_index = refill_index and i = refill_way and
+                  refill_rows_vlid(req_row mod ROW_PER_LINE) = '1')) then
                 if read_tag(i, cache_tags(req_index)) = req_tag then
                     hit_way := i;
-                    is_hit := '1';
+                    is_hit := true;
                 end if;
             end if;
         end loop;
 
+        -- We need to delay stores under some circumstances to avoid
+        -- collisions with the refill machine.
+        --
+        -- Corner case !!! The read acks pipeline takes two extra cycles
+        -- which means a store ack can collide with a previous load hit
+        -- ack. Thus we stall stores if we have a load ack pending.
+        --
+        if read_ack_0 = '1' or read_ack_1 = '1' then
+            -- Clash with pending read acks, delay..
+            store_delay := true;
+        elsif state /= IDLE then
+            -- If the reload machine is active, we cannot accept a store
+            -- for now.
+            --
+            -- We could improve this a bit by allowing stores if we have sent
+            -- all the requests down to litedram (we are only waiting for the
+            -- responses) *and* either of those conditions is true:
+            --
+            -- * It's a miss (doesn't require a write to BRAM) and isn't
+            --   for the line being reloaded (otherwise we might reload
+            --   stale data into the cache).
+            -- * It's a hit on a different way than the one being reloaded
+            --   in which case there is no conflict for BRAM access.
+            --
+            -- Otherwise we delay it...
+            --
+            store_delay := true;
+        else
+            store_delay := false;
+        end if;
+
         -- Generate the req op. We only allow OP_LOAD_* when in the
         -- IDLE state as our PLRU and ACK generation rely on this,
         -- stores are allowed in IDLE state.
         --
         req_op <= OP_NONE;
-        if valid = '1' then
+        if valid then
             if wb_req.we = '1' then
-                if is_hit = '1' then
+                if store_delay then
+                    req_op <= OP_STORE_DELAYED;
+                elsif is_hit then
                     req_op <= OP_STORE_HIT;
                 else
                     req_op <= OP_STORE_MISS;
                 end if;
             else
-                if is_hit = '1' then
+                if is_hit then
                     req_op <= OP_LOAD_HIT;
                 else
                     req_op <= OP_LOAD_MISS;
@@ -833,21 +888,38 @@ begin
 
     storeq_control : process(all)
         variable stq_data : wishbone_data_type;
-        variable stq_sel  : std_ulogic_vector(DRAM_SBITS-1 downto 0);
+        variable stq_sel  : wishbone_sel_type;
+        variable stq_wsl  : std_ulogic_vector(WB_WSEL_BITS-1 downto 0);
     begin
-        storeq_wr_data <= wb_req.dat & req_we;
+        storeq_wr_data <= wb_req.dat & wb_req.sel &
+                          wb_req.adr(WB_WSEL_RIGHT+WB_WSEL_BITS-1 downto WB_WSEL_RIGHT);
 
-        -- Only accept store if we can send a command
+        -- Only queue stores if we can also send a command
         if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then
             storeq_wr_valid <= user_port0_cmd_ready;
         else
             storeq_wr_valid <= '0';
         end if;
 
-        stq_data := storeq_rd_data(storeq_rd_data'left downto DRAM_SBITS);
-        stq_sel  := storeq_rd_data(DRAM_SBITS-1 downto 0);
-        user_port0_wdata_data  <= stq_data & stq_data;
-        user_port0_wdata_we    <= stq_sel;
+        -- Store signals (hard wired for 64-bit wishbone at the moment)
+        stq_data := storeq_rd_data(storeq_rd_data'left downto WBSL+WB_WSEL_BITS);
+        stq_sel  := storeq_rd_data(WBSL+WB_WSEL_BITS-1 downto WB_WSEL_BITS);
+        stq_wsl  := storeq_rd_data(WB_WSEL_BITS-1      downto 0);
+        for i in 0 to WB_WORD_COUNT-1 loop
+            if to_integer(unsigned(stq_wsl)) = i then
+                user_port0_wdata_we(WBSL*(i+1)-1 downto WBSL*i) <= stq_sel;
+            else
+                user_port0_wdata_we(WBSL*(i+1)-1 downto WBSL*i) <= x"00";
+            end if;
+            user_port0_wdata_data(WBL*(i+1)-1 downto WBL*i) <= stq_data;
+        end loop;
+
+        -- Note: Current litedram ignores user_port0_wdata_valid. We
+        -- must make sure to always have the data available at the
+        -- output of the store queue when we send the write command.
+        --
+        -- Thankfully this is always the case with this design.
+        --
         user_port0_wdata_valid <= storeq_rd_valid;
         storeq_rd_ready        <= user_port0_wdata_ready;
 
@@ -858,13 +930,13 @@ begin
                         to_hstring(wb_req.adr(DRAM_ABITS+3 downto 0)) &
                         " data:" & to_hstring(req_wdata) &
                         " we:" & to_hstring(req_we) &
-                        " V:" & std_ulogic'image(accept_store);
+                        " V:" & std_ulogic'image(user_port0_cmd_ready);
                 else
                     report "Store miss to:" &
                         to_hstring(wb_req.adr(DRAM_ABITS+3 downto 0)) &
                         " data:" & to_hstring(req_wdata) &
                         " we:" & to_hstring(req_we) &
-                        " V:" & std_ulogic'image(accept_store);
+                        " V:" & std_ulogic'image(user_port0_cmd_ready);
                 end if;
                 if storeq_wr_valid = '1' and storeq_wr_ready = '1' then
                     report "storeq push " & to_hstring(storeq_wr_data);
@@ -879,10 +951,10 @@ begin
     -- LiteDRAM command mux
     dram_commands: process(all)
     begin
-        if state = IDLE and (req_op = OP_STORE_HIT or req_op = OP_STORE_MISS) then
+        if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then
             -- For stores, forward signals directly. Only send command if
-            -- the FIFO can accept a store
-            user_port0_cmd_addr  <= wb_req.adr(DRAM_ABITS+3 downto 4);
+            -- the FIFO can accept a store.
+            user_port0_cmd_addr  <= wb_req.adr(DRAM_ABITS+ROW_OFF_BITS-1 downto ROW_OFF_BITS);
             user_port0_cmd_we    <= '1';
             user_port0_cmd_valid <= storeq_wr_ready;
         else
@@ -891,6 +963,9 @@ begin
             user_port0_cmd_valid <= refill_cmd_valid;
             user_port0_cmd_we    <= '0';
         end if;
+
+        -- Note: litedram  ignores this signal and assumes we are
+        -- always ready to accept read data.
         user_port0_rdata_ready <= '1'; -- Always 1
     end process;
 
@@ -918,6 +993,11 @@ begin
                     assert refill_cmd_valid = '0' report "refill cmd valid in IDLE state !"
                         severity failure;
 
+                    -- Reset per-row valid flags, only used in WAIT_ACK
+                    for i in 0 to ROW_PER_LINE - 1 loop
+                        refill_rows_vlid(i) <= '0';
+                    end loop;
+
                     -- If NO_LS_OVERLAP is set, disallow a load miss if the store
                     -- queue still has data in it.
                     wait_qdrain := false;
@@ -931,8 +1011,9 @@ begin
                         refill_way <= to_integer(unsigned(plru_victim(req_index)));
 
                         -- Keep track of our index and way for subsequent stores
-                        refill_index <= req_index;
-                        refill_row   <= get_row(req_laddr);
+                        refill_index   <= req_index;
+                        refill_row     <= get_row(req_laddr);
+                        refill_end_row <= get_row_of_line(get_row(req_laddr)) - 1;
 
                         -- Prep for first DRAM read
                         --
@@ -941,7 +1022,7 @@ begin
                         -- "dram_commands". In fact, we could make refill_cmd_addr
                         -- only contain the "counter" bits and wire it with the
                         -- other bits from req_laddr.
-                        refill_cmd_addr    <= req_laddr(DRAM_ABITS+3 downto 4);
+                        refill_cmd_addr    <= req_laddr(DRAM_ABITS+ROW_OFF_BITS-1 downto ROW_OFF_BITS);
                         refill_cmd_valid   <= '1';
 
                         if TRACE then
@@ -982,7 +1063,7 @@ begin
                         if TRACE then
                             report "got refill cmd ack !";
                         end if;
-                        if is_last_row_addr(refill_cmd_addr) then
+                        if is_last_row_addr(refill_cmd_addr, refill_end_row) then
                             refill_cmd_valid <= '0';
                             cmds_done := true;
                             if TRACE then
@@ -1003,8 +1084,12 @@ begin
                         if TRACE then
                             report "got refill data ack !";
                         end if;
+
+                        -- Mark partial line valid
+                        refill_rows_vlid(refill_row mod ROW_PER_LINE) <= '1';
+
                         -- Check for completion
-                        if cmds_done and is_last_row(refill_row) then
+                        if cmds_done and is_last_row(refill_row, refill_end_row) then
                             if TRACE then
                                 report "all refill data done !";
                             end if;

litedram/extras/wave_tb.gtkw

@@ -1,17 +1,18 @@
 [*]
 [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
-[*] Sun May 31 12:53:52 2020
+[*] Mon Jun 22 06:32:16 2020
 [*]
 [dumpfile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/foo.ghw"
-[dumpfile_mtime] "Sun May 31 12:50:15 2020"
-[dumpfile_size] 1134118
+[dumpfile_mtime] "Mon Jun 22 06:28:35 2020"
+[dumpfile_size] 1680014
 [savefile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/litedram/extras/wave_tb.gtkw"
-[timestart] 1312950000
+[timestart] 1920580000
 [size] 2509 1371
 [pos] -1 -1
-*-24.248457 1386890000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-24.248457 1935000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] top.
 [treeopen] top.dram_tb.
+[treeopen] top.dram_tb.dram.
 [sst_width] 301
 [signals_width] 433
 [sst_expanded] 1
@@ -26,7 +27,6 @@ top.dram_tb.clk
 @22
 #{top.dram_tb.wb_in.dat[63:0]} top.dram_tb.wb_in.dat[63] top.dram_tb.wb_in.dat[62] top.dram_tb.wb_in.dat[61] top.dram_tb.wb_in.dat[60] top.dram_tb.wb_in.dat[59] top.dram_tb.wb_in.dat[58] top.dram_tb.wb_in.dat[57] top.dram_tb.wb_in.dat[56] top.dram_tb.wb_in.dat[55] top.dram_tb.wb_in.dat[54] top.dram_tb.wb_in.dat[53] top.dram_tb.wb_in.dat[52] top.dram_tb.wb_in.dat[51] top.dram_tb.wb_in.dat[50] top.dram_tb.wb_in.dat[49] top.dram_tb.wb_in.dat[48] top.dram_tb.wb_in.dat[47] top.dram_tb.wb_in.dat[46] top.dram_tb.wb_in.dat[45] top.dram_tb.wb_in.dat[44] top.dram_tb.wb_in.dat[43] top.dram_tb.wb_in.dat[42] top.dram_tb.wb_in.dat[41] top.dram_tb.wb_in.dat[40] top.dram_tb.wb_in.dat[39] top.dram_tb.wb_in.dat[38] top.dram_tb.wb_in.dat[37] top.dram_tb.wb_in.dat[36] top.dram_tb.wb_in.dat[35] top.dram_tb.wb_in.dat[34] top.dram_tb.wb_in.dat[33] top.dram_tb.wb_in.dat[32] top.dram_tb.wb_in.dat[31] top.dram_tb.wb_in.dat[30] top.dram_tb.wb_in.dat[29] top.dram_tb.wb_in.dat[28] top.dram_tb.wb_in.dat[27] top.dram_tb.wb_in.dat[26] top.dram_tb.wb_in.dat[25] top.dram_tb.wb_in.dat[24] top.dram_tb.wb_in.dat[23] top.dram_tb.wb_in.dat[22] top.dram_tb.wb_in.dat[21] top.dram_tb.wb_in.dat[20] top.dram_tb.wb_in.dat[19] top.dram_tb.wb_in.dat[18] top.dram_tb.wb_in.dat[17] top.dram_tb.wb_in.dat[16] top.dram_tb.wb_in.dat[15] top.dram_tb.wb_in.dat[14] top.dram_tb.wb_in.dat[13] top.dram_tb.wb_in.dat[12] top.dram_tb.wb_in.dat[11] top.dram_tb.wb_in.dat[10] top.dram_tb.wb_in.dat[9] top.dram_tb.wb_in.dat[8] top.dram_tb.wb_in.dat[7] top.dram_tb.wb_in.dat[6] top.dram_tb.wb_in.dat[5] top.dram_tb.wb_in.dat[4] top.dram_tb.wb_in.dat[3] top.dram_tb.wb_in.dat[2] top.dram_tb.wb_in.dat[1] top.dram_tb.wb_in.dat[0]
 #{top.dram_tb.wb_in.adr[31:0]} top.dram_tb.wb_in.adr[31] top.dram_tb.wb_in.adr[30] top.dram_tb.wb_in.adr[29] top.dram_tb.wb_in.adr[28] top.dram_tb.wb_in.adr[27] top.dram_tb.wb_in.adr[26] top.dram_tb.wb_in.adr[25] top.dram_tb.wb_in.adr[24] top.dram_tb.wb_in.adr[23] top.dram_tb.wb_in.adr[22] top.dram_tb.wb_in.adr[21] top.dram_tb.wb_in.adr[20] top.dram_tb.wb_in.adr[19] top.dram_tb.wb_in.adr[18] top.dram_tb.wb_in.adr[17] top.dram_tb.wb_in.adr[16] top.dram_tb.wb_in.adr[15] top.dram_tb.wb_in.adr[14] top.dram_tb.wb_in.adr[13] top.dram_tb.wb_in.adr[12] top.dram_tb.wb_in.adr[11] top.dram_tb.wb_in.adr[10] top.dram_tb.wb_in.adr[9] top.dram_tb.wb_in.adr[8] top.dram_tb.wb_in.adr[7] top.dram_tb.wb_in.adr[6] top.dram_tb.wb_in.adr[5] top.dram_tb.wb_in.adr[4] top.dram_tb.wb_in.adr[3] top.dram_tb.wb_in.adr[2] top.dram_tb.wb_in.adr[1] top.dram_tb.wb_in.adr[0]
-@23
 #{top.dram_tb.wb_in.sel[7:0]} top.dram_tb.wb_in.sel[7] top.dram_tb.wb_in.sel[6] top.dram_tb.wb_in.sel[5] top.dram_tb.wb_in.sel[4] top.dram_tb.wb_in.sel[3] top.dram_tb.wb_in.sel[2] top.dram_tb.wb_in.sel[1] top.dram_tb.wb_in.sel[0]
 @28
 top.dram_tb.wb_in.cyc
@@ -67,6 +67,9 @@ top.dram_tb.dram.user_port0_cmd_valid
 top.dram_tb.dram.refill_cmd_valid
 @420
 top.dram_tb.dram.req_index
+@421
+top.dram_tb.dram.req_row
+@420
 top.dram_tb.dram.req_hit_way
 @28
 top.dram_tb.dram.req_ad3

litedram/gen-src/dram-init-mem.vhdl

@@ -21,7 +21,7 @@ end entity dram_init_mem;
 
 architecture rtl of dram_init_mem is
 
-    constant INIT_RAM_SIZE    : integer := 16384;
+    constant INIT_RAM_SIZE    : integer := 24576;
     constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
     constant TOTAL_RAM_SIZE   : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
     constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE-1);

litedram/gen-src/generate.py

@@ -38,16 +38,14 @@ def build_init_code(build_dir, is_sim):
     sw_inc_dir = os.path.join(sw_dir, "include")
     gen_inc_dir = os.path.join(sw_inc_dir, "generated")
     src_dir = os.path.join(gen_src_dir, "sdram_init")
-    lxbios_src_dir = os.path.join(soc_directory, "software", "liblitedram")
-    lxbios_inc_dir = os.path.join(soc_directory, "software", "include")
+    lxbios_src_dir = os.path.join(soc_directory, "software")
     print("     sw dir:", sw_dir)
     print("gen_inc_dir:", gen_inc_dir)
     print("    src dir:", src_dir)
     print(" lx src dir:", lxbios_src_dir)
-    print(" lx inc dir:", lxbios_inc_dir)
 
-    # Generate mem.h
-    mem_h = "#define MAIN_RAM_BASE 0x40000000"
+    # Generate mem.h (hard wire size, it's not important)
+    mem_h = "#define MAIN_RAM_BASE 0x40000000\n#define MAIN_RAM_SIZE 0x10000000"
     write_to_file(os.path.join(gen_inc_dir, "mem.h"), mem_h)
 
     # Environment
@@ -61,7 +59,6 @@ def build_init_code(build_dir, is_sim):
     add_var("SRC_DIR", src_dir)
     add_var("GENINC_DIR", sw_inc_dir)
     add_var("LXSRC_DIR", lxbios_src_dir)
-    add_var("LXINC_DIR", lxbios_inc_dir)
     if is_sim:
         add_var("EXTRA_CFLAGS", "-D__SIM__")
     write_to_file(os.path.join(gen_inc_dir, "variables.mak"), "".join(env_vars))
@@ -143,7 +140,7 @@ def generate_one(t):
 
 def main():
 
-    targets = ['arty','nexys-video', 'sim']
+    targets = ['arty','nexys-video', 'genesys2', 'sim']
     for t in targets:
         generate_one(t)
     

litedram/gen-src/genesys2.yml

@@ -0,0 +1,41 @@
+# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+{
+    # General ------------------------------------------------------------------
+    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
+    "cpu_variant":"standard",
+    "speedgrade": -2,          # FPGA speedgrade
+    "memtype":    "DDR3",      # DRAM type
+
+    # PHY ----------------------------------------------------------------------
+    "cmd_latency":     0,             # Command additional latency
+    "sdram_module":    "MT41J256M16", # SDRAM modules of the board or SO-DIMM
+    "sdram_module_nb": 4,             # Number of byte groups
+    "sdram_rank_nb":   1,             # Number of ranks
+    "sdram_phy":       K7DDRPHY,      # Type of FPGA PHY
+
+    # Electrical ---------------------------------------------------------------
+    "rtt_nom": "60ohm", # Nominal termination
+    "rtt_wr":  "60ohm", # Write termination
+    "ron":     "34ohm", # Output driver impedance
+
+    # Frequency ----------------------------------------------------------------
+    "input_clk_freq":   200e6, # Input clock frequency
+    "sys_clk_freq":     100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
+    "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
+
+    # Core ---------------------------------------------------------------------
+    "cmd_buffer_depth": 16,    # Depth of the command buffer
+
+    # User Ports ---------------------------------------------------------------
+    "user_ports": {
+        "native_0": {
+            "type": "native",
+        },
+    },
+
+    # CSR Port -----------------------------------------------------------------
+    "csr_alignment"  : 32,
+    "csr_data_width" : 32,
+}

litedram/gen-src/sdram_init/Makefile

@@ -3,8 +3,10 @@
 include variables.mak
 OBJ = $(BUILD_DIR)/obj
 
+LXINC_DIR=$(LXSRC_DIR)/include
+
 PROGRAM = sdram_init
-OBJECTS = $(OBJ)/head.o $(OBJ)/main.o $(OBJ)/sdram.o $(OBJ)/console.o
+OBJECTS = $(OBJ)/head.o $(OBJ)/main.o $(OBJ)/sdram.o $(OBJ)/memtest.o $(OBJ)/console.o
 
 #### Compiler
 
@@ -22,7 +24,13 @@ OBJCOPY = $(CROSS_COMPILE)objcopy
 #### Flags
 
 CPPFLAGS = -nostdinc -D__USE_LIBC $(EXTRA_CFLAGS)
-CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../../include
+
+# These includes must be first ...
+CPPFLAGS += -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../../include -I$(SRC_DIR)/libc/include 
+
+# .. and these last, otherwise litex overrides some of our stuff
+CPPFLAGS += -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(LXINC_DIR)/base -I$(LXSRC_DIR)/liblitedram
+
 CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include)
 CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks 
 ASFLAGS = $(CPPFLAGS) $(CFLAGS)
@@ -48,7 +56,9 @@ endif
 
 all: objdir $(OBJ)/$(PROGRAM).hex
 
-$(OBJ)/sdram.o: $(LXSRC_DIR)/sdram.c
+$(OBJ)/sdram.o: $(LXSRC_DIR)/liblitedram/sdram.c
+	$(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)
+$(OBJ)/memtest.o: $(LXSRC_DIR)/libbase/memtest.c
 	$(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)
 $(OBJ)/console.o: $(SRC_DIR)/../../../lib/console.c
 	$(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)

litedram/gen-src/sdram_init/head.S

@@ -14,7 +14,7 @@
  * limitations under the License.
  */
 
-#define STACK_TOP	0xff004000
+#define STACK_TOP	0xff006000
 
 #define FIXUP_ENDIAN						   \
 	tdi   0,0,0x48;	  /* Reverse endian of b . + 8		*/ \

litedram/gen-src/sdram_init/include/system.h

@@ -1,6 +1,8 @@
 #ifndef __SYSTEM_H
 #define __SYSTEM_H
 
+#include <stdint.h>
+
 #include "microwatt_soc.h"
 #include "io.h"
 
@@ -32,6 +34,9 @@ static inline uint64_t timer0_value_read(void)
 	return val;
 }
 
+static inline void init_progression_bar(int max) { }
+static inline void show_progress(int now) { }
+
 static inline void csr_write_simple(unsigned long v, unsigned long a)
 {
 	return writel(v, a);

litedram/gen-src/sdram_init/main.c

@@ -7,10 +7,10 @@
 
 #include <generated/git.h>
 
+#include "console.h"
 #include "microwatt_soc.h"
 #include "io.h"
 #include "sdram.h"
-#include "console.h"
 #include "elf64.h"
 
 #define FLASH_LOADER_USE_MAP
@@ -225,9 +225,9 @@ dump:
 
 static void boot_sdram(void)
 {
-	void *s = (void *)(DRAM_INIT_BASE + 0x4000);
+	void *s = (void *)(DRAM_INIT_BASE + 0x6000);
 	void *d = (void *)DRAM_BASE;
-	int  sz = (0x10000 - 0x4000);
+	int  sz = (0x10000 - 0x6000);
 	printf("Copying payload to DRAM...\n");
 	memcpy(d, s, sz);
 	printf("Booting from DRAM...\n");

litedram/generated/arty/litedram-initmem.vhdl

@@ -21,7 +21,7 @@ end entity dram_init_mem;
 
 architecture rtl of dram_init_mem is
 
-    constant INIT_RAM_SIZE    : integer := 16384;
+    constant INIT_RAM_SIZE    : integer := 24576;
     constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
     constant TOTAL_RAM_SIZE   : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
     constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE-1);

litedram/generated/arty/litedram_core.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (b1b2b29) & LiteX (20ff2462) on 2020-06-13 00:02:02
+// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:33:20
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,

litedram/generated/genesys2/litedram-initmem.vhdl

@@ -0,0 +1,123 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+use work.utils.all;
+
+entity dram_init_mem is
+    generic (
+        EXTRA_PAYLOAD_FILE : string   := "";
+        EXTRA_PAYLOAD_SIZE : integer  := 0
+        );
+    port (
+        clk     : in std_ulogic;
+        wb_in   : in wb_io_master_out;
+        wb_out  : out wb_io_slave_out
+      );
+end entity dram_init_mem;
+
+architecture rtl of dram_init_mem is
+
+    constant INIT_RAM_SIZE    : integer := 24576;
+    constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
+    constant TOTAL_RAM_SIZE   : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
+    constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE-1);
+    constant INIT_RAM_FILE    : string := "litedram_core.init";
+
+    type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
+
+    -- XXX FIXME: Have a single init function called twice with
+    -- an offset as argument
+    procedure init_load_payload(ram: inout ram_t; filename: string) is
+        file payload_file : text open read_mode is filename;
+        variable ram_line : line;
+        variable temp_word : std_logic_vector(63 downto 0);
+    begin
+        for i in 0 to RND_PAYLOAD_SIZE-1 loop
+            exit when endfile(payload_file);
+            readline(payload_file, ram_line);
+            hread(ram_line, temp_word);
+            ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0);
+            ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32);
+        end loop;
+        assert endfile(payload_file) report "Payload too big !" severity failure;
+    end procedure;
+
+    impure function init_load_ram(name : string) return ram_t is
+        file ram_file : text open read_mode is name;
+        variable temp_word : std_logic_vector(63 downto 0);
+        variable temp_ram : ram_t := (others => (others => '0'));
+        variable ram_line : line;
+    begin
+        report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) &
+            " rounded to:" & integer'image(RND_PAYLOAD_SIZE);
+        report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) &
+            " bytes using " & integer'image(INIT_RAM_ABITS) &
+            " address bits";
+        for i in 0 to (INIT_RAM_SIZE/8)-1 loop
+            exit when endfile(ram_file);
+            readline(ram_file, ram_line);
+            hread(ram_line, temp_word);
+            temp_ram(i*2) := temp_word(31 downto 0);
+            temp_ram(i*2+1) := temp_word(63 downto 32);
+        end loop;
+        if RND_PAYLOAD_SIZE /= 0 then
+            init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE);
+        end if;
+        return temp_ram;
+    end function;
+
+    impure function init_zero return ram_t is
+        variable temp_ram : ram_t := (others => (others => '0'));
+    begin
+        return temp_ram;
+    end function;
+
+    impure function initialize_ram(filename: string) return ram_t is
+    begin
+        report "Opening file " & filename;
+        if filename'length = 0 then
+            return init_zero;
+        else
+            return init_load_ram(filename);
+        end if;
+    end function;
+    signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE);
+
+    attribute ram_style : string;
+    attribute ram_style of init_ram: signal is "block";
+
+    signal obuf : std_ulogic_vector(31 downto 0);
+    signal oack : std_ulogic;
+begin
+
+    init_ram_0: process(clk)
+        variable adr  : integer;
+    begin
+        if rising_edge(clk) then
+            oack <= '0';
+            if (wb_in.cyc and wb_in.stb) = '1' then
+                adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
+                if wb_in.we = '0' then
+                   obuf <= init_ram(adr);
+                else
+                    for i in 0 to 3 loop
+                        if wb_in.sel(i) = '1' then
+                            init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
+                                wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
+                        end if;
+                    end loop;
+                end if;
+                oack <= '1';
+            end if;
+            wb_out.ack <= oack;
+            wb_out.dat <= obuf;
+        end if;
+    end process;
+
+    wb_out.stall <= '0';
+
+end architecture rtl;

litedram/generated/nexys-video/litedram-initmem.vhdl

@@ -21,7 +21,7 @@ end entity dram_init_mem;
 
 architecture rtl of dram_init_mem is
 
-    constant INIT_RAM_SIZE    : integer := 16384;
+    constant INIT_RAM_SIZE    : integer := 24576;
     constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
     constant TOTAL_RAM_SIZE   : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
     constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE-1);

litedram/generated/nexys-video/litedram_core.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (b1b2b29) & LiteX (20ff2462) on 2020-06-13 00:02:04
+// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:33:22
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,

litedram/generated/sim/litedram-initmem.vhdl

@@ -21,7 +21,7 @@ end entity dram_init_mem;
 
 architecture rtl of dram_init_mem is
 
-    constant INIT_RAM_SIZE    : integer := 16384;
+    constant INIT_RAM_SIZE    : integer := 24576;
     constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
     constant TOTAL_RAM_SIZE   : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
     constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE-1);

litedram/generated/sim/litedram_core.init

@@ -5,7 +5,7 @@ a64b5a7d14004a39
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@@ -604,7 +604,7 @@ f9410108f9210100
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