Set alt reset vector to the start of flash at 0xf0000000 and make it

programmable externally (using carvel LA)

fpga/top-caravel.vhdl

@@ -50,17 +50,16 @@ entity toplevel is
         jtag_trst : in std_ulogic;
         jtag_tdo  : out std_ulogic;
 
-	-- bills bus
+	-- Bill's bus
 	oib_clk        : out std_ulogic;
 	ob_data        : out std_ulogic_vector(7 downto 0);
 	ob_pty         : out std_ulogic;
 
 	ib_data        : in  std_ulogic_vector(7 downto 0);
-	ib_pty         : in  std_ulogic
-
-        -- XXX Add simple external bus
+	ib_pty         : in  std_ulogic;
 
 	-- Add an I/O pin to select fetching from flash on reset
+	alt_reset      : in std_ulogic
         );
 end entity toplevel;
 
@@ -96,6 +95,7 @@ architecture behaviour of toplevel is
     signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
     signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
     signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
+
 begin
 
     -- Main SoC
@@ -149,7 +149,10 @@ begin
 
             -- Use DRAM wishbone for Bill's bus
             wb_dram_in           => wb_dram_out,
-            wb_dram_out          => wb_dram_in
+            wb_dram_out          => wb_dram_in,
+
+	    -- Reset PC to flash offset 0 (ie 0xf000000)
+	    alt_reset            => alt_reset
             );
 
     ext_rst_n <= not ext_rst;

soc.vhdl

@@ -264,7 +264,7 @@ begin
 	    SIM => SIM,
             HAS_FPU => HAS_FPU,
 	    DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
-	    ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
+	    ALT_RESET_ADDRESS => (27 downto 0 => '0', others => '1'),
             LOG_LENGTH => LOG_LENGTH
 	    )
 	port map(