From dbb137437c902b27f16136dbda9b024182c2aa33 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 8 Jul 2020 09:37:45 +1000 Subject: [PATCH 1/2] acorn: Add support for the Acorn CLE 215+ This is a NiteFury based PCIe M2 form-factor board originally used for mining. It contains a speed grade 2 Artix 7 200T, 1GB of DDR3 and 32MB of flash. The serial port is routed to pin 2 (RX) and 3 (TX) of the P2 connector (pin 1 is GND). Note: Only 16MB of flash is currently usable until code is added to configure the flash controller to use 4-bytes address commands on that part. Signed-off-by: Benjamin Herrenschmidt --- fpga/acorn-cle-215.xdc | 338 + fpga/clk_gen_plle2.vhd | 12 + fpga/top-acorn-cle-215.vhdl | 319 + litedram/gen-src/acorn-cle-215.yml | 42 + litedram/gen-src/generate.py | 2 +- .../acorn-cle-215/litedram-initmem.vhdl | 123 + .../acorn-cle-215/litedram_core.init | 1858 ++ .../generated/acorn-cle-215/litedram_core.v | 17061 ++++++++++++++++ microwatt.core | 43 + 9 files changed, 19797 insertions(+), 1 deletion(-) create mode 100644 fpga/acorn-cle-215.xdc create mode 100644 fpga/top-acorn-cle-215.vhdl create mode 100644 litedram/gen-src/acorn-cle-215.yml create mode 100644 litedram/generated/acorn-cle-215/litedram-initmem.vhdl create mode 100644 litedram/generated/acorn-cle-215/litedram_core.init create mode 100644 litedram/generated/acorn-cle-215/litedram_core.v diff --git a/fpga/acorn-cle-215.xdc b/fpga/acorn-cle-215.xdc new file mode 100644 index 0000000..c2439b8 --- /dev/null +++ b/fpga/acorn-cle-215.xdc @@ -0,0 +1,338 @@ +################################################################################ +# clkin, reset, uart pins... +################################################################################ +# clk200:0.p +set_property LOC J19 [get_ports {clk200_p}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk200_p}] + +# clk200:0.n +set_property LOC H19 [get_ports {clk200_n}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk200_n}] + +################################################################################ +# P2 header used as UART +################################################################################ + +#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { p2_io1_n }]; +#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { p2_io1_p }]; +# AIO2_N +set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { uart_tx }]; +# AIO2_P +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { uart_rx }]; + +################################################################################ +# DRAM +################################################################################ + +# ddram:0.a +set_property LOC M15 [get_ports {ddram_a[0]}] +set_property SLEW FAST [get_ports {ddram_a[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}] + +# ddram:0.a +set_property LOC L21 [get_ports {ddram_a[1]}] +set_property SLEW FAST [get_ports {ddram_a[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}] + +# ddram:0.a +set_property LOC M16 [get_ports {ddram_a[2]}] +set_property SLEW FAST [get_ports {ddram_a[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}] + +# ddram:0.a +set_property LOC L18 [get_ports {ddram_a[3]}] +set_property SLEW FAST [get_ports {ddram_a[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}] + +# ddram:0.a +set_property LOC K21 [get_ports {ddram_a[4]}] +set_property SLEW FAST [get_ports {ddram_a[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}] + +# ddram:0.a +set_property LOC M18 [get_ports {ddram_a[5]}] +set_property SLEW FAST [get_ports {ddram_a[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}] + +# ddram:0.a +set_property LOC M21 [get_ports {ddram_a[6]}] +set_property SLEW FAST [get_ports {ddram_a[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}] + +# ddram:0.a +set_property LOC N20 [get_ports {ddram_a[7]}] +set_property SLEW FAST [get_ports {ddram_a[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}] + +# ddram:0.a +set_property LOC M20 [get_ports {ddram_a[8]}] +set_property SLEW FAST [get_ports {ddram_a[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}] + +# ddram:0.a +set_property LOC N19 [get_ports {ddram_a[9]}] +set_property SLEW FAST [get_ports {ddram_a[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}] + +# ddram:0.a +set_property LOC J21 [get_ports {ddram_a[10]}] +set_property SLEW FAST [get_ports {ddram_a[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}] + +# ddram:0.a +set_property LOC M22 [get_ports {ddram_a[11]}] +set_property SLEW FAST [get_ports {ddram_a[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}] + +# ddram:0.a +set_property LOC K22 [get_ports {ddram_a[12]}] +set_property SLEW FAST [get_ports {ddram_a[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}] + +# ddram:0.a +set_property LOC N18 [get_ports {ddram_a[13]}] +set_property SLEW FAST [get_ports {ddram_a[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}] + +# ddram:0.a +set_property LOC N22 [get_ports {ddram_a[14]}] +set_property SLEW FAST [get_ports {ddram_a[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}] + +# ddram:0.a +set_property LOC J22 [get_ports {ddram_a[15]}] +set_property SLEW FAST [get_ports {ddram_a[15]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[15]}] + +# ddram:0.ba +set_property LOC L19 [get_ports {ddram_ba[0]}] +set_property SLEW FAST [get_ports {ddram_ba[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}] + +# ddram:0.ba +set_property LOC J20 [get_ports {ddram_ba[1]}] +set_property SLEW FAST [get_ports {ddram_ba[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}] + +# ddram:0.ba +set_property LOC L20 [get_ports {ddram_ba[2]}] +set_property SLEW FAST [get_ports {ddram_ba[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}] + +# ddram:0.ras_n +set_property LOC H20 [get_ports {ddram_ras_n}] +set_property SLEW FAST [get_ports {ddram_ras_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}] + +# ddram:0.cas_n +set_property LOC K18 [get_ports {ddram_cas_n}] +set_property SLEW FAST [get_ports {ddram_cas_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}] + +# ddram:0.we_n +set_property LOC L16 [get_ports {ddram_we_n}] +set_property SLEW FAST [get_ports {ddram_we_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}] + +# ddram:0.dm +set_property LOC A19 [get_ports {ddram_dm[0]}] +set_property SLEW FAST [get_ports {ddram_dm[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[0]}] + +# ddram:0.dm +set_property LOC G22 [get_ports {ddram_dm[1]}] +set_property SLEW FAST [get_ports {ddram_dm[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[1]}] + +# ddram:0.dq +set_property LOC D19 [get_ports {ddram_dq[0]}] +set_property SLEW FAST [get_ports {ddram_dq[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[0]}] + +# ddram:0.dq +set_property LOC B20 [get_ports {ddram_dq[1]}] +set_property SLEW FAST [get_ports {ddram_dq[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[1]}] + +# ddram:0.dq +set_property LOC E19 [get_ports {ddram_dq[2]}] +set_property SLEW FAST [get_ports {ddram_dq[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[2]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[2]}] + +# ddram:0.dq +set_property LOC A20 [get_ports {ddram_dq[3]}] +set_property SLEW FAST [get_ports {ddram_dq[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[3]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[3]}] + +# ddram:0.dq +set_property LOC F19 [get_ports {ddram_dq[4]}] +set_property SLEW FAST [get_ports {ddram_dq[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[4]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[4]}] + +# ddram:0.dq +set_property LOC C19 [get_ports {ddram_dq[5]}] +set_property SLEW FAST [get_ports {ddram_dq[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[5]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[5]}] + +# ddram:0.dq +set_property LOC F20 [get_ports {ddram_dq[6]}] +set_property SLEW FAST [get_ports {ddram_dq[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[6]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[6]}] + +# ddram:0.dq +set_property LOC C18 [get_ports {ddram_dq[7]}] +set_property SLEW FAST [get_ports {ddram_dq[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[7]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[7]}] + +# ddram:0.dq +set_property LOC E22 [get_ports {ddram_dq[8]}] +set_property SLEW FAST [get_ports {ddram_dq[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[8]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[8]}] + +# ddram:0.dq +set_property LOC G21 [get_ports {ddram_dq[9]}] +set_property SLEW FAST [get_ports {ddram_dq[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[9]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[9]}] + +# ddram:0.dq +set_property LOC D20 [get_ports {ddram_dq[10]}] +set_property SLEW FAST [get_ports {ddram_dq[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[10]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[10]}] + +# ddram:0.dq +set_property LOC E21 [get_ports {ddram_dq[11]}] +set_property SLEW FAST [get_ports {ddram_dq[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[11]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[11]}] + +# ddram:0.dq +set_property LOC C22 [get_ports {ddram_dq[12]}] +set_property SLEW FAST [get_ports {ddram_dq[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[12]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[12]}] + +# ddram:0.dq +set_property LOC D21 [get_ports {ddram_dq[13]}] +set_property SLEW FAST [get_ports {ddram_dq[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[13]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[13]}] + +# ddram:0.dq +set_property LOC B22 [get_ports {ddram_dq[14]}] +set_property SLEW FAST [get_ports {ddram_dq[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[14]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[14]}] + +# ddram:0.dq +set_property LOC D22 [get_ports {ddram_dq[15]}] +set_property SLEW FAST [get_ports {ddram_dq[15]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[15]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[15]}] + +# ddram:0.dqs_p +set_property LOC F18 [get_ports {ddram_dqs_p[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}] + +# ddram:0.dqs_p +set_property LOC B21 [get_ports {ddram_dqs_p[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}] + +# ddram:0.dqs_n +set_property LOC E18 [get_ports {ddram_dqs_n[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}] + +# ddram:0.dqs_n +set_property LOC A21 [get_ports {ddram_dqs_n[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}] + +# ddram:0.clk_p +set_property LOC K17 [get_ports {ddram_clk_p}] +set_property SLEW FAST [get_ports {ddram_clk_p}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}] + +# ddram:0.clk_n +set_property LOC J17 [get_ports {ddram_clk_n}] +set_property SLEW FAST [get_ports {ddram_clk_n}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}] + +# ddram:0.cke +set_property LOC H22 [get_ports {ddram_cke}] +set_property SLEW FAST [get_ports {ddram_cke}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}] + +# ddram:0.odt +set_property LOC K19 [get_ports {ddram_odt}] +set_property SLEW FAST [get_ports {ddram_odt}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}] + +# ddram:0.reset_n +set_property LOC K16 [get_ports {ddram_reset_n}] +set_property SLEW FAST [get_ports {ddram_reset_n}] +set_property IOSTANDARD LVCMOS15 [get_ports {ddram_reset_n}] + +################################################################################ +# LEDs +################################################################################ + +set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led0 }]; +set_property -dict { PACKAGE_PIN H3 IOSTANDARD LVCMOS33 } [get_ports { led1 }]; +set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { led2 }]; +set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { led3 }]; + +############################################################################### +# SPI Flash +############################################################################### + +set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_cs_n }]; +set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_mosi }]; +set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_miso }]; +set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n }]; +set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }]; + + +################################################################################ +# Design constraints +################################################################################ + +set_property INTERNAL_VREF 0.750 [get_iobanks 34] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Div-1 [current_design] + +################################################################################ +# Clock constraints +################################################################################ + + +create_clock -name clk200_p -period 5.0 [get_nets clk200_p] + +################################################################################ +# False path constraints +################################################################################ + + +set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}] + +set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] + +set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]] diff --git a/fpga/clk_gen_plle2.vhd b/fpga/clk_gen_plle2.vhd index 750840b..dfe2ed9 100644 --- a/fpga/clk_gen_plle2.vhd +++ b/fpga/clk_gen_plle2.vhd @@ -40,6 +40,18 @@ architecture rtl of clock_generator is force_rst => '1'); begin case input_hz is + when 200000000 => + case output_hz is + when 100000000 => + return (clkin_period => 5.0, + clkfbout_mult => 8, + clkout_divide => 16, + divclk_divide => 1, + force_rst => '0'); + when others => + report "Unsupported output frequency" severity failure; + return bad_settings; + end case; when 100000000 => case output_hz is when 100000000 => diff --git a/fpga/top-acorn-cle-215.vhdl b/fpga/top-acorn-cle-215.vhdl new file mode 100644 index 0000000..bcbadad --- /dev/null +++ b/fpga/top-acorn-cle-215.vhdl @@ -0,0 +1,319 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +library work; +use work.wishbone_types.all; + +entity toplevel is + generic ( + MEMORY_SIZE : integer := 16384; + RAM_INIT_FILE : string := "firmware.hex"; + CLK_FREQUENCY : positive := 100000000; + USE_LITEDRAM : boolean := false; + NO_BRAM : boolean := false; + DISABLE_FLATTEN_CORE : boolean := false; + SPI_FLASH_OFFSET : integer := 10485760; + SPI_FLASH_DEF_CKDV : natural := 1; + SPI_FLASH_DEF_QUAD : boolean := true; + LOG_LENGTH : natural := 2048; + UART_IS_16550 : boolean := true + ); + port( + clk200_p : in std_ulogic; + clk200_n : in std_ulogic; + + -- P2 signals used as UART + uart_rx : in std_ulogic; + uart_tx : out std_ulogic; + + -- LEDs + led0 : out std_logic; + led1 : out std_logic; + led2 : out std_logic; + led3 : out std_logic; + + -- SPI + spi_flash_cs_n : out std_ulogic; + spi_flash_mosi : inout std_ulogic; + spi_flash_miso : inout std_ulogic; + spi_flash_wp_n : inout std_ulogic; + spi_flash_hold_n : inout std_ulogic; + + -- DRAM wires + ddram_a : out std_logic_vector(15 downto 0); + ddram_ba : out std_logic_vector(2 downto 0); + ddram_ras_n : out std_logic; + ddram_cas_n : out std_logic; + ddram_we_n : out std_logic; + ddram_dm : out std_logic_vector(1 downto 0); + ddram_dq : inout std_logic_vector(15 downto 0); + ddram_dqs_p : inout std_logic_vector(1 downto 0); + ddram_dqs_n : inout std_logic_vector(1 downto 0); + ddram_clk_p : out std_logic; + ddram_clk_n : out std_logic; + ddram_cke : out std_logic; + ddram_odt : out std_logic; + ddram_reset_n : out std_logic + ); +end entity toplevel; + +architecture behaviour of toplevel is + + -- Internal clock + signal ext_clk : std_ulogic; + + -- Reset signals: + signal soc_rst : std_ulogic; + signal pll_rst : std_ulogic; + + -- Internal clock signals: + signal system_clk : std_ulogic; + signal system_clk_locked : std_ulogic; + + -- DRAM main data wishbone connection + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + + -- DRAM control wishbone connection + signal wb_ext_io_in : wb_io_master_out; + signal wb_ext_io_out : wb_io_slave_out; + signal wb_ext_is_dram_csr : std_ulogic; + signal wb_ext_is_dram_init : std_ulogic; + + -- Control/status + signal core_alt_reset : std_ulogic; + + -- SPI flash + signal spi_sck : std_ulogic; + signal spi_cs_n : std_ulogic; + signal spi_sdat_o : std_ulogic_vector(3 downto 0); + signal spi_sdat_oe : std_ulogic_vector(3 downto 0); + signal spi_sdat_i : std_ulogic_vector(3 downto 0); + + -- Fixup various memory sizes based on generics + function get_bram_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return 0; + else + return MEMORY_SIZE; + end if; + end function; + + function get_payload_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return MEMORY_SIZE; + else + return 0; + end if; + end function; + + constant BRAM_SIZE : natural := get_bram_size; + constant PAYLOAD_SIZE : natural := get_payload_size; +begin + + -- Main SoC + soc0: entity work.soc + generic map( + MEMORY_SIZE => BRAM_SIZE, + RAM_INIT_FILE => RAM_INIT_FILE, + SIM => false, + CLK_FREQ => CLK_FREQUENCY, + HAS_DRAM => USE_LITEDRAM, + DRAM_SIZE => 1024 * 1024 * 1024, + DRAM_INIT_SIZE => PAYLOAD_SIZE, + DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE, + HAS_SPI_FLASH => true, + SPI_FLASH_DLINES => 4, + SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, + SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV, + SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD, + LOG_LENGTH => LOG_LENGTH, + UART0_IS_16550 => UART_IS_16550 + ) + port map ( + -- System signals + system_clk => system_clk, + rst => soc_rst, + + -- UART signals + uart0_txd => uart_tx, + uart0_rxd => uart_rx, + + -- SPI signals + spi_flash_sck => spi_sck, + spi_flash_cs_n => spi_cs_n, + spi_flash_sdat_o => spi_sdat_o, + spi_flash_sdat_oe => spi_sdat_oe, + spi_flash_sdat_i => spi_sdat_i, + + -- DRAM wishbone + wb_dram_in => wb_dram_in, + wb_dram_out => wb_dram_out, + wb_ext_io_in => wb_ext_io_in, + wb_ext_io_out => wb_ext_io_out, + wb_ext_is_dram_csr => wb_ext_is_dram_csr, + wb_ext_is_dram_init => wb_ext_is_dram_init, + alt_reset => core_alt_reset + ); + + -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2 + -- primitive of the FPGA as it's not a normal pin + -- + spi_flash_cs_n <= spi_cs_n; + spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z'; + spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z'; + spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z'; + spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z'; + spi_sdat_i(0) <= spi_flash_mosi; + spi_sdat_i(1) <= spi_flash_miso; + spi_sdat_i(2) <= spi_flash_wp_n; + spi_sdat_i(3) <= spi_flash_hold_n; + + STARTUPE2_INST: STARTUPE2 + port map ( + CLK => '0', + GSR => '0', + GTS => '0', + KEYCLEARB => '0', + PACK => '0', + USRCCLKO => spi_sck, + USRCCLKTS => '0', + USRDONEO => '1', + USRDONETS => '0' + ); + + clk200: IBUFDS + port map ( + i => clk200_p, + ib => clk200_n, + o => ext_clk + ); + + nodram: if not USE_LITEDRAM generate + signal ddram_clk_dummy : std_ulogic; + begin + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => false + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => '0', + pll_rst_out => pll_rst, + rst_out => soc_rst + ); + + clkgen: entity work.clock_generator + generic map( + CLK_INPUT_HZ => 200000000, + CLK_OUTPUT_HZ => CLK_FREQUENCY + ) + port map( + ext_clk => ext_clk, + pll_rst_in => pll_rst, + pll_clk_out => system_clk, + pll_locked_out => system_clk_locked + ); + + led0 <= soc_rst; + led1 <= pll_rst; + led2 <= not system_clk_locked; + led3 <= '0'; + core_alt_reset <= '0'; + + -- Vivado barfs on those differential signals if left + -- unconnected. So instanciate a diff. buffer and feed + -- it a constant '0'. + dummy_dram_clk: OBUFDS + port map ( + O => ddram_clk_p, + OB => ddram_clk_n, + I => ddram_clk_dummy + ); + ddram_clk_dummy <= '0'; + + end generate; + + has_dram: if USE_LITEDRAM generate + signal dram_init_done : std_ulogic; + signal dram_init_error : std_ulogic; + signal dram_sys_rst : std_ulogic; + begin + + -- Eventually dig out the frequency from the generator + -- but for now, assert it's 100Mhz + assert CLK_FREQUENCY = 100000000; + + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => false, + PLL_RESET_BITS => 18, + SOC_RESET_BITS => 1 + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => '1', + ext_rst_in => '0', + pll_rst_out => pll_rst, + rst_out => open + ); + + dram: entity work.litedram_wrapper + generic map( + DRAM_ABITS => 26, + DRAM_ALINES => 16, + DRAM_DLINES => 16, + DRAM_PORT_WIDTH => 128, + PAYLOAD_FILE => RAM_INIT_FILE, + PAYLOAD_SIZE => PAYLOAD_SIZE + ) + port map( + clk_in => ext_clk, + rst => pll_rst, + system_clk => system_clk, + system_reset => soc_rst, + core_alt_reset => core_alt_reset, + pll_locked => system_clk_locked, + + wb_in => wb_dram_in, + wb_out => wb_dram_out, + wb_ctrl_in => wb_ext_io_in, + wb_ctrl_out => wb_ext_io_out, + wb_ctrl_is_csr => wb_ext_is_dram_csr, + wb_ctrl_is_init => wb_ext_is_dram_init, + + init_done => dram_init_done, + init_error => dram_init_error, + + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => open, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_dqs_n => ddram_dqs_n, + ddram_clk_p => ddram_clk_p, + ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + ddram_reset_n => ddram_reset_n + ); + + led0 <= soc_rst; + led1 <= pll_rst; + led2 <= not dram_init_done or dram_init_error; + led3 <= not dram_init_error; -- Make it blink ? + end generate; +end architecture behaviour; diff --git a/litedram/gen-src/acorn-cle-215.yml b/litedram/gen-src/acorn-cle-215.yml new file mode 100644 index 0000000..bce467b --- /dev/null +++ b/litedram/gen-src/acorn-cle-215.yml @@ -0,0 +1,42 @@ +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# License: BSD + +{ + # General ------------------------------------------------------------------ + "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) + "cpu_variant":"standard", + "speedgrade": -2, # FPGA speedgrade + "memtype": "DDR3", # DRAM type + + # PHY ---------------------------------------------------------------------- + "cmd_delay": 0, # Command additional delay (in taps) + "cmd_latency": 0, # Command additional latency + "sdram_module": "MT41K512M16", # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 2, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": "A7DDRPHY", # Type of FPGA PHY + + # Electrical --------------------------------------------------------------- + "rtt_nom": "60ohm", # Nominal termination + "rtt_wr": "60ohm", # Write termination + "ron": "34ohm", # Output driver impedance + + # Frequency ---------------------------------------------------------------- + "input_clk_freq": 200e6, # Input clock frequency + "sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk) + "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency + + # Core --------------------------------------------------------------------- + "cmd_buffer_depth": 16, # Depth of the command buffer + + # User Ports --------------------------------------------------------------- + "user_ports": { + "native_0": { + "type": "native", + }, + }, + + # CSR Port ----------------------------------------------------------------- + "csr_alignment" : 32, + "csr_data_width" : 32, +} diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 08d42fb..eb677a8 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -140,7 +140,7 @@ def generate_one(t): def main(): - targets = ['arty','nexys-video', 'genesys2', 'sim'] + targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'sim'] for t in targets: generate_one(t) diff --git a/litedram/generated/acorn-cle-215/litedram-initmem.vhdl b/litedram/generated/acorn-cle-215/litedram-initmem.vhdl new file mode 100644 index 0000000..395602b --- /dev/null +++ b/litedram/generated/acorn-cle-215/litedram-initmem.vhdl @@ -0,0 +1,123 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +library work; +use work.wishbone_types.all; +use work.utils.all; + +entity dram_init_mem is + generic ( + EXTRA_PAYLOAD_FILE : string := ""; + EXTRA_PAYLOAD_SIZE : integer := 0 + ); + port ( + clk : in std_ulogic; + wb_in : in wb_io_master_out; + wb_out : out wb_io_slave_out + ); +end entity dram_init_mem; + +architecture rtl of dram_init_mem is + + constant INIT_RAM_SIZE : integer := 24576; + constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); + constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1); + constant INIT_RAM_FILE : string := "litedram_core.init"; + + type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + + -- XXX FIXME: Have a single init function called twice with + -- an offset as argument + procedure init_load_payload(ram: inout ram_t; filename: string) is + file payload_file : text open read_mode is filename; + variable ram_line : line; + variable temp_word : std_logic_vector(63 downto 0); + begin + for i in 0 to RND_PAYLOAD_SIZE-1 loop + exit when endfile(payload_file); + readline(payload_file, ram_line); + hread(ram_line, temp_word); + ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0); + ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32); + end loop; + assert endfile(payload_file) report "Payload too big !" severity failure; + end procedure; + + impure function init_load_ram(name : string) return ram_t is + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; + begin + report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & + " rounded to:" & integer'image(RND_PAYLOAD_SIZE); + report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & + " bytes using " & integer'image(INIT_RAM_ABITS) & + " address bits"; + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i*2) := temp_word(31 downto 0); + temp_ram(i*2+1) := temp_word(63 downto 32); + end loop; + if RND_PAYLOAD_SIZE /= 0 then + init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); + end if; + return temp_ram; + end function; + + impure function init_zero return ram_t is + variable temp_ram : ram_t := (others => (others => '0')); + begin + return temp_ram; + end function; + + impure function initialize_ram(filename: string) return ram_t is + begin + report "Opening file " & filename; + if filename'length = 0 then + return init_zero; + else + return init_load_ram(filename); + end if; + end function; + signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE); + + attribute ram_style : string; + attribute ram_style of init_ram: signal is "block"; + + signal obuf : std_ulogic_vector(31 downto 0); + signal oack : std_ulogic; +begin + + init_ram_0: process(clk) + variable adr : integer; + begin + if rising_edge(clk) then + oack <= '0'; + if (wb_in.cyc and wb_in.stb) = '1' then + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); + if wb_in.we = '0' then + obuf <= init_ram(adr); + else + for i in 0 to 3 loop + if wb_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_in.dat(((i + 1) * 8) - 1 downto i * 8); + end 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+00000000000a4b4f +0000000000000000 +00000000000000ff +000000000000ffff +0000000000ffffff +00000000ffffffff +000000ffffffffff +0000ffffffffffff +00ffffffffffffff +ffffffffffffffff +0000000000007830 diff --git a/litedram/generated/acorn-cle-215/litedram_core.v b/litedram/generated/acorn-cle-215/litedram_core.v new file mode 100644 index 0000000..19b8d15 --- /dev/null +++ b/litedram/generated/acorn-cle-215/litedram_core.v @@ -0,0 +1,17061 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:36:59 +//-------------------------------------------------------------------------------- +module litedram_core( + input wire clk, + input wire rst, + output wire pll_locked, + output wire [15:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire ddram_cs_n, + output wire [1:0] ddram_dm, + inout wire [15:0] ddram_dq, + inout wire [1:0] ddram_dqs_p, + inout wire [1:0] ddram_dqs_n, + output wire ddram_clk_p, + output wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + output wire init_done, + output wire init_error, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [25:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [127:0] user_port_native_0_rdata_data +); + +reg [13:0] soc_litedramcore_adr = 14'd0; +reg soc_litedramcore_we = 1'd0; +wire [31:0] soc_litedramcore_dat_w; +wire [31:0] soc_litedramcore_dat_r; +wire [29:0] soc_litedramcore_wishbone_adr; +wire [31:0] soc_litedramcore_wishbone_dat_w; +wire [31:0] soc_litedramcore_wishbone_dat_r; +wire [3:0] soc_litedramcore_wishbone_sel; +wire soc_litedramcore_wishbone_cyc; +wire soc_litedramcore_wishbone_stb; +reg soc_litedramcore_wishbone_ack = 1'd0; +wire soc_litedramcore_wishbone_we; +wire [2:0] soc_litedramcore_wishbone_cti; +wire [1:0] soc_litedramcore_wishbone_bte; +reg soc_litedramcore_wishbone_err = 1'd0; +wire sys_clk; +wire sys_rst; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire iodelay_clk; +wire iodelay_rst; +wire soc_reset; +wire soc_locked; +wire soc_clkin; +wire soc_clkout0; +wire soc_clkout_buf0; +wire soc_clkout1; +wire soc_clkout_buf1; +wire soc_clkout2; +wire soc_clkout_buf2; +wire soc_clkout3; +wire soc_clkout_buf3; +reg [3:0] soc_reset_counter = 4'd15; +reg soc_ic_reset = 1'd1; +reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg soc_a7ddrphy_wlevel_en_storage = 1'd0; +reg soc_a7ddrphy_wlevel_en_re = 1'd0; +wire soc_a7ddrphy_wlevel_strobe_re; +wire soc_a7ddrphy_wlevel_strobe_r; +wire soc_a7ddrphy_wlevel_strobe_we; +reg soc_a7ddrphy_wlevel_strobe_w = 1'd0; +wire soc_a7ddrphy_cdly_rst_re; +wire soc_a7ddrphy_cdly_rst_r; +wire soc_a7ddrphy_cdly_rst_we; +reg soc_a7ddrphy_cdly_rst_w = 1'd0; +wire soc_a7ddrphy_cdly_inc_re; +wire soc_a7ddrphy_cdly_inc_r; +wire soc_a7ddrphy_cdly_inc_we; +reg soc_a7ddrphy_cdly_inc_w = 1'd0; +reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0; +reg soc_a7ddrphy_dly_sel_re = 1'd0; +wire soc_a7ddrphy_rdly_dq_rst_re; +wire soc_a7ddrphy_rdly_dq_rst_r; +wire soc_a7ddrphy_rdly_dq_rst_we; +reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0; +wire soc_a7ddrphy_rdly_dq_inc_re; +wire soc_a7ddrphy_rdly_dq_inc_r; +wire soc_a7ddrphy_rdly_dq_inc_we; +reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0; +wire soc_a7ddrphy_rdly_dq_bitslip_rst_re; +wire soc_a7ddrphy_rdly_dq_bitslip_rst_r; +wire soc_a7ddrphy_rdly_dq_bitslip_rst_we; +reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +wire soc_a7ddrphy_rdly_dq_bitslip_re; +wire soc_a7ddrphy_rdly_dq_bitslip_r; +wire soc_a7ddrphy_rdly_dq_bitslip_we; +reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +wire [15:0] soc_a7ddrphy_dfi_p0_address; +wire [2:0] soc_a7ddrphy_dfi_p0_bank; +wire soc_a7ddrphy_dfi_p0_cas_n; +wire soc_a7ddrphy_dfi_p0_cs_n; +wire soc_a7ddrphy_dfi_p0_ras_n; +wire soc_a7ddrphy_dfi_p0_we_n; +wire soc_a7ddrphy_dfi_p0_cke; +wire soc_a7ddrphy_dfi_p0_odt; +wire soc_a7ddrphy_dfi_p0_reset_n; +wire soc_a7ddrphy_dfi_p0_act_n; +wire [31:0] soc_a7ddrphy_dfi_p0_wrdata; +wire soc_a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask; +wire soc_a7ddrphy_dfi_p0_rddata_en; +reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0; +reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0; +wire [15:0] soc_a7ddrphy_dfi_p1_address; +wire [2:0] soc_a7ddrphy_dfi_p1_bank; +wire soc_a7ddrphy_dfi_p1_cas_n; +wire soc_a7ddrphy_dfi_p1_cs_n; +wire soc_a7ddrphy_dfi_p1_ras_n; +wire soc_a7ddrphy_dfi_p1_we_n; +wire soc_a7ddrphy_dfi_p1_cke; +wire soc_a7ddrphy_dfi_p1_odt; +wire soc_a7ddrphy_dfi_p1_reset_n; +wire soc_a7ddrphy_dfi_p1_act_n; +wire [31:0] soc_a7ddrphy_dfi_p1_wrdata; +wire soc_a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask; +wire soc_a7ddrphy_dfi_p1_rddata_en; +reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0; +reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0; +wire [15:0] soc_a7ddrphy_dfi_p2_address; +wire [2:0] soc_a7ddrphy_dfi_p2_bank; +wire soc_a7ddrphy_dfi_p2_cas_n; +wire soc_a7ddrphy_dfi_p2_cs_n; +wire soc_a7ddrphy_dfi_p2_ras_n; +wire soc_a7ddrphy_dfi_p2_we_n; +wire soc_a7ddrphy_dfi_p2_cke; +wire soc_a7ddrphy_dfi_p2_odt; +wire soc_a7ddrphy_dfi_p2_reset_n; +wire soc_a7ddrphy_dfi_p2_act_n; +wire [31:0] soc_a7ddrphy_dfi_p2_wrdata; +wire soc_a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask; +wire soc_a7ddrphy_dfi_p2_rddata_en; +reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0; +reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0; +wire [15:0] soc_a7ddrphy_dfi_p3_address; +wire [2:0] soc_a7ddrphy_dfi_p3_bank; +wire soc_a7ddrphy_dfi_p3_cas_n; +wire soc_a7ddrphy_dfi_p3_cs_n; +wire soc_a7ddrphy_dfi_p3_ras_n; +wire soc_a7ddrphy_dfi_p3_we_n; +wire soc_a7ddrphy_dfi_p3_cke; +wire soc_a7ddrphy_dfi_p3_odt; +wire soc_a7ddrphy_dfi_p3_reset_n; +wire soc_a7ddrphy_dfi_p3_act_n; +wire [31:0] soc_a7ddrphy_dfi_p3_wrdata; +wire soc_a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask; +wire soc_a7ddrphy_dfi_p3_rddata_en; +reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0; +reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0; +wire soc_a7ddrphy_sd_clk_se_nodelay; +reg soc_a7ddrphy_dqs_oe = 1'd0; +reg soc_a7ddrphy_dqs_oe_delayed = 1'd0; +wire soc_a7ddrphy_dqspattern0; +wire soc_a7ddrphy_dqspattern1; +reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0; +wire [1:0] soc_a7ddrphy_dqs_i; +wire [1:0] soc_a7ddrphy_dqs_i_delayed; +wire soc_a7ddrphy_dqs_o_no_delay0; +wire soc_a7ddrphy_dqs_t0; +wire soc_a7ddrphy0; +wire soc_a7ddrphy_dqs_o_no_delay1; +wire soc_a7ddrphy_dqs_t1; +wire soc_a7ddrphy1; +wire soc_a7ddrphy_dq_oe; +reg soc_a7ddrphy_dq_oe_delayed = 1'd0; +wire soc_a7ddrphy_dq_o_nodelay0; +wire soc_a7ddrphy_dq_i_nodelay0; +wire soc_a7ddrphy_dq_i_delayed0; +wire soc_a7ddrphy_dq_t0; +wire [7:0] soc_a7ddrphy_dq_i_data0; +wire [7:0] soc_a7ddrphy_bitslip0_i; +reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip0_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip0_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay1; +wire soc_a7ddrphy_dq_i_nodelay1; +wire soc_a7ddrphy_dq_i_delayed1; +wire soc_a7ddrphy_dq_t1; +wire [7:0] soc_a7ddrphy_dq_i_data1; +wire [7:0] soc_a7ddrphy_bitslip1_i; +reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip1_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip1_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay2; +wire soc_a7ddrphy_dq_i_nodelay2; +wire soc_a7ddrphy_dq_i_delayed2; +wire soc_a7ddrphy_dq_t2; +wire [7:0] soc_a7ddrphy_dq_i_data2; +wire [7:0] soc_a7ddrphy_bitslip2_i; +reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip2_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip2_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay3; +wire soc_a7ddrphy_dq_i_nodelay3; +wire soc_a7ddrphy_dq_i_delayed3; +wire soc_a7ddrphy_dq_t3; +wire [7:0] soc_a7ddrphy_dq_i_data3; +wire [7:0] soc_a7ddrphy_bitslip3_i; +reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip3_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip3_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay4; +wire soc_a7ddrphy_dq_i_nodelay4; +wire soc_a7ddrphy_dq_i_delayed4; +wire soc_a7ddrphy_dq_t4; +wire [7:0] soc_a7ddrphy_dq_i_data4; +wire [7:0] soc_a7ddrphy_bitslip4_i; +reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip4_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip4_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay5; +wire soc_a7ddrphy_dq_i_nodelay5; +wire soc_a7ddrphy_dq_i_delayed5; +wire soc_a7ddrphy_dq_t5; +wire [7:0] soc_a7ddrphy_dq_i_data5; +wire [7:0] soc_a7ddrphy_bitslip5_i; +reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip5_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip5_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay6; +wire soc_a7ddrphy_dq_i_nodelay6; +wire soc_a7ddrphy_dq_i_delayed6; +wire soc_a7ddrphy_dq_t6; +wire [7:0] soc_a7ddrphy_dq_i_data6; +wire [7:0] soc_a7ddrphy_bitslip6_i; +reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip6_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip6_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay7; +wire soc_a7ddrphy_dq_i_nodelay7; +wire soc_a7ddrphy_dq_i_delayed7; +wire soc_a7ddrphy_dq_t7; +wire [7:0] soc_a7ddrphy_dq_i_data7; +wire [7:0] soc_a7ddrphy_bitslip7_i; +reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip7_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip7_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay8; +wire soc_a7ddrphy_dq_i_nodelay8; +wire soc_a7ddrphy_dq_i_delayed8; +wire soc_a7ddrphy_dq_t8; +wire [7:0] soc_a7ddrphy_dq_i_data8; +wire [7:0] soc_a7ddrphy_bitslip8_i; +reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip8_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip8_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay9; +wire soc_a7ddrphy_dq_i_nodelay9; +wire soc_a7ddrphy_dq_i_delayed9; +wire soc_a7ddrphy_dq_t9; +wire [7:0] soc_a7ddrphy_dq_i_data9; +wire [7:0] soc_a7ddrphy_bitslip9_i; +reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip9_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip9_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay10; +wire soc_a7ddrphy_dq_i_nodelay10; +wire soc_a7ddrphy_dq_i_delayed10; +wire soc_a7ddrphy_dq_t10; +wire [7:0] soc_a7ddrphy_dq_i_data10; +wire [7:0] soc_a7ddrphy_bitslip10_i; +reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip10_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip10_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay11; +wire soc_a7ddrphy_dq_i_nodelay11; +wire soc_a7ddrphy_dq_i_delayed11; +wire soc_a7ddrphy_dq_t11; +wire [7:0] soc_a7ddrphy_dq_i_data11; +wire [7:0] soc_a7ddrphy_bitslip11_i; +reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip11_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip11_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay12; +wire soc_a7ddrphy_dq_i_nodelay12; +wire soc_a7ddrphy_dq_i_delayed12; +wire soc_a7ddrphy_dq_t12; +wire [7:0] soc_a7ddrphy_dq_i_data12; +wire [7:0] soc_a7ddrphy_bitslip12_i; +reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip12_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip12_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay13; +wire soc_a7ddrphy_dq_i_nodelay13; +wire soc_a7ddrphy_dq_i_delayed13; +wire soc_a7ddrphy_dq_t13; +wire [7:0] soc_a7ddrphy_dq_i_data13; +wire [7:0] soc_a7ddrphy_bitslip13_i; +reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip13_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip13_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay14; +wire soc_a7ddrphy_dq_i_nodelay14; +wire soc_a7ddrphy_dq_i_delayed14; +wire soc_a7ddrphy_dq_t14; +wire [7:0] soc_a7ddrphy_dq_i_data14; +wire [7:0] soc_a7ddrphy_bitslip14_i; +reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip14_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip14_r = 24'd0; +wire soc_a7ddrphy_dq_o_nodelay15; +wire soc_a7ddrphy_dq_i_nodelay15; +wire soc_a7ddrphy_dq_i_delayed15; +wire soc_a7ddrphy_dq_t15; +wire [7:0] soc_a7ddrphy_dq_i_data15; +wire [7:0] soc_a7ddrphy_bitslip15_i; +reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0; +reg [3:0] soc_a7ddrphy_bitslip15_value = 4'd0; +reg [23:0] soc_a7ddrphy_bitslip15_r = 24'd0; +wire [7:0] soc_a7ddrphy_rddata_en; +reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0; +wire [3:0] soc_a7ddrphy_wrdata_en; +reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0; +wire [15:0] soc_litedramcore_inti_p0_address; +wire [2:0] soc_litedramcore_inti_p0_bank; +reg soc_litedramcore_inti_p0_cas_n = 1'd1; +reg soc_litedramcore_inti_p0_cs_n = 1'd1; +reg soc_litedramcore_inti_p0_ras_n = 1'd1; +reg soc_litedramcore_inti_p0_we_n = 1'd1; +wire soc_litedramcore_inti_p0_cke; +wire soc_litedramcore_inti_p0_odt; +wire soc_litedramcore_inti_p0_reset_n; +reg soc_litedramcore_inti_p0_act_n = 1'd1; +wire [31:0] soc_litedramcore_inti_p0_wrdata; +wire soc_litedramcore_inti_p0_wrdata_en; +wire [3:0] soc_litedramcore_inti_p0_wrdata_mask; +wire soc_litedramcore_inti_p0_rddata_en; +reg [31:0] soc_litedramcore_inti_p0_rddata = 32'd0; +reg soc_litedramcore_inti_p0_rddata_valid = 1'd0; +wire [15:0] soc_litedramcore_inti_p1_address; +wire [2:0] soc_litedramcore_inti_p1_bank; +reg soc_litedramcore_inti_p1_cas_n = 1'd1; +reg soc_litedramcore_inti_p1_cs_n = 1'd1; +reg soc_litedramcore_inti_p1_ras_n = 1'd1; +reg soc_litedramcore_inti_p1_we_n = 1'd1; +wire soc_litedramcore_inti_p1_cke; +wire soc_litedramcore_inti_p1_odt; +wire soc_litedramcore_inti_p1_reset_n; +reg soc_litedramcore_inti_p1_act_n = 1'd1; +wire [31:0] soc_litedramcore_inti_p1_wrdata; +wire soc_litedramcore_inti_p1_wrdata_en; +wire [3:0] soc_litedramcore_inti_p1_wrdata_mask; +wire soc_litedramcore_inti_p1_rddata_en; +reg [31:0] soc_litedramcore_inti_p1_rddata = 32'd0; +reg soc_litedramcore_inti_p1_rddata_valid = 1'd0; +wire [15:0] soc_litedramcore_inti_p2_address; +wire [2:0] soc_litedramcore_inti_p2_bank; +reg soc_litedramcore_inti_p2_cas_n = 1'd1; +reg soc_litedramcore_inti_p2_cs_n = 1'd1; +reg soc_litedramcore_inti_p2_ras_n = 1'd1; +reg soc_litedramcore_inti_p2_we_n = 1'd1; +wire soc_litedramcore_inti_p2_cke; +wire soc_litedramcore_inti_p2_odt; +wire soc_litedramcore_inti_p2_reset_n; +reg soc_litedramcore_inti_p2_act_n = 1'd1; +wire [31:0] soc_litedramcore_inti_p2_wrdata; +wire soc_litedramcore_inti_p2_wrdata_en; +wire [3:0] soc_litedramcore_inti_p2_wrdata_mask; +wire soc_litedramcore_inti_p2_rddata_en; +reg [31:0] soc_litedramcore_inti_p2_rddata = 32'd0; +reg soc_litedramcore_inti_p2_rddata_valid = 1'd0; +wire [15:0] soc_litedramcore_inti_p3_address; +wire [2:0] soc_litedramcore_inti_p3_bank; +reg soc_litedramcore_inti_p3_cas_n = 1'd1; +reg soc_litedramcore_inti_p3_cs_n = 1'd1; +reg soc_litedramcore_inti_p3_ras_n = 1'd1; +reg soc_litedramcore_inti_p3_we_n = 1'd1; +wire soc_litedramcore_inti_p3_cke; +wire soc_litedramcore_inti_p3_odt; +wire soc_litedramcore_inti_p3_reset_n; +reg soc_litedramcore_inti_p3_act_n = 1'd1; +wire [31:0] soc_litedramcore_inti_p3_wrdata; +wire soc_litedramcore_inti_p3_wrdata_en; +wire [3:0] soc_litedramcore_inti_p3_wrdata_mask; +wire soc_litedramcore_inti_p3_rddata_en; +reg [31:0] soc_litedramcore_inti_p3_rddata = 32'd0; +reg soc_litedramcore_inti_p3_rddata_valid = 1'd0; +wire [15:0] soc_litedramcore_slave_p0_address; +wire [2:0] soc_litedramcore_slave_p0_bank; +wire soc_litedramcore_slave_p0_cas_n; +wire soc_litedramcore_slave_p0_cs_n; +wire soc_litedramcore_slave_p0_ras_n; +wire soc_litedramcore_slave_p0_we_n; +wire soc_litedramcore_slave_p0_cke; +wire soc_litedramcore_slave_p0_odt; +wire soc_litedramcore_slave_p0_reset_n; +wire soc_litedramcore_slave_p0_act_n; +wire [31:0] soc_litedramcore_slave_p0_wrdata; +wire soc_litedramcore_slave_p0_wrdata_en; +wire [3:0] soc_litedramcore_slave_p0_wrdata_mask; +wire soc_litedramcore_slave_p0_rddata_en; +reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0; +reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; +wire [15:0] soc_litedramcore_slave_p1_address; +wire [2:0] soc_litedramcore_slave_p1_bank; +wire soc_litedramcore_slave_p1_cas_n; +wire soc_litedramcore_slave_p1_cs_n; +wire soc_litedramcore_slave_p1_ras_n; +wire soc_litedramcore_slave_p1_we_n; +wire soc_litedramcore_slave_p1_cke; +wire soc_litedramcore_slave_p1_odt; +wire soc_litedramcore_slave_p1_reset_n; +wire soc_litedramcore_slave_p1_act_n; +wire [31:0] soc_litedramcore_slave_p1_wrdata; +wire soc_litedramcore_slave_p1_wrdata_en; +wire [3:0] soc_litedramcore_slave_p1_wrdata_mask; +wire soc_litedramcore_slave_p1_rddata_en; +reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0; +reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; +wire [15:0] soc_litedramcore_slave_p2_address; +wire [2:0] soc_litedramcore_slave_p2_bank; +wire soc_litedramcore_slave_p2_cas_n; +wire soc_litedramcore_slave_p2_cs_n; +wire soc_litedramcore_slave_p2_ras_n; +wire soc_litedramcore_slave_p2_we_n; +wire soc_litedramcore_slave_p2_cke; +wire soc_litedramcore_slave_p2_odt; +wire soc_litedramcore_slave_p2_reset_n; +wire soc_litedramcore_slave_p2_act_n; +wire [31:0] soc_litedramcore_slave_p2_wrdata; +wire soc_litedramcore_slave_p2_wrdata_en; +wire [3:0] soc_litedramcore_slave_p2_wrdata_mask; +wire soc_litedramcore_slave_p2_rddata_en; +reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0; +reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; +wire [15:0] soc_litedramcore_slave_p3_address; +wire [2:0] soc_litedramcore_slave_p3_bank; +wire soc_litedramcore_slave_p3_cas_n; +wire soc_litedramcore_slave_p3_cs_n; +wire soc_litedramcore_slave_p3_ras_n; +wire soc_litedramcore_slave_p3_we_n; +wire soc_litedramcore_slave_p3_cke; +wire soc_litedramcore_slave_p3_odt; +wire soc_litedramcore_slave_p3_reset_n; +wire soc_litedramcore_slave_p3_act_n; +wire [31:0] soc_litedramcore_slave_p3_wrdata; +wire soc_litedramcore_slave_p3_wrdata_en; +wire [3:0] soc_litedramcore_slave_p3_wrdata_mask; +wire soc_litedramcore_slave_p3_rddata_en; +reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0; +reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [15:0] soc_litedramcore_master_p0_address = 16'd0; +reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; +reg soc_litedramcore_master_p0_cas_n = 1'd1; +reg soc_litedramcore_master_p0_cs_n = 1'd1; +reg soc_litedramcore_master_p0_ras_n = 1'd1; +reg soc_litedramcore_master_p0_we_n = 1'd1; +reg soc_litedramcore_master_p0_cke = 1'd0; +reg soc_litedramcore_master_p0_odt = 1'd0; +reg soc_litedramcore_master_p0_reset_n = 1'd0; +reg soc_litedramcore_master_p0_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0; +reg soc_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_master_p0_rddata; +wire soc_litedramcore_master_p0_rddata_valid; +reg [15:0] soc_litedramcore_master_p1_address = 16'd0; +reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; +reg soc_litedramcore_master_p1_cas_n = 1'd1; +reg soc_litedramcore_master_p1_cs_n = 1'd1; +reg soc_litedramcore_master_p1_ras_n = 1'd1; +reg soc_litedramcore_master_p1_we_n = 1'd1; +reg soc_litedramcore_master_p1_cke = 1'd0; +reg soc_litedramcore_master_p1_odt = 1'd0; +reg soc_litedramcore_master_p1_reset_n = 1'd0; +reg soc_litedramcore_master_p1_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0; +reg soc_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_master_p1_rddata; +wire soc_litedramcore_master_p1_rddata_valid; +reg [15:0] soc_litedramcore_master_p2_address = 16'd0; +reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; +reg soc_litedramcore_master_p2_cas_n = 1'd1; +reg soc_litedramcore_master_p2_cs_n = 1'd1; +reg soc_litedramcore_master_p2_ras_n = 1'd1; +reg soc_litedramcore_master_p2_we_n = 1'd1; +reg soc_litedramcore_master_p2_cke = 1'd0; +reg soc_litedramcore_master_p2_odt = 1'd0; +reg soc_litedramcore_master_p2_reset_n = 1'd0; +reg soc_litedramcore_master_p2_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0; +reg soc_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_master_p2_rddata; +wire soc_litedramcore_master_p2_rddata_valid; +reg [15:0] soc_litedramcore_master_p3_address = 16'd0; +reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; +reg soc_litedramcore_master_p3_cas_n = 1'd1; +reg soc_litedramcore_master_p3_cs_n = 1'd1; +reg soc_litedramcore_master_p3_ras_n = 1'd1; +reg soc_litedramcore_master_p3_we_n = 1'd1; +reg soc_litedramcore_master_p3_cke = 1'd0; +reg soc_litedramcore_master_p3_odt = 1'd0; +reg soc_litedramcore_master_p3_reset_n = 1'd0; +reg soc_litedramcore_master_p3_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0; +reg soc_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_master_p3_rddata; +wire soc_litedramcore_master_p3_rddata_valid; +wire soc_litedramcore_sel; +wire soc_litedramcore_cke; +wire soc_litedramcore_odt; +wire soc_litedramcore_reset_n; +reg [3:0] soc_litedramcore_storage = 4'd1; +reg soc_litedramcore_re = 1'd0; +reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector0_command_re = 1'd0; +wire soc_litedramcore_phaseinjector0_command_issue_re; +wire soc_litedramcore_phaseinjector0_command_issue_r; +wire soc_litedramcore_phaseinjector0_command_issue_we; +reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [15:0] soc_litedramcore_phaseinjector0_address_storage = 16'd0; +reg soc_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector0_status = 32'd0; +wire soc_litedramcore_phaseinjector0_we; +reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector1_command_re = 1'd0; +wire soc_litedramcore_phaseinjector1_command_issue_re; +wire soc_litedramcore_phaseinjector1_command_issue_r; +wire soc_litedramcore_phaseinjector1_command_issue_we; +reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [15:0] soc_litedramcore_phaseinjector1_address_storage = 16'd0; +reg soc_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector1_status = 32'd0; +wire soc_litedramcore_phaseinjector1_we; +reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector2_command_re = 1'd0; +wire soc_litedramcore_phaseinjector2_command_issue_re; +wire soc_litedramcore_phaseinjector2_command_issue_r; +wire soc_litedramcore_phaseinjector2_command_issue_we; +reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [15:0] soc_litedramcore_phaseinjector2_address_storage = 16'd0; +reg soc_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector2_status = 32'd0; +wire soc_litedramcore_phaseinjector2_we; +reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector3_command_re = 1'd0; +wire soc_litedramcore_phaseinjector3_command_issue_re; +wire soc_litedramcore_phaseinjector3_command_issue_r; +wire soc_litedramcore_phaseinjector3_command_issue_we; +reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [15:0] soc_litedramcore_phaseinjector3_address_storage = 16'd0; +reg soc_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector3_status = 32'd0; +wire soc_litedramcore_phaseinjector3_we; +wire soc_litedramcore_interface_bank0_valid; +wire soc_litedramcore_interface_bank0_ready; +wire soc_litedramcore_interface_bank0_we; +wire [22:0] soc_litedramcore_interface_bank0_addr; +wire soc_litedramcore_interface_bank0_lock; +wire soc_litedramcore_interface_bank0_wdata_ready; +wire soc_litedramcore_interface_bank0_rdata_valid; +wire soc_litedramcore_interface_bank1_valid; +wire soc_litedramcore_interface_bank1_ready; +wire soc_litedramcore_interface_bank1_we; +wire [22:0] soc_litedramcore_interface_bank1_addr; +wire soc_litedramcore_interface_bank1_lock; +wire soc_litedramcore_interface_bank1_wdata_ready; +wire soc_litedramcore_interface_bank1_rdata_valid; +wire soc_litedramcore_interface_bank2_valid; +wire soc_litedramcore_interface_bank2_ready; +wire soc_litedramcore_interface_bank2_we; +wire [22:0] soc_litedramcore_interface_bank2_addr; +wire soc_litedramcore_interface_bank2_lock; +wire soc_litedramcore_interface_bank2_wdata_ready; +wire soc_litedramcore_interface_bank2_rdata_valid; +wire soc_litedramcore_interface_bank3_valid; +wire soc_litedramcore_interface_bank3_ready; +wire soc_litedramcore_interface_bank3_we; +wire [22:0] soc_litedramcore_interface_bank3_addr; +wire soc_litedramcore_interface_bank3_lock; +wire soc_litedramcore_interface_bank3_wdata_ready; +wire soc_litedramcore_interface_bank3_rdata_valid; +wire soc_litedramcore_interface_bank4_valid; +wire soc_litedramcore_interface_bank4_ready; +wire soc_litedramcore_interface_bank4_we; +wire [22:0] soc_litedramcore_interface_bank4_addr; +wire soc_litedramcore_interface_bank4_lock; +wire soc_litedramcore_interface_bank4_wdata_ready; +wire soc_litedramcore_interface_bank4_rdata_valid; +wire soc_litedramcore_interface_bank5_valid; +wire soc_litedramcore_interface_bank5_ready; +wire soc_litedramcore_interface_bank5_we; +wire [22:0] soc_litedramcore_interface_bank5_addr; +wire soc_litedramcore_interface_bank5_lock; +wire soc_litedramcore_interface_bank5_wdata_ready; +wire soc_litedramcore_interface_bank5_rdata_valid; +wire soc_litedramcore_interface_bank6_valid; +wire soc_litedramcore_interface_bank6_ready; +wire soc_litedramcore_interface_bank6_we; +wire [22:0] soc_litedramcore_interface_bank6_addr; +wire soc_litedramcore_interface_bank6_lock; +wire soc_litedramcore_interface_bank6_wdata_ready; +wire soc_litedramcore_interface_bank6_rdata_valid; +wire soc_litedramcore_interface_bank7_valid; +wire soc_litedramcore_interface_bank7_ready; +wire soc_litedramcore_interface_bank7_we; +wire [22:0] soc_litedramcore_interface_bank7_addr; +wire soc_litedramcore_interface_bank7_lock; +wire soc_litedramcore_interface_bank7_wdata_ready; +wire soc_litedramcore_interface_bank7_rdata_valid; +reg [127:0] soc_litedramcore_interface_wdata = 128'd0; +reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0; +wire [127:0] soc_litedramcore_interface_rdata; +reg [15:0] soc_litedramcore_dfi_p0_address = 16'd0; +reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; +reg soc_litedramcore_dfi_p0_cas_n = 1'd1; +reg soc_litedramcore_dfi_p0_cs_n = 1'd1; +reg soc_litedramcore_dfi_p0_ras_n = 1'd1; +reg soc_litedramcore_dfi_p0_we_n = 1'd1; +wire soc_litedramcore_dfi_p0_cke; +wire soc_litedramcore_dfi_p0_odt; +wire soc_litedramcore_dfi_p0_reset_n; +reg soc_litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p0_wrdata; +reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask; +reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_dfi_p0_rddata; +wire soc_litedramcore_dfi_p0_rddata_valid; +reg [15:0] soc_litedramcore_dfi_p1_address = 16'd0; +reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; +reg soc_litedramcore_dfi_p1_cas_n = 1'd1; +reg soc_litedramcore_dfi_p1_cs_n = 1'd1; +reg soc_litedramcore_dfi_p1_ras_n = 1'd1; +reg soc_litedramcore_dfi_p1_we_n = 1'd1; +wire soc_litedramcore_dfi_p1_cke; +wire soc_litedramcore_dfi_p1_odt; +wire soc_litedramcore_dfi_p1_reset_n; +reg soc_litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p1_wrdata; +reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask; +reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_dfi_p1_rddata; +wire soc_litedramcore_dfi_p1_rddata_valid; +reg [15:0] soc_litedramcore_dfi_p2_address = 16'd0; +reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; +reg soc_litedramcore_dfi_p2_cas_n = 1'd1; +reg soc_litedramcore_dfi_p2_cs_n = 1'd1; +reg soc_litedramcore_dfi_p2_ras_n = 1'd1; +reg soc_litedramcore_dfi_p2_we_n = 1'd1; +wire soc_litedramcore_dfi_p2_cke; +wire soc_litedramcore_dfi_p2_odt; +wire soc_litedramcore_dfi_p2_reset_n; +reg soc_litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p2_wrdata; +reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask; +reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_dfi_p2_rddata; +wire soc_litedramcore_dfi_p2_rddata_valid; +reg [15:0] soc_litedramcore_dfi_p3_address = 16'd0; +reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; +reg soc_litedramcore_dfi_p3_cas_n = 1'd1; +reg soc_litedramcore_dfi_p3_cs_n = 1'd1; +reg soc_litedramcore_dfi_p3_ras_n = 1'd1; +reg soc_litedramcore_dfi_p3_we_n = 1'd1; +wire soc_litedramcore_dfi_p3_cke; +wire soc_litedramcore_dfi_p3_odt; +wire soc_litedramcore_dfi_p3_reset_n; +reg soc_litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p3_wrdata; +reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask; +reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_dfi_p3_rddata; +wire soc_litedramcore_dfi_p3_rddata_valid; +reg soc_litedramcore_cmd_valid = 1'd0; +reg soc_litedramcore_cmd_ready = 1'd0; +reg soc_litedramcore_cmd_last = 1'd0; +reg [15:0] soc_litedramcore_cmd_payload_a = 16'd0; +reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; +reg soc_litedramcore_cmd_payload_cas = 1'd0; +reg soc_litedramcore_cmd_payload_ras = 1'd0; +reg soc_litedramcore_cmd_payload_we = 1'd0; +reg soc_litedramcore_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_cmd_payload_is_write = 1'd0; +wire soc_litedramcore_wants_refresh; +wire soc_litedramcore_wants_zqcs; +wire soc_litedramcore_timer_wait; +wire soc_litedramcore_timer_done0; +wire [9:0] soc_litedramcore_timer_count0; +wire soc_litedramcore_timer_done1; +reg [9:0] soc_litedramcore_timer_count1 = 10'd781; +wire soc_litedramcore_postponer_req_i; +reg soc_litedramcore_postponer_req_o = 1'd0; +reg soc_litedramcore_postponer_count = 1'd0; +reg soc_litedramcore_sequencer_start0 = 1'd0; +wire soc_litedramcore_sequencer_done0; +wire soc_litedramcore_sequencer_start1; +reg soc_litedramcore_sequencer_done1 = 1'd0; +reg [6:0] soc_litedramcore_sequencer_counter = 7'd0; +reg soc_litedramcore_sequencer_count = 1'd0; +wire soc_litedramcore_zqcs_timer_wait; +wire soc_litedramcore_zqcs_timer_done0; +wire [26:0] soc_litedramcore_zqcs_timer_count0; +wire soc_litedramcore_zqcs_timer_done1; +reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg soc_litedramcore_zqcs_executer_start = 1'd0; +reg soc_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0; +wire soc_litedramcore_bankmachine0_req_valid; +wire soc_litedramcore_bankmachine0_req_ready; +wire soc_litedramcore_bankmachine0_req_we; +wire [22:0] soc_litedramcore_bankmachine0_req_addr; +wire soc_litedramcore_bankmachine0_req_lock; +reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine0_refresh_req; +reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [15:0] soc_litedramcore_bankmachine0_cmd_payload_a = 16'd0; +wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba; +reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [22:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [25:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [25:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [25:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [25:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] soc_litedramcore_bankmachine0_row = 16'd0; +reg soc_litedramcore_bankmachine0_row_opened = 1'd0; +wire soc_litedramcore_bankmachine0_row_hit; +reg soc_litedramcore_bankmachine0_row_open = 1'd0; +reg soc_litedramcore_bankmachine0_row_close = 1'd0; +reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine1_req_valid; +wire soc_litedramcore_bankmachine1_req_ready; +wire soc_litedramcore_bankmachine1_req_we; +wire [22:0] soc_litedramcore_bankmachine1_req_addr; +wire soc_litedramcore_bankmachine1_req_lock; +reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine1_refresh_req; +reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [15:0] soc_litedramcore_bankmachine1_cmd_payload_a = 16'd0; +wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba; +reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [22:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [25:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [25:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [25:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [25:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] soc_litedramcore_bankmachine1_row = 16'd0; +reg soc_litedramcore_bankmachine1_row_opened = 1'd0; +wire soc_litedramcore_bankmachine1_row_hit; +reg soc_litedramcore_bankmachine1_row_open = 1'd0; +reg soc_litedramcore_bankmachine1_row_close = 1'd0; +reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine2_req_valid; +wire soc_litedramcore_bankmachine2_req_ready; +wire soc_litedramcore_bankmachine2_req_we; +wire [22:0] soc_litedramcore_bankmachine2_req_addr; +wire soc_litedramcore_bankmachine2_req_lock; +reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine2_refresh_req; +reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [15:0] soc_litedramcore_bankmachine2_cmd_payload_a = 16'd0; +wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba; +reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [22:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [25:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [25:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [25:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [25:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] soc_litedramcore_bankmachine2_row = 16'd0; +reg soc_litedramcore_bankmachine2_row_opened = 1'd0; +wire soc_litedramcore_bankmachine2_row_hit; +reg soc_litedramcore_bankmachine2_row_open = 1'd0; +reg soc_litedramcore_bankmachine2_row_close = 1'd0; +reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine3_req_valid; +wire soc_litedramcore_bankmachine3_req_ready; +wire soc_litedramcore_bankmachine3_req_we; +wire [22:0] soc_litedramcore_bankmachine3_req_addr; +wire soc_litedramcore_bankmachine3_req_lock; +reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine3_refresh_req; +reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [15:0] soc_litedramcore_bankmachine3_cmd_payload_a = 16'd0; +wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba; +reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [22:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [25:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [25:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [25:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [25:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] soc_litedramcore_bankmachine3_row = 16'd0; +reg soc_litedramcore_bankmachine3_row_opened = 1'd0; +wire soc_litedramcore_bankmachine3_row_hit; +reg soc_litedramcore_bankmachine3_row_open = 1'd0; +reg soc_litedramcore_bankmachine3_row_close = 1'd0; +reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine4_req_valid; +wire soc_litedramcore_bankmachine4_req_ready; +wire soc_litedramcore_bankmachine4_req_we; +wire [22:0] soc_litedramcore_bankmachine4_req_addr; +wire soc_litedramcore_bankmachine4_req_lock; +reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine4_refresh_req; +reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [15:0] soc_litedramcore_bankmachine4_cmd_payload_a = 16'd0; +wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba; +reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [22:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [25:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [25:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [25:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [25:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] soc_litedramcore_bankmachine4_row = 16'd0; +reg soc_litedramcore_bankmachine4_row_opened = 1'd0; +wire soc_litedramcore_bankmachine4_row_hit; +reg soc_litedramcore_bankmachine4_row_open = 1'd0; +reg soc_litedramcore_bankmachine4_row_close = 1'd0; +reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine5_req_valid; +wire soc_litedramcore_bankmachine5_req_ready; +wire soc_litedramcore_bankmachine5_req_we; +wire [22:0] soc_litedramcore_bankmachine5_req_addr; +wire soc_litedramcore_bankmachine5_req_lock; +reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine5_refresh_req; +reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [15:0] soc_litedramcore_bankmachine5_cmd_payload_a = 16'd0; +wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba; +reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [22:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [25:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [25:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [25:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [25:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] soc_litedramcore_bankmachine5_row = 16'd0; +reg soc_litedramcore_bankmachine5_row_opened = 1'd0; +wire soc_litedramcore_bankmachine5_row_hit; +reg soc_litedramcore_bankmachine5_row_open = 1'd0; +reg soc_litedramcore_bankmachine5_row_close = 1'd0; +reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine6_req_valid; +wire soc_litedramcore_bankmachine6_req_ready; +wire soc_litedramcore_bankmachine6_req_we; +wire [22:0] soc_litedramcore_bankmachine6_req_addr; +wire soc_litedramcore_bankmachine6_req_lock; +reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine6_refresh_req; +reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [15:0] soc_litedramcore_bankmachine6_cmd_payload_a = 16'd0; +wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba; +reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [22:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [25:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [25:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [25:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [25:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] soc_litedramcore_bankmachine6_row = 16'd0; +reg soc_litedramcore_bankmachine6_row_opened = 1'd0; +wire soc_litedramcore_bankmachine6_row_hit; +reg soc_litedramcore_bankmachine6_row_open = 1'd0; +reg soc_litedramcore_bankmachine6_row_close = 1'd0; +reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine7_req_valid; +wire soc_litedramcore_bankmachine7_req_ready; +wire soc_litedramcore_bankmachine7_req_we; +wire [22:0] soc_litedramcore_bankmachine7_req_addr; +wire soc_litedramcore_bankmachine7_req_lock; +reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine7_refresh_req; +reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [15:0] soc_litedramcore_bankmachine7_cmd_payload_a = 16'd0; +wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba; +reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [22:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [25:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [25:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [25:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [25:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [25:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [22:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [22:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last; +wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; +wire [22:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] soc_litedramcore_bankmachine7_row = 16'd0; +reg soc_litedramcore_bankmachine7_row_opened = 1'd0; +wire soc_litedramcore_bankmachine7_row_hit; +reg soc_litedramcore_bankmachine7_row_open = 1'd0; +reg soc_litedramcore_bankmachine7_row_close = 1'd0; +reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0; +wire soc_litedramcore_ras_allowed; +wire soc_litedramcore_cas_allowed; +reg soc_litedramcore_choose_cmd_want_reads = 1'd0; +reg soc_litedramcore_choose_cmd_want_writes = 1'd0; +reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; +reg soc_litedramcore_choose_cmd_want_activates = 1'd0; +wire soc_litedramcore_choose_cmd_cmd_valid; +reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [15:0] soc_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba; +reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire soc_litedramcore_choose_cmd_cmd_payload_is_read; +wire soc_litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] soc_litedramcore_choose_cmd_request; +reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; +wire soc_litedramcore_choose_cmd_ce; +reg soc_litedramcore_choose_req_want_reads = 1'd0; +reg soc_litedramcore_choose_req_want_writes = 1'd0; +reg soc_litedramcore_choose_req_want_cmds = 1'd0; +reg soc_litedramcore_choose_req_want_activates = 1'd0; +wire soc_litedramcore_choose_req_cmd_valid; +reg soc_litedramcore_choose_req_cmd_ready = 1'd0; +wire [15:0] soc_litedramcore_choose_req_cmd_payload_a; +wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba; +reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; +wire soc_litedramcore_choose_req_cmd_payload_is_cmd; +wire soc_litedramcore_choose_req_cmd_payload_is_read; +wire soc_litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; +wire [7:0] soc_litedramcore_choose_req_request; +reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; +wire soc_litedramcore_choose_req_ce; +reg [15:0] soc_litedramcore_nop_a = 16'd0; +reg [2:0] soc_litedramcore_nop_ba = 3'd0; +reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; +reg soc_litedramcore_steerer0 = 1'd1; +reg soc_litedramcore_steerer1 = 1'd1; +reg soc_litedramcore_steerer2 = 1'd1; +reg soc_litedramcore_steerer3 = 1'd1; +reg soc_litedramcore_steerer4 = 1'd1; +reg soc_litedramcore_steerer5 = 1'd1; +reg soc_litedramcore_steerer6 = 1'd1; +reg soc_litedramcore_steerer7 = 1'd1; +wire soc_litedramcore_trrdcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_trrdcon_ready = 1'd0; +reg soc_litedramcore_trrdcon_count = 1'd0; +wire soc_litedramcore_tfawcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_tfawcon_ready = 1'd1; +wire [2:0] soc_litedramcore_tfawcon_count; +reg [4:0] soc_litedramcore_tfawcon_window = 5'd0; +wire soc_litedramcore_tccdcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_tccdcon_ready = 1'd0; +reg soc_litedramcore_tccdcon_count = 1'd0; +wire soc_litedramcore_twtrcon_valid; +(* dont_touch = "true" *) reg soc_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; +wire soc_litedramcore_read_available; +wire soc_litedramcore_write_available; +reg soc_litedramcore_en0 = 1'd0; +wire soc_litedramcore_max_time0; +reg [4:0] soc_litedramcore_time0 = 5'd0; +reg soc_litedramcore_en1 = 1'd0; +wire soc_litedramcore_max_time1; +reg [3:0] soc_litedramcore_time1 = 4'd0; +wire soc_litedramcore_go_to_refresh; +reg soc_init_done_storage = 1'd0; +reg soc_init_done_re = 1'd0; +reg soc_init_error_storage = 1'd0; +reg soc_init_error_re = 1'd0; +wire [29:0] soc_wb_bus_adr; +wire [31:0] soc_wb_bus_dat_w; +wire [31:0] soc_wb_bus_dat_r; +wire [3:0] soc_wb_bus_sel; +wire soc_wb_bus_cyc; +wire soc_wb_bus_stb; +wire soc_wb_bus_ack; +wire soc_wb_bus_we; +wire [2:0] soc_wb_bus_cti; +wire [1:0] soc_wb_bus_bte; +wire soc_wb_bus_err; +wire soc_user_port_cmd_valid; +wire soc_user_port_cmd_ready; +wire soc_user_port_cmd_payload_we; +wire [25:0] soc_user_port_cmd_payload_addr; +wire soc_user_port_wdata_valid; +wire soc_user_port_wdata_ready; +wire [127:0] soc_user_port_wdata_payload_data; +wire [15:0] soc_user_port_wdata_payload_we; +wire soc_user_port_rdata_valid; +wire soc_user_port_rdata_ready; +wire [127:0] soc_user_port_rdata_payload_data; +reg vns_state = 1'd0; +reg vns_next_state = 1'd0; +wire vns_pll_fb; +reg [1:0] vns_refresher_state = 2'd0; +reg [1:0] vns_refresher_next_state = 2'd0; +reg [3:0] vns_bankmachine0_state = 4'd0; +reg [3:0] vns_bankmachine0_next_state = 4'd0; +reg [3:0] vns_bankmachine1_state = 4'd0; +reg [3:0] vns_bankmachine1_next_state = 4'd0; +reg [3:0] vns_bankmachine2_state = 4'd0; +reg [3:0] vns_bankmachine2_next_state = 4'd0; +reg [3:0] vns_bankmachine3_state = 4'd0; +reg [3:0] vns_bankmachine3_next_state = 4'd0; +reg [3:0] vns_bankmachine4_state = 4'd0; +reg [3:0] vns_bankmachine4_next_state = 4'd0; +reg [3:0] vns_bankmachine5_state = 4'd0; +reg [3:0] vns_bankmachine5_next_state = 4'd0; +reg [3:0] vns_bankmachine6_state = 4'd0; +reg [3:0] vns_bankmachine6_next_state = 4'd0; +reg [3:0] vns_bankmachine7_state = 4'd0; +reg [3:0] vns_bankmachine7_next_state = 4'd0; +reg [3:0] vns_multiplexer_state = 4'd0; +reg [3:0] vns_multiplexer_next_state = 4'd0; +wire vns_roundrobin0_request; +wire vns_roundrobin0_grant; +wire vns_roundrobin0_ce; +wire vns_roundrobin1_request; +wire vns_roundrobin1_grant; +wire vns_roundrobin1_ce; +wire vns_roundrobin2_request; +wire vns_roundrobin2_grant; +wire vns_roundrobin2_ce; +wire vns_roundrobin3_request; +wire vns_roundrobin3_grant; +wire vns_roundrobin3_ce; +wire vns_roundrobin4_request; +wire vns_roundrobin4_grant; +wire vns_roundrobin4_ce; +wire vns_roundrobin5_request; +wire vns_roundrobin5_grant; +wire vns_roundrobin5_ce; +wire vns_roundrobin6_request; +wire vns_roundrobin6_grant; +wire vns_roundrobin6_ce; +wire vns_roundrobin7_request; +wire vns_roundrobin7_grant; +wire vns_roundrobin7_ce; +reg vns_locked0 = 1'd0; +reg vns_locked1 = 1'd0; +reg vns_locked2 = 1'd0; +reg vns_locked3 = 1'd0; +reg vns_locked4 = 1'd0; +reg vns_locked5 = 1'd0; +reg vns_locked6 = 1'd0; +reg vns_locked7 = 1'd0; +reg vns_new_master_wdata_ready0 = 1'd0; +reg vns_new_master_wdata_ready1 = 1'd0; +reg vns_new_master_wdata_ready2 = 1'd0; +reg vns_new_master_rdata_valid0 = 1'd0; +reg vns_new_master_rdata_valid1 = 1'd0; +reg vns_new_master_rdata_valid2 = 1'd0; +reg vns_new_master_rdata_valid3 = 1'd0; +reg vns_new_master_rdata_valid4 = 1'd0; +reg vns_new_master_rdata_valid5 = 1'd0; +reg vns_new_master_rdata_valid6 = 1'd0; +reg vns_new_master_rdata_valid7 = 1'd0; +reg vns_new_master_rdata_valid8 = 1'd0; +wire [13:0] vns_interface0_bank_bus_adr; +wire vns_interface0_bank_bus_we; +wire [31:0] vns_interface0_bank_bus_dat_w; +reg [31:0] vns_interface0_bank_bus_dat_r = 32'd0; +wire vns_csrbank0_init_done0_re; +wire vns_csrbank0_init_done0_r; +wire vns_csrbank0_init_done0_we; +wire vns_csrbank0_init_done0_w; +wire vns_csrbank0_init_error0_re; +wire vns_csrbank0_init_error0_r; +wire vns_csrbank0_init_error0_we; +wire vns_csrbank0_init_error0_w; +wire vns_csrbank0_sel; +wire [13:0] vns_interface1_bank_bus_adr; +wire vns_interface1_bank_bus_we; +wire [31:0] vns_interface1_bank_bus_dat_w; +reg [31:0] vns_interface1_bank_bus_dat_r = 32'd0; +wire vns_csrbank1_half_sys8x_taps0_re; +wire [4:0] vns_csrbank1_half_sys8x_taps0_r; +wire vns_csrbank1_half_sys8x_taps0_we; +wire [4:0] vns_csrbank1_half_sys8x_taps0_w; +wire vns_csrbank1_wlevel_en0_re; +wire vns_csrbank1_wlevel_en0_r; +wire vns_csrbank1_wlevel_en0_we; +wire vns_csrbank1_wlevel_en0_w; +wire vns_csrbank1_dly_sel0_re; +wire [1:0] vns_csrbank1_dly_sel0_r; +wire vns_csrbank1_dly_sel0_we; +wire [1:0] vns_csrbank1_dly_sel0_w; +wire vns_csrbank1_sel; +wire [13:0] vns_interface2_bank_bus_adr; +wire vns_interface2_bank_bus_we; +wire [31:0] vns_interface2_bank_bus_dat_w; +reg [31:0] vns_interface2_bank_bus_dat_r = 32'd0; +wire vns_csrbank2_dfii_control0_re; +wire [3:0] vns_csrbank2_dfii_control0_r; +wire vns_csrbank2_dfii_control0_we; +wire [3:0] vns_csrbank2_dfii_control0_w; +wire vns_csrbank2_dfii_pi0_command0_re; +wire [5:0] vns_csrbank2_dfii_pi0_command0_r; +wire vns_csrbank2_dfii_pi0_command0_we; +wire [5:0] vns_csrbank2_dfii_pi0_command0_w; +wire vns_csrbank2_dfii_pi0_address0_re; +wire [15:0] vns_csrbank2_dfii_pi0_address0_r; +wire vns_csrbank2_dfii_pi0_address0_we; +wire [15:0] vns_csrbank2_dfii_pi0_address0_w; +wire vns_csrbank2_dfii_pi0_baddress0_re; +wire [2:0] vns_csrbank2_dfii_pi0_baddress0_r; +wire vns_csrbank2_dfii_pi0_baddress0_we; +wire [2:0] vns_csrbank2_dfii_pi0_baddress0_w; +wire vns_csrbank2_dfii_pi0_wrdata0_re; +wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_r; +wire vns_csrbank2_dfii_pi0_wrdata0_we; +wire [31:0] vns_csrbank2_dfii_pi0_wrdata0_w; +wire vns_csrbank2_dfii_pi0_rddata_re; +wire [31:0] vns_csrbank2_dfii_pi0_rddata_r; +wire vns_csrbank2_dfii_pi0_rddata_we; +wire [31:0] vns_csrbank2_dfii_pi0_rddata_w; +wire vns_csrbank2_dfii_pi1_command0_re; +wire [5:0] vns_csrbank2_dfii_pi1_command0_r; +wire vns_csrbank2_dfii_pi1_command0_we; +wire [5:0] vns_csrbank2_dfii_pi1_command0_w; +wire vns_csrbank2_dfii_pi1_address0_re; +wire [15:0] vns_csrbank2_dfii_pi1_address0_r; +wire vns_csrbank2_dfii_pi1_address0_we; +wire [15:0] vns_csrbank2_dfii_pi1_address0_w; +wire vns_csrbank2_dfii_pi1_baddress0_re; +wire [2:0] vns_csrbank2_dfii_pi1_baddress0_r; +wire vns_csrbank2_dfii_pi1_baddress0_we; +wire [2:0] vns_csrbank2_dfii_pi1_baddress0_w; +wire vns_csrbank2_dfii_pi1_wrdata0_re; +wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_r; +wire vns_csrbank2_dfii_pi1_wrdata0_we; +wire [31:0] vns_csrbank2_dfii_pi1_wrdata0_w; +wire vns_csrbank2_dfii_pi1_rddata_re; +wire [31:0] vns_csrbank2_dfii_pi1_rddata_r; +wire vns_csrbank2_dfii_pi1_rddata_we; +wire [31:0] vns_csrbank2_dfii_pi1_rddata_w; +wire vns_csrbank2_dfii_pi2_command0_re; +wire [5:0] vns_csrbank2_dfii_pi2_command0_r; +wire vns_csrbank2_dfii_pi2_command0_we; +wire [5:0] vns_csrbank2_dfii_pi2_command0_w; +wire vns_csrbank2_dfii_pi2_address0_re; +wire [15:0] vns_csrbank2_dfii_pi2_address0_r; +wire vns_csrbank2_dfii_pi2_address0_we; +wire [15:0] vns_csrbank2_dfii_pi2_address0_w; +wire vns_csrbank2_dfii_pi2_baddress0_re; +wire [2:0] vns_csrbank2_dfii_pi2_baddress0_r; +wire vns_csrbank2_dfii_pi2_baddress0_we; +wire [2:0] vns_csrbank2_dfii_pi2_baddress0_w; +wire vns_csrbank2_dfii_pi2_wrdata0_re; +wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_r; +wire vns_csrbank2_dfii_pi2_wrdata0_we; +wire [31:0] vns_csrbank2_dfii_pi2_wrdata0_w; +wire vns_csrbank2_dfii_pi2_rddata_re; +wire [31:0] vns_csrbank2_dfii_pi2_rddata_r; +wire vns_csrbank2_dfii_pi2_rddata_we; +wire [31:0] vns_csrbank2_dfii_pi2_rddata_w; +wire vns_csrbank2_dfii_pi3_command0_re; +wire [5:0] vns_csrbank2_dfii_pi3_command0_r; +wire vns_csrbank2_dfii_pi3_command0_we; +wire [5:0] vns_csrbank2_dfii_pi3_command0_w; +wire vns_csrbank2_dfii_pi3_address0_re; +wire [15:0] vns_csrbank2_dfii_pi3_address0_r; +wire vns_csrbank2_dfii_pi3_address0_we; +wire [15:0] vns_csrbank2_dfii_pi3_address0_w; +wire vns_csrbank2_dfii_pi3_baddress0_re; +wire [2:0] vns_csrbank2_dfii_pi3_baddress0_r; +wire vns_csrbank2_dfii_pi3_baddress0_we; +wire [2:0] vns_csrbank2_dfii_pi3_baddress0_w; +wire vns_csrbank2_dfii_pi3_wrdata0_re; +wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_r; +wire vns_csrbank2_dfii_pi3_wrdata0_we; +wire [31:0] vns_csrbank2_dfii_pi3_wrdata0_w; +wire vns_csrbank2_dfii_pi3_rddata_re; +wire [31:0] vns_csrbank2_dfii_pi3_rddata_r; +wire vns_csrbank2_dfii_pi3_rddata_we; +wire [31:0] vns_csrbank2_dfii_pi3_rddata_w; +wire vns_csrbank2_sel; +wire [13:0] vns_adr; +wire vns_we; +wire [31:0] vns_dat_w; +wire [31:0] vns_dat_r; +reg vns_rhs_array_muxed0 = 1'd0; +reg [15:0] vns_rhs_array_muxed1 = 16'd0; +reg [2:0] vns_rhs_array_muxed2 = 3'd0; +reg vns_rhs_array_muxed3 = 1'd0; +reg vns_rhs_array_muxed4 = 1'd0; +reg vns_rhs_array_muxed5 = 1'd0; +reg vns_t_array_muxed0 = 1'd0; +reg vns_t_array_muxed1 = 1'd0; +reg vns_t_array_muxed2 = 1'd0; +reg vns_rhs_array_muxed6 = 1'd0; +reg [15:0] vns_rhs_array_muxed7 = 16'd0; +reg [2:0] vns_rhs_array_muxed8 = 3'd0; +reg vns_rhs_array_muxed9 = 1'd0; +reg vns_rhs_array_muxed10 = 1'd0; +reg vns_rhs_array_muxed11 = 1'd0; +reg vns_t_array_muxed3 = 1'd0; +reg vns_t_array_muxed4 = 1'd0; +reg vns_t_array_muxed5 = 1'd0; +reg [22:0] vns_rhs_array_muxed12 = 23'd0; +reg vns_rhs_array_muxed13 = 1'd0; +reg vns_rhs_array_muxed14 = 1'd0; +reg [22:0] vns_rhs_array_muxed15 = 23'd0; +reg vns_rhs_array_muxed16 = 1'd0; +reg vns_rhs_array_muxed17 = 1'd0; +reg [22:0] vns_rhs_array_muxed18 = 23'd0; +reg vns_rhs_array_muxed19 = 1'd0; +reg vns_rhs_array_muxed20 = 1'd0; +reg [22:0] vns_rhs_array_muxed21 = 23'd0; +reg vns_rhs_array_muxed22 = 1'd0; +reg vns_rhs_array_muxed23 = 1'd0; +reg [22:0] vns_rhs_array_muxed24 = 23'd0; +reg vns_rhs_array_muxed25 = 1'd0; +reg vns_rhs_array_muxed26 = 1'd0; +reg [22:0] vns_rhs_array_muxed27 = 23'd0; +reg vns_rhs_array_muxed28 = 1'd0; +reg vns_rhs_array_muxed29 = 1'd0; +reg [22:0] vns_rhs_array_muxed30 = 23'd0; +reg vns_rhs_array_muxed31 = 1'd0; +reg vns_rhs_array_muxed32 = 1'd0; +reg [22:0] vns_rhs_array_muxed33 = 23'd0; +reg vns_rhs_array_muxed34 = 1'd0; +reg vns_rhs_array_muxed35 = 1'd0; +reg [2:0] vns_array_muxed0 = 3'd0; +reg [15:0] vns_array_muxed1 = 16'd0; +reg vns_array_muxed2 = 1'd0; +reg vns_array_muxed3 = 1'd0; +reg vns_array_muxed4 = 1'd0; +reg vns_array_muxed5 = 1'd0; +reg vns_array_muxed6 = 1'd0; +reg [2:0] vns_array_muxed7 = 3'd0; +reg [15:0] vns_array_muxed8 = 16'd0; +reg vns_array_muxed9 = 1'd0; +reg vns_array_muxed10 = 1'd0; +reg vns_array_muxed11 = 1'd0; +reg vns_array_muxed12 = 1'd0; +reg vns_array_muxed13 = 1'd0; +reg [2:0] vns_array_muxed14 = 3'd0; +reg [15:0] vns_array_muxed15 = 16'd0; +reg vns_array_muxed16 = 1'd0; +reg vns_array_muxed17 = 1'd0; +reg vns_array_muxed18 = 1'd0; +reg vns_array_muxed19 = 1'd0; +reg vns_array_muxed20 = 1'd0; +reg [2:0] vns_array_muxed21 = 3'd0; +reg [15:0] vns_array_muxed22 = 16'd0; +reg vns_array_muxed23 = 1'd0; +reg vns_array_muxed24 = 1'd0; +reg vns_array_muxed25 = 1'd0; +reg vns_array_muxed26 = 1'd0; +reg vns_array_muxed27 = 1'd0; +wire vns_xilinxasyncresetsynchronizerimpl0; +wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl1; +wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl2; +wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl2_expr; +wire vns_xilinxasyncresetsynchronizerimpl3; +wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl3_expr; + +// synthesis translate_off +reg dummy_s; +initial dummy_s <= 1'd0; +// synthesis translate_on +assign init_done = soc_init_done_storage; +assign init_error = soc_init_error_storage; +assign soc_wb_bus_adr = wb_ctrl_adr; +assign soc_wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = soc_wb_bus_dat_r; +assign soc_wb_bus_sel = wb_ctrl_sel; +assign soc_wb_bus_cyc = wb_ctrl_cyc; +assign soc_wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = soc_wb_bus_ack; +assign soc_wb_bus_we = wb_ctrl_we; +assign soc_wb_bus_cti = wb_ctrl_cti; +assign soc_wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = soc_wb_bus_err; +assign user_clk = sys_clk; +assign user_rst = sys_rst; +assign soc_user_port_cmd_valid = user_port_native_0_cmd_valid; +assign user_port_native_0_cmd_ready = soc_user_port_cmd_ready; +assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign soc_user_port_wdata_valid = user_port_native_0_wdata_valid; +assign user_port_native_0_wdata_ready = soc_user_port_wdata_ready; +assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = soc_user_port_rdata_valid; +assign soc_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data; +assign soc_litedramcore_dat_w = soc_litedramcore_wishbone_dat_w; +assign soc_litedramcore_wishbone_dat_r = soc_litedramcore_dat_r; + +// synthesis translate_off +reg dummy_d; +// synthesis translate_on +always @(*) begin + vns_next_state <= 1'd0; + vns_next_state <= vns_state; + case (vns_state) + 1'd1: begin + vns_next_state <= 1'd0; + end + default: begin + if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin + vns_next_state <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_1; +// synthesis translate_on +always @(*) begin + soc_litedramcore_adr <= 14'd0; + case (vns_state) + 1'd1: begin + end + default: begin + if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin + soc_litedramcore_adr <= soc_litedramcore_wishbone_adr; + end + end + endcase +// synthesis translate_off + dummy_d_1 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_2; +// synthesis translate_on +always @(*) begin + soc_litedramcore_wishbone_ack <= 1'd0; + case (vns_state) + 1'd1: begin + soc_litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_2 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_3; +// synthesis translate_on +always @(*) begin + soc_litedramcore_we <= 1'd0; + case (vns_state) + 1'd1: begin + end + default: begin + if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin + soc_litedramcore_we <= (soc_litedramcore_wishbone_we & (soc_litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +// synthesis translate_off + dummy_d_3 = dummy_s; +// synthesis translate_on +end +assign soc_reset = rst; +assign pll_locked = soc_locked; +assign soc_clkin = clk; +assign iodelay_clk = soc_clkout_buf0; +assign sys_clk = soc_clkout_buf1; +assign sys4x_clk = soc_clkout_buf2; +assign sys4x_dqs_clk = soc_clkout_buf3; +assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0; + +// synthesis translate_off +reg dummy_d_4; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dfi_p0_rddata <= 32'd0; + soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0]; + soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1]; + soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0]; + soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1]; + soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0]; + soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1]; + soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0]; + soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1]; + soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0]; + soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1]; + soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0]; + soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1]; + soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0]; + soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1]; + soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0]; + soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1]; + soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0]; + soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1]; + soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0]; + soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1]; + soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0]; + soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1]; + soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0]; + soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1]; + soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0]; + soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1]; + soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0]; + soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1]; + soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0]; + soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1]; + soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0]; + soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1]; +// synthesis translate_off + dummy_d_4 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_5; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dfi_p1_rddata <= 32'd0; + soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2]; + soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3]; + soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2]; + soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3]; + soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2]; + soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3]; + soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2]; + soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3]; + soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2]; + soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3]; + soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2]; + soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3]; + soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2]; + soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3]; + soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2]; + soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3]; + soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2]; + soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3]; + soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2]; + soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3]; + soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2]; + soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3]; + soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2]; + soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3]; + soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2]; + soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3]; + soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2]; + soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3]; + soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2]; + soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3]; + soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2]; + soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3]; +// synthesis translate_off + dummy_d_5 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_6; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dfi_p2_rddata <= 32'd0; + soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4]; + soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5]; + soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4]; + soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5]; + soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4]; + soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5]; + soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4]; + soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5]; + soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4]; + soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5]; + soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4]; + soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5]; + soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4]; + soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5]; + soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4]; + soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5]; + soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4]; + soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5]; + soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4]; + soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5]; + soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4]; + soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5]; + soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4]; + soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5]; + soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4]; + soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5]; + soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4]; + soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5]; + soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4]; + soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5]; + soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4]; + soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5]; +// synthesis translate_off + dummy_d_6 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_7; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dfi_p3_rddata <= 32'd0; + soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6]; + soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7]; + soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6]; + soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7]; + soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6]; + soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7]; + soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6]; + soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7]; + soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6]; + soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7]; + soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6]; + soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7]; + soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6]; + soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7]; + soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6]; + soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7]; + soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6]; + soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7]; + soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6]; + soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7]; + soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6]; + soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7]; + soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6]; + soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7]; + soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6]; + soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7]; + soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6]; + soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7]; + soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6]; + soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7]; + soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6]; + soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7]; +// synthesis translate_off + dummy_d_7 = dummy_s; +// synthesis translate_on +end +assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1; +assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2; +assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3; +assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4; +assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5; +assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6; +assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7; +assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8; +assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9; +assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10; +assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11; +assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12; +assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13; +assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14; +assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15; +assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en}; +assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en}; +assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2]; + +// synthesis translate_off +reg dummy_d_8; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dqs_oe <= 1'd0; + if (soc_a7ddrphy_wlevel_en_storage) begin + soc_a7ddrphy_dqs_oe <= 1'd1; + end else begin + soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe; + end +// synthesis translate_off + dummy_d_8 = dummy_s; +// synthesis translate_on +end +assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2])); +assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2])); + +// synthesis translate_off +reg dummy_d_9; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dqspattern_o0 <= 8'd0; + soc_a7ddrphy_dqspattern_o0 <= 7'd85; + if (soc_a7ddrphy_dqspattern0) begin + soc_a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (soc_a7ddrphy_dqspattern1) begin + soc_a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (soc_a7ddrphy_wlevel_en_storage) begin + soc_a7ddrphy_dqspattern_o0 <= 1'd0; + if (soc_a7ddrphy_wlevel_strobe_re) begin + soc_a7ddrphy_dqspattern_o0 <= 1'd1; + end + end +// synthesis translate_off + dummy_d_9 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_10; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip0_o <= 8'd0; + case (soc_a7ddrphy_bitslip0_value) + 1'd0: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_10 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_11; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip1_o <= 8'd0; + case (soc_a7ddrphy_bitslip1_value) + 1'd0: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_11 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_12; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip2_o <= 8'd0; + case (soc_a7ddrphy_bitslip2_value) + 1'd0: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_12 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_13; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip3_o <= 8'd0; + case (soc_a7ddrphy_bitslip3_value) + 1'd0: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_13 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_14; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip4_o <= 8'd0; + case (soc_a7ddrphy_bitslip4_value) + 1'd0: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_14 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_15; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip5_o <= 8'd0; + case (soc_a7ddrphy_bitslip5_value) + 1'd0: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_15 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_16; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip6_o <= 8'd0; + case (soc_a7ddrphy_bitslip6_value) + 1'd0: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_16 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_17; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip7_o <= 8'd0; + case (soc_a7ddrphy_bitslip7_value) + 1'd0: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_17 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_18; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip8_o <= 8'd0; + case (soc_a7ddrphy_bitslip8_value) + 1'd0: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_18 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_19; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip9_o <= 8'd0; + case (soc_a7ddrphy_bitslip9_value) + 1'd0: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_19 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_20; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip10_o <= 8'd0; + case (soc_a7ddrphy_bitslip10_value) + 1'd0: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_20 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_21; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip11_o <= 8'd0; + case (soc_a7ddrphy_bitslip11_value) + 1'd0: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_21 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_22; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip12_o <= 8'd0; + case (soc_a7ddrphy_bitslip12_value) + 1'd0: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_22 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_23; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip13_o <= 8'd0; + case (soc_a7ddrphy_bitslip13_value) + 1'd0: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_23 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_24; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip14_o <= 8'd0; + case (soc_a7ddrphy_bitslip14_value) + 1'd0: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_24 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_25; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip15_o <= 8'd0; + case (soc_a7ddrphy_bitslip15_value) + 1'd0: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7]; + end + 4'd8: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[15:8]; + end + 4'd9: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[16:9]; + end + 4'd10: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[17:10]; + end + 4'd11: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[18:11]; + end + 4'd12: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[19:12]; + end + 4'd13: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[20:13]; + end + 4'd14: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[21:14]; + end + 4'd15: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[22:15]; + end + endcase +// synthesis translate_off + dummy_d_25 = dummy_s; +// synthesis translate_on +end +assign soc_a7ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address; +assign soc_a7ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank; +assign soc_a7ddrphy_dfi_p0_cas_n = soc_litedramcore_master_p0_cas_n; +assign soc_a7ddrphy_dfi_p0_cs_n = soc_litedramcore_master_p0_cs_n; +assign soc_a7ddrphy_dfi_p0_ras_n = soc_litedramcore_master_p0_ras_n; +assign soc_a7ddrphy_dfi_p0_we_n = soc_litedramcore_master_p0_we_n; +assign soc_a7ddrphy_dfi_p0_cke = soc_litedramcore_master_p0_cke; +assign soc_a7ddrphy_dfi_p0_odt = soc_litedramcore_master_p0_odt; +assign soc_a7ddrphy_dfi_p0_reset_n = soc_litedramcore_master_p0_reset_n; +assign soc_a7ddrphy_dfi_p0_act_n = soc_litedramcore_master_p0_act_n; +assign soc_a7ddrphy_dfi_p0_wrdata = soc_litedramcore_master_p0_wrdata; +assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_litedramcore_master_p0_wrdata_en; +assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_litedramcore_master_p0_wrdata_mask; +assign soc_a7ddrphy_dfi_p0_rddata_en = soc_litedramcore_master_p0_rddata_en; +assign soc_litedramcore_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata; +assign soc_litedramcore_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid; +assign soc_a7ddrphy_dfi_p1_address = soc_litedramcore_master_p1_address; +assign soc_a7ddrphy_dfi_p1_bank = soc_litedramcore_master_p1_bank; +assign soc_a7ddrphy_dfi_p1_cas_n = soc_litedramcore_master_p1_cas_n; +assign soc_a7ddrphy_dfi_p1_cs_n = soc_litedramcore_master_p1_cs_n; +assign soc_a7ddrphy_dfi_p1_ras_n = soc_litedramcore_master_p1_ras_n; +assign soc_a7ddrphy_dfi_p1_we_n = soc_litedramcore_master_p1_we_n; +assign soc_a7ddrphy_dfi_p1_cke = soc_litedramcore_master_p1_cke; +assign soc_a7ddrphy_dfi_p1_odt = soc_litedramcore_master_p1_odt; +assign soc_a7ddrphy_dfi_p1_reset_n = soc_litedramcore_master_p1_reset_n; +assign soc_a7ddrphy_dfi_p1_act_n = soc_litedramcore_master_p1_act_n; +assign soc_a7ddrphy_dfi_p1_wrdata = soc_litedramcore_master_p1_wrdata; +assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_litedramcore_master_p1_wrdata_en; +assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_litedramcore_master_p1_wrdata_mask; +assign soc_a7ddrphy_dfi_p1_rddata_en = soc_litedramcore_master_p1_rddata_en; +assign soc_litedramcore_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata; +assign soc_litedramcore_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid; +assign soc_a7ddrphy_dfi_p2_address = soc_litedramcore_master_p2_address; +assign soc_a7ddrphy_dfi_p2_bank = soc_litedramcore_master_p2_bank; +assign soc_a7ddrphy_dfi_p2_cas_n = soc_litedramcore_master_p2_cas_n; +assign soc_a7ddrphy_dfi_p2_cs_n = soc_litedramcore_master_p2_cs_n; +assign soc_a7ddrphy_dfi_p2_ras_n = soc_litedramcore_master_p2_ras_n; +assign soc_a7ddrphy_dfi_p2_we_n = soc_litedramcore_master_p2_we_n; +assign soc_a7ddrphy_dfi_p2_cke = soc_litedramcore_master_p2_cke; +assign soc_a7ddrphy_dfi_p2_odt = soc_litedramcore_master_p2_odt; +assign soc_a7ddrphy_dfi_p2_reset_n = soc_litedramcore_master_p2_reset_n; +assign soc_a7ddrphy_dfi_p2_act_n = soc_litedramcore_master_p2_act_n; +assign soc_a7ddrphy_dfi_p2_wrdata = soc_litedramcore_master_p2_wrdata; +assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_litedramcore_master_p2_wrdata_en; +assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_litedramcore_master_p2_wrdata_mask; +assign soc_a7ddrphy_dfi_p2_rddata_en = soc_litedramcore_master_p2_rddata_en; +assign soc_litedramcore_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata; +assign soc_litedramcore_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid; +assign soc_a7ddrphy_dfi_p3_address = soc_litedramcore_master_p3_address; +assign soc_a7ddrphy_dfi_p3_bank = soc_litedramcore_master_p3_bank; +assign soc_a7ddrphy_dfi_p3_cas_n = soc_litedramcore_master_p3_cas_n; +assign soc_a7ddrphy_dfi_p3_cs_n = soc_litedramcore_master_p3_cs_n; +assign soc_a7ddrphy_dfi_p3_ras_n = soc_litedramcore_master_p3_ras_n; +assign soc_a7ddrphy_dfi_p3_we_n = soc_litedramcore_master_p3_we_n; +assign soc_a7ddrphy_dfi_p3_cke = soc_litedramcore_master_p3_cke; +assign soc_a7ddrphy_dfi_p3_odt = soc_litedramcore_master_p3_odt; +assign soc_a7ddrphy_dfi_p3_reset_n = soc_litedramcore_master_p3_reset_n; +assign soc_a7ddrphy_dfi_p3_act_n = soc_litedramcore_master_p3_act_n; +assign soc_a7ddrphy_dfi_p3_wrdata = soc_litedramcore_master_p3_wrdata; +assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_litedramcore_master_p3_wrdata_en; +assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_litedramcore_master_p3_wrdata_mask; +assign soc_a7ddrphy_dfi_p3_rddata_en = soc_litedramcore_master_p3_rddata_en; +assign soc_litedramcore_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata; +assign soc_litedramcore_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid; +assign soc_litedramcore_slave_p0_address = soc_litedramcore_dfi_p0_address; +assign soc_litedramcore_slave_p0_bank = soc_litedramcore_dfi_p0_bank; +assign soc_litedramcore_slave_p0_cas_n = soc_litedramcore_dfi_p0_cas_n; +assign soc_litedramcore_slave_p0_cs_n = soc_litedramcore_dfi_p0_cs_n; +assign soc_litedramcore_slave_p0_ras_n = soc_litedramcore_dfi_p0_ras_n; +assign soc_litedramcore_slave_p0_we_n = soc_litedramcore_dfi_p0_we_n; +assign soc_litedramcore_slave_p0_cke = soc_litedramcore_dfi_p0_cke; +assign soc_litedramcore_slave_p0_odt = soc_litedramcore_dfi_p0_odt; +assign soc_litedramcore_slave_p0_reset_n = soc_litedramcore_dfi_p0_reset_n; +assign soc_litedramcore_slave_p0_act_n = soc_litedramcore_dfi_p0_act_n; +assign soc_litedramcore_slave_p0_wrdata = soc_litedramcore_dfi_p0_wrdata; +assign soc_litedramcore_slave_p0_wrdata_en = soc_litedramcore_dfi_p0_wrdata_en; +assign soc_litedramcore_slave_p0_wrdata_mask = soc_litedramcore_dfi_p0_wrdata_mask; +assign soc_litedramcore_slave_p0_rddata_en = soc_litedramcore_dfi_p0_rddata_en; +assign soc_litedramcore_dfi_p0_rddata = soc_litedramcore_slave_p0_rddata; +assign soc_litedramcore_dfi_p0_rddata_valid = soc_litedramcore_slave_p0_rddata_valid; +assign soc_litedramcore_slave_p1_address = soc_litedramcore_dfi_p1_address; +assign soc_litedramcore_slave_p1_bank = soc_litedramcore_dfi_p1_bank; +assign soc_litedramcore_slave_p1_cas_n = soc_litedramcore_dfi_p1_cas_n; +assign soc_litedramcore_slave_p1_cs_n = soc_litedramcore_dfi_p1_cs_n; +assign soc_litedramcore_slave_p1_ras_n = soc_litedramcore_dfi_p1_ras_n; +assign soc_litedramcore_slave_p1_we_n = soc_litedramcore_dfi_p1_we_n; +assign soc_litedramcore_slave_p1_cke = soc_litedramcore_dfi_p1_cke; +assign soc_litedramcore_slave_p1_odt = soc_litedramcore_dfi_p1_odt; +assign soc_litedramcore_slave_p1_reset_n = soc_litedramcore_dfi_p1_reset_n; +assign soc_litedramcore_slave_p1_act_n = soc_litedramcore_dfi_p1_act_n; +assign soc_litedramcore_slave_p1_wrdata = soc_litedramcore_dfi_p1_wrdata; +assign soc_litedramcore_slave_p1_wrdata_en = soc_litedramcore_dfi_p1_wrdata_en; +assign soc_litedramcore_slave_p1_wrdata_mask = soc_litedramcore_dfi_p1_wrdata_mask; +assign soc_litedramcore_slave_p1_rddata_en = soc_litedramcore_dfi_p1_rddata_en; +assign soc_litedramcore_dfi_p1_rddata = soc_litedramcore_slave_p1_rddata; +assign soc_litedramcore_dfi_p1_rddata_valid = soc_litedramcore_slave_p1_rddata_valid; +assign soc_litedramcore_slave_p2_address = soc_litedramcore_dfi_p2_address; +assign soc_litedramcore_slave_p2_bank = soc_litedramcore_dfi_p2_bank; +assign soc_litedramcore_slave_p2_cas_n = soc_litedramcore_dfi_p2_cas_n; +assign soc_litedramcore_slave_p2_cs_n = soc_litedramcore_dfi_p2_cs_n; +assign soc_litedramcore_slave_p2_ras_n = soc_litedramcore_dfi_p2_ras_n; +assign soc_litedramcore_slave_p2_we_n = soc_litedramcore_dfi_p2_we_n; +assign soc_litedramcore_slave_p2_cke = soc_litedramcore_dfi_p2_cke; +assign soc_litedramcore_slave_p2_odt = soc_litedramcore_dfi_p2_odt; +assign soc_litedramcore_slave_p2_reset_n = soc_litedramcore_dfi_p2_reset_n; +assign soc_litedramcore_slave_p2_act_n = soc_litedramcore_dfi_p2_act_n; +assign soc_litedramcore_slave_p2_wrdata = soc_litedramcore_dfi_p2_wrdata; +assign soc_litedramcore_slave_p2_wrdata_en = soc_litedramcore_dfi_p2_wrdata_en; +assign soc_litedramcore_slave_p2_wrdata_mask = soc_litedramcore_dfi_p2_wrdata_mask; +assign soc_litedramcore_slave_p2_rddata_en = soc_litedramcore_dfi_p2_rddata_en; +assign soc_litedramcore_dfi_p2_rddata = soc_litedramcore_slave_p2_rddata; +assign soc_litedramcore_dfi_p2_rddata_valid = soc_litedramcore_slave_p2_rddata_valid; +assign soc_litedramcore_slave_p3_address = soc_litedramcore_dfi_p3_address; +assign soc_litedramcore_slave_p3_bank = soc_litedramcore_dfi_p3_bank; +assign soc_litedramcore_slave_p3_cas_n = soc_litedramcore_dfi_p3_cas_n; +assign soc_litedramcore_slave_p3_cs_n = soc_litedramcore_dfi_p3_cs_n; +assign soc_litedramcore_slave_p3_ras_n = soc_litedramcore_dfi_p3_ras_n; +assign soc_litedramcore_slave_p3_we_n = soc_litedramcore_dfi_p3_we_n; +assign soc_litedramcore_slave_p3_cke = soc_litedramcore_dfi_p3_cke; +assign soc_litedramcore_slave_p3_odt = soc_litedramcore_dfi_p3_odt; +assign soc_litedramcore_slave_p3_reset_n = soc_litedramcore_dfi_p3_reset_n; +assign soc_litedramcore_slave_p3_act_n = soc_litedramcore_dfi_p3_act_n; +assign soc_litedramcore_slave_p3_wrdata = soc_litedramcore_dfi_p3_wrdata; +assign soc_litedramcore_slave_p3_wrdata_en = soc_litedramcore_dfi_p3_wrdata_en; +assign soc_litedramcore_slave_p3_wrdata_mask = soc_litedramcore_dfi_p3_wrdata_mask; +assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en; +assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata; +assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid; + +// synthesis translate_off +reg dummy_d_26; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_cke <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke; + end else begin + soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke; + end +// synthesis translate_off + dummy_d_26 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_27; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_odt <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt; + end else begin + soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt; + end +// synthesis translate_off + dummy_d_27 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_28; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_reset_n <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n; + end else begin + soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n; + end +// synthesis translate_off + dummy_d_28 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_29; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_act_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n; + end else begin + soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n; + end +// synthesis translate_off + dummy_d_29 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_30; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_wrdata <= 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata; + end else begin + soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata; + end +// synthesis translate_off + dummy_d_30 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_31; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p2_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata; + end +// synthesis translate_off + dummy_d_31 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_32; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_wrdata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en; + end else begin + soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en; + end +// synthesis translate_off + dummy_d_32 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_33; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p2_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + end +// synthesis translate_off + dummy_d_33 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_34; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_wrdata_mask <= 4'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask; + end else begin + soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask; + end +// synthesis translate_off + dummy_d_34 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_35; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_rddata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en; + end else begin + soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en; + end +// synthesis translate_off + dummy_d_35 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_36; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_address <= 16'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address; + end else begin + soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address; + end +// synthesis translate_off + dummy_d_36 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_37; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_bank <= 3'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank; + end else begin + soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank; + end +// synthesis translate_off + dummy_d_37 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_38; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_cas_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n; + end else begin + soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n; + end +// synthesis translate_off + dummy_d_38 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_39; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_cs_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n; + end else begin + soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n; + end +// synthesis translate_off + dummy_d_39 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_40; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_ras_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n; + end else begin + soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n; + end +// synthesis translate_off + dummy_d_40 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_41; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p2_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata; + end else begin + end +// synthesis translate_off + dummy_d_41 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_42; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_we_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n; + end else begin + soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n; + end +// synthesis translate_off + dummy_d_42 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_43; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_43 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_44; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_cke <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke; + end else begin + soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke; + end +// synthesis translate_off + dummy_d_44 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_45; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_odt <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt; + end else begin + soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt; + end +// synthesis translate_off + dummy_d_45 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_46; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_reset_n <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n; + end else begin + soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n; + end +// synthesis translate_off + dummy_d_46 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_47; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_act_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n; + end else begin + soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n; + end +// synthesis translate_off + dummy_d_47 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_48; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_wrdata <= 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata; + end else begin + soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata; + end +// synthesis translate_off + dummy_d_48 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_49; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p3_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata; + end +// synthesis translate_off + dummy_d_49 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_50; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_wrdata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en; + end else begin + soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en; + end +// synthesis translate_off + dummy_d_50 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_51; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p3_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + end +// synthesis translate_off + dummy_d_51 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_52; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_wrdata_mask <= 4'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask; + end else begin + soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask; + end +// synthesis translate_off + dummy_d_52 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_53; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p2_rddata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en; + end else begin + soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en; + end +// synthesis translate_off + dummy_d_53 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_54; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_address <= 16'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address; + end else begin + soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address; + end +// synthesis translate_off + dummy_d_54 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_55; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_bank <= 3'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank; + end else begin + soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank; + end +// synthesis translate_off + dummy_d_55 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_56; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_cas_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n; + end else begin + soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n; + end +// synthesis translate_off + dummy_d_56 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_57; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_cs_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n; + end else begin + soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n; + end +// synthesis translate_off + dummy_d_57 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_58; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_ras_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n; + end else begin + soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n; + end +// synthesis translate_off + dummy_d_58 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_59; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p3_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata; + end else begin + end +// synthesis translate_off + dummy_d_59 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_60; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_we_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n; + end else begin + soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n; + end +// synthesis translate_off + dummy_d_60 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_61; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p3_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_61 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_62; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_cke <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke; + end else begin + soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke; + end +// synthesis translate_off + dummy_d_62 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_63; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_odt <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt; + end else begin + soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt; + end +// synthesis translate_off + dummy_d_63 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_64; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_reset_n <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n; + end else begin + soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n; + end +// synthesis translate_off + dummy_d_64 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_65; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_act_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n; + end else begin + soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n; + end +// synthesis translate_off + dummy_d_65 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_66; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_wrdata <= 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata; + end else begin + soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata; + end +// synthesis translate_off + dummy_d_66 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_67; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p0_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata; + end +// synthesis translate_off + dummy_d_67 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_68; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_wrdata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en; + end else begin + soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en; + end +// synthesis translate_off + dummy_d_68 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_69; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p0_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; + end +// synthesis translate_off + dummy_d_69 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_70; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_wrdata_mask <= 4'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask; + end else begin + soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask; + end +// synthesis translate_off + dummy_d_70 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_71; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p3_rddata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en; + end else begin + soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en; + end +// synthesis translate_off + dummy_d_71 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_72; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_address <= 16'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address; + end else begin + soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address; + end +// synthesis translate_off + dummy_d_72 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_73; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_bank <= 3'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank; + end else begin + soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank; + end +// synthesis translate_off + dummy_d_73 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_74; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_cas_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n; + end else begin + soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n; + end +// synthesis translate_off + dummy_d_74 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_75; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p1_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata; + end else begin + end +// synthesis translate_off + dummy_d_75 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_76; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_cs_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n; + end else begin + soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n; + end +// synthesis translate_off + dummy_d_76 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_77; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p0_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata; + end else begin + end +// synthesis translate_off + dummy_d_77 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_78; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_ras_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n; + end else begin + soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n; + end +// synthesis translate_off + dummy_d_78 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_79; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p0_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_79 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_80; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_we_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n; + end else begin + soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n; + end +// synthesis translate_off + dummy_d_80 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_81; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_cke <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke; + end else begin + soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke; + end +// synthesis translate_off + dummy_d_81 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_82; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_odt <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt; + end else begin + soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt; + end +// synthesis translate_off + dummy_d_82 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_83; +// synthesis translate_on +always @(*) begin + soc_litedramcore_slave_p1_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_83 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_84; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_reset_n <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n; + end else begin + soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n; + end +// synthesis translate_off + dummy_d_84 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_85; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_act_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n; + end else begin + soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n; + end +// synthesis translate_off + dummy_d_85 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_86; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_wrdata <= 32'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata; + end else begin + soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata; + end +// synthesis translate_off + dummy_d_86 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_87; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p1_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata; + end +// synthesis translate_off + dummy_d_87 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_88; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_wrdata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en; + end else begin + soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en; + end +// synthesis translate_off + dummy_d_88 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_89; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p1_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + end +// synthesis translate_off + dummy_d_89 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_90; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_wrdata_mask <= 4'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask; + end else begin + soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask; + end +// synthesis translate_off + dummy_d_90 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_91; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p0_rddata_en <= 1'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en; + end else begin + soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en; + end +// synthesis translate_off + dummy_d_91 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_92; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_address <= 16'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address; + end else begin + soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address; + end +// synthesis translate_off + dummy_d_92 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_93; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_bank <= 3'd0; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank; + end else begin + soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank; + end +// synthesis translate_off + dummy_d_93 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_94; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_cas_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n; + end else begin + soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n; + end +// synthesis translate_off + dummy_d_94 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_95; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_cs_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n; + end else begin + soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n; + end +// synthesis translate_off + dummy_d_95 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_96; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_ras_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n; + end else begin + soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n; + end +// synthesis translate_off + dummy_d_96 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_97; +// synthesis translate_on +always @(*) begin + soc_litedramcore_master_p1_we_n <= 1'd1; + if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n; + end else begin + soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n; + end +// synthesis translate_off + dummy_d_97 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke; +assign soc_litedramcore_inti_p1_cke = soc_litedramcore_cke; +assign soc_litedramcore_inti_p2_cke = soc_litedramcore_cke; +assign soc_litedramcore_inti_p3_cke = soc_litedramcore_cke; +assign soc_litedramcore_inti_p0_odt = soc_litedramcore_odt; +assign soc_litedramcore_inti_p1_odt = soc_litedramcore_odt; +assign soc_litedramcore_inti_p2_odt = soc_litedramcore_odt; +assign soc_litedramcore_inti_p3_odt = soc_litedramcore_odt; +assign soc_litedramcore_inti_p0_reset_n = soc_litedramcore_reset_n; +assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n; +assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n; +assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n; + +// synthesis translate_off +reg dummy_d_98; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p0_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]); + end else begin + soc_litedramcore_inti_p0_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_98 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_99; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p0_cs_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}}; + end else begin + soc_litedramcore_inti_p0_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_99 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_100; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p0_ras_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]); + end else begin + soc_litedramcore_inti_p0_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_100 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_101; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p0_we_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]); + end else begin + soc_litedramcore_inti_p0_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_101 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage; +assign soc_litedramcore_inti_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage; +assign soc_litedramcore_inti_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[4]); +assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[5]); +assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage; +assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_102; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p1_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]); + end else begin + soc_litedramcore_inti_p1_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_102 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_103; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p1_cs_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}}; + end else begin + soc_litedramcore_inti_p1_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_103 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_104; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p1_ras_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]); + end else begin + soc_litedramcore_inti_p1_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_104 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_105; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p1_we_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]); + end else begin + soc_litedramcore_inti_p1_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_105 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage; +assign soc_litedramcore_inti_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage; +assign soc_litedramcore_inti_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[4]); +assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[5]); +assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage; +assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_106; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p2_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]); + end else begin + soc_litedramcore_inti_p2_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_106 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_107; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p2_cs_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}}; + end else begin + soc_litedramcore_inti_p2_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_107 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_108; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p2_ras_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]); + end else begin + soc_litedramcore_inti_p2_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_108 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_109; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p2_we_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]); + end else begin + soc_litedramcore_inti_p2_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_109 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage; +assign soc_litedramcore_inti_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage; +assign soc_litedramcore_inti_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[4]); +assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[5]); +assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage; +assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_110; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p3_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]); + end else begin + soc_litedramcore_inti_p3_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_110 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_111; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p3_cs_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}}; + end else begin + soc_litedramcore_inti_p3_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_111 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_112; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p3_ras_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]); + end else begin + soc_litedramcore_inti_p3_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_112 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_113; +// synthesis translate_on +always @(*) begin + soc_litedramcore_inti_p3_we_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]); + end else begin + soc_litedramcore_inti_p3_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_113 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage; +assign soc_litedramcore_inti_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage; +assign soc_litedramcore_inti_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[4]); +assign soc_litedramcore_inti_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[5]); +assign soc_litedramcore_inti_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage; +assign soc_litedramcore_inti_p3_wrdata_mask = 1'd0; +assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid; +assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready; +assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we; +assign soc_litedramcore_bankmachine0_req_addr = soc_litedramcore_interface_bank0_addr; +assign soc_litedramcore_interface_bank0_lock = soc_litedramcore_bankmachine0_req_lock; +assign soc_litedramcore_interface_bank0_wdata_ready = soc_litedramcore_bankmachine0_req_wdata_ready; +assign soc_litedramcore_interface_bank0_rdata_valid = soc_litedramcore_bankmachine0_req_rdata_valid; +assign soc_litedramcore_bankmachine1_req_valid = soc_litedramcore_interface_bank1_valid; +assign soc_litedramcore_interface_bank1_ready = soc_litedramcore_bankmachine1_req_ready; +assign soc_litedramcore_bankmachine1_req_we = soc_litedramcore_interface_bank1_we; +assign soc_litedramcore_bankmachine1_req_addr = soc_litedramcore_interface_bank1_addr; +assign soc_litedramcore_interface_bank1_lock = soc_litedramcore_bankmachine1_req_lock; +assign soc_litedramcore_interface_bank1_wdata_ready = soc_litedramcore_bankmachine1_req_wdata_ready; +assign soc_litedramcore_interface_bank1_rdata_valid = soc_litedramcore_bankmachine1_req_rdata_valid; +assign soc_litedramcore_bankmachine2_req_valid = soc_litedramcore_interface_bank2_valid; +assign soc_litedramcore_interface_bank2_ready = soc_litedramcore_bankmachine2_req_ready; +assign soc_litedramcore_bankmachine2_req_we = soc_litedramcore_interface_bank2_we; +assign soc_litedramcore_bankmachine2_req_addr = soc_litedramcore_interface_bank2_addr; +assign soc_litedramcore_interface_bank2_lock = soc_litedramcore_bankmachine2_req_lock; +assign soc_litedramcore_interface_bank2_wdata_ready = soc_litedramcore_bankmachine2_req_wdata_ready; +assign soc_litedramcore_interface_bank2_rdata_valid = soc_litedramcore_bankmachine2_req_rdata_valid; +assign soc_litedramcore_bankmachine3_req_valid = soc_litedramcore_interface_bank3_valid; +assign soc_litedramcore_interface_bank3_ready = soc_litedramcore_bankmachine3_req_ready; +assign soc_litedramcore_bankmachine3_req_we = soc_litedramcore_interface_bank3_we; +assign soc_litedramcore_bankmachine3_req_addr = soc_litedramcore_interface_bank3_addr; +assign soc_litedramcore_interface_bank3_lock = soc_litedramcore_bankmachine3_req_lock; +assign soc_litedramcore_interface_bank3_wdata_ready = soc_litedramcore_bankmachine3_req_wdata_ready; +assign soc_litedramcore_interface_bank3_rdata_valid = soc_litedramcore_bankmachine3_req_rdata_valid; +assign soc_litedramcore_bankmachine4_req_valid = soc_litedramcore_interface_bank4_valid; +assign soc_litedramcore_interface_bank4_ready = soc_litedramcore_bankmachine4_req_ready; +assign soc_litedramcore_bankmachine4_req_we = soc_litedramcore_interface_bank4_we; +assign soc_litedramcore_bankmachine4_req_addr = soc_litedramcore_interface_bank4_addr; +assign soc_litedramcore_interface_bank4_lock = soc_litedramcore_bankmachine4_req_lock; +assign soc_litedramcore_interface_bank4_wdata_ready = soc_litedramcore_bankmachine4_req_wdata_ready; +assign soc_litedramcore_interface_bank4_rdata_valid = soc_litedramcore_bankmachine4_req_rdata_valid; +assign soc_litedramcore_bankmachine5_req_valid = soc_litedramcore_interface_bank5_valid; +assign soc_litedramcore_interface_bank5_ready = soc_litedramcore_bankmachine5_req_ready; +assign soc_litedramcore_bankmachine5_req_we = soc_litedramcore_interface_bank5_we; +assign soc_litedramcore_bankmachine5_req_addr = soc_litedramcore_interface_bank5_addr; +assign soc_litedramcore_interface_bank5_lock = soc_litedramcore_bankmachine5_req_lock; +assign soc_litedramcore_interface_bank5_wdata_ready = soc_litedramcore_bankmachine5_req_wdata_ready; +assign soc_litedramcore_interface_bank5_rdata_valid = soc_litedramcore_bankmachine5_req_rdata_valid; +assign soc_litedramcore_bankmachine6_req_valid = soc_litedramcore_interface_bank6_valid; +assign soc_litedramcore_interface_bank6_ready = soc_litedramcore_bankmachine6_req_ready; +assign soc_litedramcore_bankmachine6_req_we = soc_litedramcore_interface_bank6_we; +assign soc_litedramcore_bankmachine6_req_addr = soc_litedramcore_interface_bank6_addr; +assign soc_litedramcore_interface_bank6_lock = soc_litedramcore_bankmachine6_req_lock; +assign soc_litedramcore_interface_bank6_wdata_ready = soc_litedramcore_bankmachine6_req_wdata_ready; +assign soc_litedramcore_interface_bank6_rdata_valid = soc_litedramcore_bankmachine6_req_rdata_valid; +assign soc_litedramcore_bankmachine7_req_valid = soc_litedramcore_interface_bank7_valid; +assign soc_litedramcore_interface_bank7_ready = soc_litedramcore_bankmachine7_req_ready; +assign soc_litedramcore_bankmachine7_req_we = soc_litedramcore_interface_bank7_we; +assign soc_litedramcore_bankmachine7_req_addr = soc_litedramcore_interface_bank7_addr; +assign soc_litedramcore_interface_bank7_lock = soc_litedramcore_bankmachine7_req_lock; +assign soc_litedramcore_interface_bank7_wdata_ready = soc_litedramcore_bankmachine7_req_wdata_ready; +assign soc_litedramcore_interface_bank7_rdata_valid = soc_litedramcore_bankmachine7_req_rdata_valid; +assign soc_litedramcore_timer_wait = (~soc_litedramcore_timer_done0); +assign soc_litedramcore_postponer_req_i = soc_litedramcore_timer_done0; +assign soc_litedramcore_wants_refresh = soc_litedramcore_postponer_req_o; +assign soc_litedramcore_wants_zqcs = soc_litedramcore_zqcs_timer_done0; +assign soc_litedramcore_zqcs_timer_wait = (~soc_litedramcore_zqcs_executer_done); +assign soc_litedramcore_timer_done1 = (soc_litedramcore_timer_count1 == 1'd0); +assign soc_litedramcore_timer_done0 = soc_litedramcore_timer_done1; +assign soc_litedramcore_timer_count0 = soc_litedramcore_timer_count1; +assign soc_litedramcore_sequencer_start1 = (soc_litedramcore_sequencer_start0 | (soc_litedramcore_sequencer_count != 1'd0)); +assign soc_litedramcore_sequencer_done0 = (soc_litedramcore_sequencer_done1 & (soc_litedramcore_sequencer_count == 1'd0)); +assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 == 1'd0); +assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1; +assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1; + +// synthesis translate_off +reg dummy_d_114; +// synthesis translate_on +always @(*) begin + vns_refresher_next_state <= 2'd0; + vns_refresher_next_state <= vns_refresher_state; + case (vns_refresher_state) + 1'd1: begin + if (soc_litedramcore_cmd_ready) begin + vns_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + vns_refresher_next_state <= 2'd3; + end else begin + vns_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (soc_litedramcore_zqcs_executer_done) begin + vns_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (soc_litedramcore_wants_refresh) begin + vns_refresher_next_state <= 1'd1; + end + end + end + endcase +// synthesis translate_off + dummy_d_114 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_115; +// synthesis translate_on +always @(*) begin + soc_litedramcore_cmd_valid <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + soc_litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + soc_litedramcore_cmd_valid <= 1'd1; + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + end else begin + soc_litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + soc_litedramcore_cmd_valid <= 1'd1; + if (soc_litedramcore_zqcs_executer_done) begin + soc_litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_115 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_116; +// synthesis translate_on +always @(*) begin + soc_litedramcore_zqcs_executer_start <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + soc_litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_116 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_117; +// synthesis translate_on +always @(*) begin + soc_litedramcore_cmd_last <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + end else begin + soc_litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (soc_litedramcore_zqcs_executer_done) begin + soc_litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_117 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_118; +// synthesis translate_on +always @(*) begin + soc_litedramcore_sequencer_start0 <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + if (soc_litedramcore_cmd_ready) begin + soc_litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_118 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine0_req_valid; +assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine0_req_we; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine0_cmd_buffer_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid); +assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine0_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]); +assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; + +// synthesis translate_off +reg dummy_d_119; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_a <= 16'd0; + if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]; + end else begin + soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_119 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write); +assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); +assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); + +// synthesis translate_off +reg dummy_d_120; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7])) begin + soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_120 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_121; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_121 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_122; +// synthesis translate_on +always @(*) begin + vns_bankmachine0_next_state <= 4'd0; + vns_bankmachine0_next_state <= vns_bankmachine0_state; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + if (soc_litedramcore_bankmachine0_cmd_ready) begin + vns_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + vns_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + if (soc_litedramcore_bankmachine0_cmd_ready) begin + vns_bankmachine0_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine0_refresh_req)) begin + vns_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine0_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + vns_bankmachine0_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin + vns_bankmachine0_next_state <= 2'd2; + end + end else begin + vns_bankmachine0_next_state <= 1'd1; + end + end else begin + vns_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_122 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_123; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_123 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_124; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine0_twtpcon_ready) begin + soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_124 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_125; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_125 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_126; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_row_open <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_126 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_127; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_row_close <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_127 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_128; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_128 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_129; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_129 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_130; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_130 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_131; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_131 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_132; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_132 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_133; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_133 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_134; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_134 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_135; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_135 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine1_req_valid; +assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine1_req_we; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine1_cmd_buffer_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid); +assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine1_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]); +assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; + +// synthesis translate_off +reg dummy_d_136; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_a <= 16'd0; + if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]; + end else begin + soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_136 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write); +assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); +assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); + +// synthesis translate_off +reg dummy_d_137; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7])) begin + soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_137 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_138; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_138 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_139; +// synthesis translate_on +always @(*) begin + vns_bankmachine1_next_state <= 4'd0; + vns_bankmachine1_next_state <= vns_bankmachine1_state; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + if (soc_litedramcore_bankmachine1_cmd_ready) begin + vns_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + vns_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + if (soc_litedramcore_bankmachine1_cmd_ready) begin + vns_bankmachine1_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine1_refresh_req)) begin + vns_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine1_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine1_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine1_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine1_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + vns_bankmachine1_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin + vns_bankmachine1_next_state <= 2'd2; + end + end else begin + vns_bankmachine1_next_state <= 1'd1; + end + end else begin + vns_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_139 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_140; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_140 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_141; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine1_twtpcon_ready) begin + soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_141 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_142; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_142 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_143; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_143 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_144; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_row_open <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_144 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_145; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_row_close <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + soc_litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_145 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_146; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_146 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_147; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_147 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_148; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_148 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_149; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_149 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_150; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_150 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_151; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_151 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_152; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_152 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid; +assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid); +assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]); +assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; + +// synthesis translate_off +reg dummy_d_153; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_a <= 16'd0; + if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]; + end else begin + soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_153 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write); +assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); +assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); + +// synthesis translate_off +reg dummy_d_154; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7])) begin + soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_154 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_155; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_155 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_156; +// synthesis translate_on +always @(*) begin + vns_bankmachine2_next_state <= 4'd0; + vns_bankmachine2_next_state <= vns_bankmachine2_state; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + if (soc_litedramcore_bankmachine2_cmd_ready) begin + vns_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + vns_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + if (soc_litedramcore_bankmachine2_cmd_ready) begin + vns_bankmachine2_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine2_refresh_req)) begin + vns_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine2_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine2_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine2_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine2_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + vns_bankmachine2_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin + vns_bankmachine2_next_state <= 2'd2; + end + end else begin + vns_bankmachine2_next_state <= 1'd1; + end + end else begin + vns_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_156 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_157; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_157 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_158; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine2_twtpcon_ready) begin + soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_158 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_159; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_159 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_160; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_row_open <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_160 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_161; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_row_close <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_161 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_162; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_162 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_163; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_163 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_164; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_164 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_165; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_165 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_166; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_166 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_167; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_167 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_168; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_168 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_169; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_169 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine3_req_valid; +assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine3_req_we; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine3_cmd_buffer_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid); +assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine3_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]); +assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; + +// synthesis translate_off +reg dummy_d_170; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_a <= 16'd0; + if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]; + end else begin + soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_170 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write); +assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); +assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); + +// synthesis translate_off +reg dummy_d_171; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7])) begin + soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_171 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_172; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_172 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_173; +// synthesis translate_on +always @(*) begin + vns_bankmachine3_next_state <= 4'd0; + vns_bankmachine3_next_state <= vns_bankmachine3_state; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + if (soc_litedramcore_bankmachine3_cmd_ready) begin + vns_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + vns_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + if (soc_litedramcore_bankmachine3_cmd_ready) begin + vns_bankmachine3_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine3_refresh_req)) begin + vns_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine3_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine3_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine3_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine3_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + vns_bankmachine3_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin + vns_bankmachine3_next_state <= 2'd2; + end + end else begin + vns_bankmachine3_next_state <= 1'd1; + end + end else begin + vns_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_173 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_174; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_174 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_175; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine3_twtpcon_ready) begin + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_175 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_176; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_176 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_177; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_177 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_178; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_row_open <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_178 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_179; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_row_close <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + soc_litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_179 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_180; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_180 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_181; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_181 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_182; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_182 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_183; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_183 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_184; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_184 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_185; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_185 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_186; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_186 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid; +assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid); +assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]); +assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; + +// synthesis translate_off +reg dummy_d_187; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_a <= 16'd0; + if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]; + end else begin + soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_187 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write); +assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); +assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); + +// synthesis translate_off +reg dummy_d_188; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7])) begin + soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_188 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_189; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_189 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_190; +// synthesis translate_on +always @(*) begin + vns_bankmachine4_next_state <= 4'd0; + vns_bankmachine4_next_state <= vns_bankmachine4_state; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + if (soc_litedramcore_bankmachine4_cmd_ready) begin + vns_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + vns_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + if (soc_litedramcore_bankmachine4_cmd_ready) begin + vns_bankmachine4_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine4_refresh_req)) begin + vns_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine4_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine4_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine4_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine4_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + vns_bankmachine4_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin + vns_bankmachine4_next_state <= 2'd2; + end + end else begin + vns_bankmachine4_next_state <= 1'd1; + end + end else begin + vns_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_190 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_191; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_191 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_192; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_192 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_193; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine4_twtpcon_ready) begin + soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_193 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_194; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_194 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_195; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_row_open <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_195 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_196; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_row_close <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_196 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_197; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_197 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_198; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_198 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_199; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_199 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_200; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_200 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_201; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_201 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_202; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_202 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_203; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_203 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine5_req_valid; +assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine5_req_we; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine5_cmd_buffer_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid); +assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine5_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]); +assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; + +// synthesis translate_off +reg dummy_d_204; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_a <= 16'd0; + if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]; + end else begin + soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_204 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write); +assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); +assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); + +// synthesis translate_off +reg dummy_d_205; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7])) begin + soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_205 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_206; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_206 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_207; +// synthesis translate_on +always @(*) begin + vns_bankmachine5_next_state <= 4'd0; + vns_bankmachine5_next_state <= vns_bankmachine5_state; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + if (soc_litedramcore_bankmachine5_cmd_ready) begin + vns_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + vns_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + if (soc_litedramcore_bankmachine5_cmd_ready) begin + vns_bankmachine5_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine5_refresh_req)) begin + vns_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine5_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine5_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine5_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine5_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + vns_bankmachine5_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin + vns_bankmachine5_next_state <= 2'd2; + end + end else begin + vns_bankmachine5_next_state <= 1'd1; + end + end else begin + vns_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_207 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_208; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_208 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_209; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine5_twtpcon_ready) begin + soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_209 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_210; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_210 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_211; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_211 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_212; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_row_open <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_212 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_213; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_row_close <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + soc_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_213 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_214; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_214 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_215; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_215 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_216; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_216 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_217; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_217 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_218; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_218 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_219; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_219 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_220; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_220 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid; +assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid); +assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]); +assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; + +// synthesis translate_off +reg dummy_d_221; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_a <= 16'd0; + if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]; + end else begin + soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_221 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write); +assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); +assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); + +// synthesis translate_off +reg dummy_d_222; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7])) begin + soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_222 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_223; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_223 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_224; +// synthesis translate_on +always @(*) begin + vns_bankmachine6_next_state <= 4'd0; + vns_bankmachine6_next_state <= vns_bankmachine6_state; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + if (soc_litedramcore_bankmachine6_cmd_ready) begin + vns_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + vns_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + if (soc_litedramcore_bankmachine6_cmd_ready) begin + vns_bankmachine6_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine6_refresh_req)) begin + vns_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine6_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine6_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine6_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine6_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + vns_bankmachine6_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin + vns_bankmachine6_next_state <= 2'd2; + end + end else begin + vns_bankmachine6_next_state <= 1'd1; + end + end else begin + vns_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_224 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_225; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_225 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_226; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine6_twtpcon_ready) begin + soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_226 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_227; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_227 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_228; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_row_open <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_228 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_229; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_row_close <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_229 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_230; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_230 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_231; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_231 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_232; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_232 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_233; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_233 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_234; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_234 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_235; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_235 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_236; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_236 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_237; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_237 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine7_req_valid; +assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine7_req_we; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine7_cmd_buffer_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid); +assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine7_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]); +assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; + +// synthesis translate_off +reg dummy_d_238; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_a <= 16'd0; + if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]; + end else begin + soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_238 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write); +assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); +assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); + +// synthesis translate_off +reg dummy_d_239; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[22:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7])) begin + soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_239 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_240; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_240 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_241; +// synthesis translate_on +always @(*) begin + vns_bankmachine7_next_state <= 4'd0; + vns_bankmachine7_next_state <= vns_bankmachine7_state; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + if (soc_litedramcore_bankmachine7_cmd_ready) begin + vns_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + vns_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + if (soc_litedramcore_bankmachine7_cmd_ready) begin + vns_bankmachine7_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine7_refresh_req)) begin + vns_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine7_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine7_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine7_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine7_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + vns_bankmachine7_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin + vns_bankmachine7_next_state <= 2'd2; + end + end else begin + vns_bankmachine7_next_state <= 1'd1; + end + end else begin + vns_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_241 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_242; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_242 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_243; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_243 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_244; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine7_twtpcon_ready) begin + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_244 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_245; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_245 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_246; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_row_open <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_246 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_247; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_row_close <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_247 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_248; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_248 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_249; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_249 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_250; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_250 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_251; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_251 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_252; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_252 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_253; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_253 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_254; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_254 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); +assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); +assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready); +assign soc_litedramcore_tccdcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_cmd_payload_is_write | soc_litedramcore_choose_req_cmd_payload_is_read)); +assign soc_litedramcore_cas_allowed = soc_litedramcore_tccdcon_ready; +assign soc_litedramcore_twtrcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); +assign soc_litedramcore_read_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_read) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_read)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_read)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_read)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_read)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_read)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_read)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_read)); +assign soc_litedramcore_write_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_write) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_write)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_write)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_write)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_write)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_write)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_write)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_write)); +assign soc_litedramcore_max_time0 = (soc_litedramcore_time0 == 1'd0); +assign soc_litedramcore_max_time1 = (soc_litedramcore_time1 == 1'd0); +assign soc_litedramcore_bankmachine0_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine1_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine2_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine3_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine4_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine5_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine6_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_bankmachine7_refresh_req = soc_litedramcore_cmd_valid; +assign soc_litedramcore_go_to_refresh = (((((((soc_litedramcore_bankmachine0_refresh_gnt & soc_litedramcore_bankmachine1_refresh_gnt) & soc_litedramcore_bankmachine2_refresh_gnt) & soc_litedramcore_bankmachine3_refresh_gnt) & soc_litedramcore_bankmachine4_refresh_gnt) & soc_litedramcore_bankmachine5_refresh_gnt) & soc_litedramcore_bankmachine6_refresh_gnt) & soc_litedramcore_bankmachine7_refresh_gnt); +assign soc_litedramcore_interface_rdata = {soc_litedramcore_dfi_p3_rddata, soc_litedramcore_dfi_p2_rddata, soc_litedramcore_dfi_p1_rddata, soc_litedramcore_dfi_p0_rddata}; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata; +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); +assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); + +// synthesis translate_off +reg dummy_d_255; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_cmd_valids <= 8'd0; + soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); +// synthesis translate_off + dummy_d_255 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids; +assign soc_litedramcore_choose_cmd_cmd_valid = vns_rhs_array_muxed0; +assign soc_litedramcore_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1; +assign soc_litedramcore_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2; +assign soc_litedramcore_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3; +assign soc_litedramcore_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4; +assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5; + +// synthesis translate_off +reg dummy_d_256; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0; + end +// synthesis translate_off + dummy_d_256 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_257; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1; + end +// synthesis translate_off + dummy_d_257 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_258; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_we <= vns_t_array_muxed2; + end +// synthesis translate_off + dummy_d_258 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_259; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin + soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin + soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_259 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_260; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin + soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin + soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_260 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_261; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin + soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin + soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_261 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_262; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin + soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin + soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_262 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_263; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin + soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin + soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_263 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_264; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin + soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin + soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_264 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_265; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin + soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin + soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_265 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_266; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin + soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin + soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_266 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid)); + +// synthesis translate_off +reg dummy_d_267; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_valids <= 8'd0; + soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); +// synthesis translate_off + dummy_d_267 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids; +assign soc_litedramcore_choose_req_cmd_valid = vns_rhs_array_muxed6; +assign soc_litedramcore_choose_req_cmd_payload_a = vns_rhs_array_muxed7; +assign soc_litedramcore_choose_req_cmd_payload_ba = vns_rhs_array_muxed8; +assign soc_litedramcore_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9; +assign soc_litedramcore_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10; +assign soc_litedramcore_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11; + +// synthesis translate_off +reg dummy_d_268; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_cas <= vns_t_array_muxed3; + end +// synthesis translate_off + dummy_d_268 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_269; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_ras <= vns_t_array_muxed4; + end +// synthesis translate_off + dummy_d_269 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_270; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_we <= vns_t_array_muxed5; + end +// synthesis translate_off + dummy_d_270 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid)); +assign soc_litedramcore_dfi_p0_reset_n = 1'd1; +assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}}; +assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}}; +assign soc_litedramcore_dfi_p1_reset_n = 1'd1; +assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}}; +assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}}; +assign soc_litedramcore_dfi_p2_reset_n = 1'd1; +assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}}; +assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}}; +assign soc_litedramcore_dfi_p3_reset_n = 1'd1; +assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}}; +assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}}; +assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]); + +// synthesis translate_off +reg dummy_d_271; +// synthesis translate_on +always @(*) begin + vns_multiplexer_next_state <= 4'd0; + vns_multiplexer_next_state <= vns_multiplexer_state; + case (vns_multiplexer_state) + 1'd1: begin + if (soc_litedramcore_read_available) begin + if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin + vns_multiplexer_next_state <= 2'd3; + end + end + if (soc_litedramcore_go_to_refresh) begin + vns_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (soc_litedramcore_cmd_last) begin + vns_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (soc_litedramcore_twtrcon_ready) begin + vns_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + vns_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + vns_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + vns_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + vns_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + vns_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + vns_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + vns_multiplexer_next_state <= 1'd1; + end + default: begin + if (soc_litedramcore_write_available) begin + if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin + vns_multiplexer_next_state <= 3'd4; + end + end + if (soc_litedramcore_go_to_refresh) begin + vns_multiplexer_next_state <= 2'd2; + end + end + endcase +// synthesis translate_off + dummy_d_271 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_272; +// synthesis translate_on +always @(*) begin + soc_litedramcore_en0 <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_en0 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_272 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_273; +// synthesis translate_on +always @(*) begin + soc_litedramcore_steerer_sel3 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel3 <= 2'd2; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_steerer_sel3 <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_273 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_274; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + end + end + endcase +// synthesis translate_off + dummy_d_274 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_275; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_want_reads <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_275 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_276; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_want_writes <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_276 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_277; +// synthesis translate_on +always @(*) begin + soc_litedramcore_cmd_ready <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + soc_litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_277 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_278; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_req_cmd_ready <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + if (1'd0) begin + soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + end else begin + soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + end else begin + soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + end + end + endcase +// synthesis translate_off + dummy_d_278 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_279; +// synthesis translate_on +always @(*) begin + soc_litedramcore_en1 <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_279 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_280; +// synthesis translate_on +always @(*) begin + soc_litedramcore_steerer_sel0 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel0 <= 1'd0; + end + 2'd2: begin + soc_litedramcore_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_steerer_sel0 <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_280 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_281; +// synthesis translate_on +always @(*) begin + soc_litedramcore_steerer_sel1 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel1 <= 1'd0; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_steerer_sel1 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_281 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_282; +// synthesis translate_on +always @(*) begin + soc_litedramcore_steerer_sel2 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel2 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_steerer_sel2 <= 2'd2; + end + endcase +// synthesis translate_off + dummy_d_282 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_283; +// synthesis translate_on +always @(*) begin + soc_litedramcore_choose_cmd_want_activates <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + end + end + endcase +// synthesis translate_off + dummy_d_283 = dummy_s; +// synthesis translate_on +end +assign vns_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock)); +assign soc_litedramcore_interface_bank0_addr = vns_rhs_array_muxed12; +assign soc_litedramcore_interface_bank0_we = vns_rhs_array_muxed13; +assign soc_litedramcore_interface_bank0_valid = vns_rhs_array_muxed14; +assign vns_roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock)); +assign soc_litedramcore_interface_bank1_addr = vns_rhs_array_muxed15; +assign soc_litedramcore_interface_bank1_we = vns_rhs_array_muxed16; +assign soc_litedramcore_interface_bank1_valid = vns_rhs_array_muxed17; +assign vns_roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock)); +assign soc_litedramcore_interface_bank2_addr = vns_rhs_array_muxed18; +assign soc_litedramcore_interface_bank2_we = vns_rhs_array_muxed19; +assign soc_litedramcore_interface_bank2_valid = vns_rhs_array_muxed20; +assign vns_roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock)); +assign soc_litedramcore_interface_bank3_addr = vns_rhs_array_muxed21; +assign soc_litedramcore_interface_bank3_we = vns_rhs_array_muxed22; +assign soc_litedramcore_interface_bank3_valid = vns_rhs_array_muxed23; +assign vns_roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock)); +assign soc_litedramcore_interface_bank4_addr = vns_rhs_array_muxed24; +assign soc_litedramcore_interface_bank4_we = vns_rhs_array_muxed25; +assign soc_litedramcore_interface_bank4_valid = vns_rhs_array_muxed26; +assign vns_roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock)); +assign soc_litedramcore_interface_bank5_addr = vns_rhs_array_muxed27; +assign soc_litedramcore_interface_bank5_we = vns_rhs_array_muxed28; +assign soc_litedramcore_interface_bank5_valid = vns_rhs_array_muxed29; +assign vns_roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock)); +assign soc_litedramcore_interface_bank6_addr = vns_rhs_array_muxed30; +assign soc_litedramcore_interface_bank6_we = vns_rhs_array_muxed31; +assign soc_litedramcore_interface_bank6_valid = vns_rhs_array_muxed32; +assign vns_roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)}; +assign vns_roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock)); +assign soc_litedramcore_interface_bank7_addr = vns_rhs_array_muxed33; +assign soc_litedramcore_interface_bank7_we = vns_rhs_array_muxed34; +assign soc_litedramcore_interface_bank7_valid = vns_rhs_array_muxed35; +assign soc_user_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready)); +assign soc_user_port_wdata_ready = vns_new_master_wdata_ready2; +assign soc_user_port_rdata_valid = vns_new_master_rdata_valid8; + +// synthesis translate_off +reg dummy_d_284; +// synthesis translate_on +always @(*) begin + soc_litedramcore_interface_wdata_we <= 16'd0; + case ({vns_new_master_wdata_ready2}) + 1'd1: begin + soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; + end + default: begin + soc_litedramcore_interface_wdata_we <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_284 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_285; +// synthesis translate_on +always @(*) begin + soc_litedramcore_interface_wdata <= 128'd0; + case ({vns_new_master_wdata_ready2}) + 1'd1: begin + soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; + end + default: begin + soc_litedramcore_interface_wdata <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_285 = dummy_s; +// synthesis translate_on +end +assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata; +assign vns_roundrobin0_grant = 1'd0; +assign vns_roundrobin1_grant = 1'd0; +assign vns_roundrobin2_grant = 1'd0; +assign vns_roundrobin3_grant = 1'd0; +assign vns_roundrobin4_grant = 1'd0; +assign vns_roundrobin5_grant = 1'd0; +assign vns_roundrobin6_grant = 1'd0; +assign vns_roundrobin7_grant = 1'd0; +assign soc_litedramcore_wishbone_adr = soc_wb_bus_adr; +assign soc_litedramcore_wishbone_dat_w = soc_wb_bus_dat_w; +assign soc_wb_bus_dat_r = soc_litedramcore_wishbone_dat_r; +assign soc_litedramcore_wishbone_sel = soc_wb_bus_sel; +assign soc_litedramcore_wishbone_cyc = soc_wb_bus_cyc; +assign soc_litedramcore_wishbone_stb = soc_wb_bus_stb; +assign soc_wb_bus_ack = soc_litedramcore_wishbone_ack; +assign soc_litedramcore_wishbone_we = soc_wb_bus_we; +assign soc_litedramcore_wishbone_cti = soc_wb_bus_cti; +assign soc_litedramcore_wishbone_bte = soc_wb_bus_bte; +assign soc_wb_bus_err = soc_litedramcore_wishbone_err; +assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 2'd2); +assign vns_csrbank0_init_done0_r = vns_interface0_bank_bus_dat_w[0]; +assign vns_csrbank0_init_done0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd0)); +assign vns_csrbank0_init_done0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd0)); +assign vns_csrbank0_init_error0_r = vns_interface0_bank_bus_dat_w[0]; +assign vns_csrbank0_init_error0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[0] == 1'd1)); +assign vns_csrbank0_init_error0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[0] == 1'd1)); +assign vns_csrbank0_init_done0_w = soc_init_done_storage; +assign vns_csrbank0_init_error0_w = soc_init_error_storage; +assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 1'd0); +assign vns_csrbank1_half_sys8x_taps0_r = vns_interface1_bank_bus_dat_w[4:0]; +assign vns_csrbank1_half_sys8x_taps0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd0)); +assign vns_csrbank1_half_sys8x_taps0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd0)); +assign vns_csrbank1_wlevel_en0_r = vns_interface1_bank_bus_dat_w[0]; +assign vns_csrbank1_wlevel_en0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 1'd1)); +assign vns_csrbank1_wlevel_en0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 1'd1)); +assign soc_a7ddrphy_wlevel_strobe_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd2)); +assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd2)); +assign soc_a7ddrphy_cdly_rst_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 2'd3)); +assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 2'd3)); +assign soc_a7ddrphy_cdly_inc_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd4)); +assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd4)); +assign vns_csrbank1_dly_sel0_r = vns_interface1_bank_bus_dat_w[1:0]; +assign vns_csrbank1_dly_sel0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd5)); +assign vns_csrbank1_dly_sel0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd5)); +assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd6)); +assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd6)); +assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 3'd7)); +assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 3'd7)); +assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd8)); +assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd8)); +assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface1_bank_bus_dat_w[0]; +assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[3:0] == 4'd9)); +assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[3:0] == 4'd9)); +assign vns_csrbank1_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign vns_csrbank1_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage; +assign vns_csrbank1_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0]; +assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 1'd1); +assign vns_csrbank2_dfii_control0_r = vns_interface2_bank_bus_dat_w[3:0]; +assign vns_csrbank2_dfii_control0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 1'd0)); +assign vns_csrbank2_dfii_control0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 1'd0)); +assign vns_csrbank2_dfii_pi0_command0_r = vns_interface2_bank_bus_dat_w[5:0]; +assign vns_csrbank2_dfii_pi0_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 1'd1)); +assign vns_csrbank2_dfii_pi0_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 1'd1)); +assign soc_litedramcore_phaseinjector0_command_issue_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_litedramcore_phaseinjector0_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 2'd2)); +assign soc_litedramcore_phaseinjector0_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 2'd2)); +assign vns_csrbank2_dfii_pi0_address0_r = vns_interface2_bank_bus_dat_w[15:0]; +assign vns_csrbank2_dfii_pi0_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 2'd3)); +assign vns_csrbank2_dfii_pi0_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 2'd3)); +assign vns_csrbank2_dfii_pi0_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; +assign vns_csrbank2_dfii_pi0_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd4)); +assign vns_csrbank2_dfii_pi0_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd4)); +assign vns_csrbank2_dfii_pi0_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi0_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd5)); +assign vns_csrbank2_dfii_pi0_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd5)); +assign vns_csrbank2_dfii_pi0_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi0_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd6)); +assign vns_csrbank2_dfii_pi0_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd6)); +assign vns_csrbank2_dfii_pi1_command0_r = vns_interface2_bank_bus_dat_w[5:0]; +assign vns_csrbank2_dfii_pi1_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 3'd7)); +assign vns_csrbank2_dfii_pi1_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 3'd7)); +assign soc_litedramcore_phaseinjector1_command_issue_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_litedramcore_phaseinjector1_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd8)); +assign soc_litedramcore_phaseinjector1_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd8)); +assign vns_csrbank2_dfii_pi1_address0_r = vns_interface2_bank_bus_dat_w[15:0]; +assign vns_csrbank2_dfii_pi1_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd9)); +assign vns_csrbank2_dfii_pi1_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd9)); +assign vns_csrbank2_dfii_pi1_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; +assign vns_csrbank2_dfii_pi1_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd10)); +assign vns_csrbank2_dfii_pi1_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd10)); +assign vns_csrbank2_dfii_pi1_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi1_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd11)); +assign vns_csrbank2_dfii_pi1_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd11)); +assign vns_csrbank2_dfii_pi1_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi1_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd12)); +assign vns_csrbank2_dfii_pi1_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd12)); +assign vns_csrbank2_dfii_pi2_command0_r = vns_interface2_bank_bus_dat_w[5:0]; +assign vns_csrbank2_dfii_pi2_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd13)); +assign vns_csrbank2_dfii_pi2_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd13)); +assign soc_litedramcore_phaseinjector2_command_issue_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_litedramcore_phaseinjector2_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd14)); +assign soc_litedramcore_phaseinjector2_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd14)); +assign vns_csrbank2_dfii_pi2_address0_r = vns_interface2_bank_bus_dat_w[15:0]; +assign vns_csrbank2_dfii_pi2_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 4'd15)); +assign vns_csrbank2_dfii_pi2_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 4'd15)); +assign vns_csrbank2_dfii_pi2_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; +assign vns_csrbank2_dfii_pi2_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd16)); +assign vns_csrbank2_dfii_pi2_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd16)); +assign vns_csrbank2_dfii_pi2_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi2_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd17)); +assign vns_csrbank2_dfii_pi2_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd17)); +assign vns_csrbank2_dfii_pi2_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi2_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd18)); +assign vns_csrbank2_dfii_pi2_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd18)); +assign vns_csrbank2_dfii_pi3_command0_r = vns_interface2_bank_bus_dat_w[5:0]; +assign vns_csrbank2_dfii_pi3_command0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd19)); +assign vns_csrbank2_dfii_pi3_command0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd19)); +assign soc_litedramcore_phaseinjector3_command_issue_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_litedramcore_phaseinjector3_command_issue_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd20)); +assign soc_litedramcore_phaseinjector3_command_issue_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd20)); +assign vns_csrbank2_dfii_pi3_address0_r = vns_interface2_bank_bus_dat_w[15:0]; +assign vns_csrbank2_dfii_pi3_address0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd21)); +assign vns_csrbank2_dfii_pi3_address0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd21)); +assign vns_csrbank2_dfii_pi3_baddress0_r = vns_interface2_bank_bus_dat_w[2:0]; +assign vns_csrbank2_dfii_pi3_baddress0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd22)); +assign vns_csrbank2_dfii_pi3_baddress0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd22)); +assign vns_csrbank2_dfii_pi3_wrdata0_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi3_wrdata0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd23)); +assign vns_csrbank2_dfii_pi3_wrdata0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd23)); +assign vns_csrbank2_dfii_pi3_rddata_r = vns_interface2_bank_bus_dat_w[31:0]; +assign vns_csrbank2_dfii_pi3_rddata_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[4:0] == 5'd24)); +assign vns_csrbank2_dfii_pi3_rddata_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[4:0] == 5'd24)); +assign soc_litedramcore_sel = soc_litedramcore_storage[0]; +assign soc_litedramcore_cke = soc_litedramcore_storage[1]; +assign soc_litedramcore_odt = soc_litedramcore_storage[2]; +assign soc_litedramcore_reset_n = soc_litedramcore_storage[3]; +assign vns_csrbank2_dfii_control0_w = soc_litedramcore_storage[3:0]; +assign vns_csrbank2_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0]; +assign vns_csrbank2_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[15:0]; +assign vns_csrbank2_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign vns_csrbank2_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign vns_csrbank2_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_status[31:0]; +assign soc_litedramcore_phaseinjector0_we = vns_csrbank2_dfii_pi0_rddata_we; +assign vns_csrbank2_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0]; +assign vns_csrbank2_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[15:0]; +assign vns_csrbank2_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign vns_csrbank2_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign vns_csrbank2_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_status[31:0]; +assign soc_litedramcore_phaseinjector1_we = vns_csrbank2_dfii_pi1_rddata_we; +assign vns_csrbank2_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0]; +assign vns_csrbank2_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[15:0]; +assign vns_csrbank2_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign vns_csrbank2_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign vns_csrbank2_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_status[31:0]; +assign soc_litedramcore_phaseinjector2_we = vns_csrbank2_dfii_pi2_rddata_we; +assign vns_csrbank2_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0]; +assign vns_csrbank2_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[15:0]; +assign vns_csrbank2_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign vns_csrbank2_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign vns_csrbank2_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_status[31:0]; +assign soc_litedramcore_phaseinjector3_we = vns_csrbank2_dfii_pi3_rddata_we; +assign vns_adr = soc_litedramcore_adr; +assign vns_we = soc_litedramcore_we; +assign vns_dat_w = soc_litedramcore_dat_w; +assign soc_litedramcore_dat_r = vns_dat_r; +assign vns_interface0_bank_bus_adr = vns_adr; +assign vns_interface1_bank_bus_adr = vns_adr; +assign vns_interface2_bank_bus_adr = vns_adr; +assign vns_interface0_bank_bus_we = vns_we; +assign vns_interface1_bank_bus_we = vns_we; +assign vns_interface2_bank_bus_we = vns_we; +assign vns_interface0_bank_bus_dat_w = vns_dat_w; +assign vns_interface1_bank_bus_dat_w = vns_dat_w; +assign vns_interface2_bank_bus_dat_w = vns_dat_w; +assign vns_dat_r = ((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r); + +// synthesis translate_off +reg dummy_d_286; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed0 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6]; + end + default: begin + vns_rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7]; + end + endcase +// synthesis translate_off + dummy_d_286 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_287; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed1 <= 16'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + vns_rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_287 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_288; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed2 <= 3'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + vns_rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +// synthesis translate_off + dummy_d_288 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_289; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed3 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + vns_rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +// synthesis translate_off + dummy_d_289 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_290; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed4 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + vns_rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +// synthesis translate_off + dummy_d_290 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_291; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed5 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + vns_rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +// synthesis translate_off + dummy_d_291 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_292; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed0 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + vns_t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +// synthesis translate_off + dummy_d_292 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_293; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed1 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + vns_t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +// synthesis translate_off + dummy_d_293 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_294; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed2 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + vns_t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_294 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_295; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed6 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0]; + end + 1'd1: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1]; + end + 2'd2: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2]; + end + 2'd3: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3]; + end + 3'd4: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4]; + end + 3'd5: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5]; + end + 3'd6: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6]; + end + default: begin + vns_rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7]; + end + endcase +// synthesis translate_off + dummy_d_295 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_296; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed7 <= 16'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + vns_rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_296 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_297; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed8 <= 3'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + vns_rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +// synthesis translate_off + dummy_d_297 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_298; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed9 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + vns_rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +// synthesis translate_off + dummy_d_298 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_299; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed10 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + vns_rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +// synthesis translate_off + dummy_d_299 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_300; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed11 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + vns_rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +// synthesis translate_off + dummy_d_300 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_301; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed3 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + vns_t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +// synthesis translate_off + dummy_d_301 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_302; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed4 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + vns_t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +// synthesis translate_off + dummy_d_302 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_303; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed5 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + vns_t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_303 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_304; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed12 <= 23'd0; + case (vns_roundrobin0_grant) + default: begin + vns_rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_304 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_305; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed13 <= 1'd0; + case (vns_roundrobin0_grant) + default: begin + vns_rhs_array_muxed13 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_305 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_306; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed14 <= 1'd0; + case (vns_roundrobin0_grant) + default: begin + vns_rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_306 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_307; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed15 <= 23'd0; + case (vns_roundrobin1_grant) + default: begin + vns_rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_307 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_308; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed16 <= 1'd0; + case (vns_roundrobin1_grant) + default: begin + vns_rhs_array_muxed16 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_308 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_309; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed17 <= 1'd0; + case (vns_roundrobin1_grant) + default: begin + vns_rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_309 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_310; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed18 <= 23'd0; + case (vns_roundrobin2_grant) + default: begin + vns_rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_310 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_311; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed19 <= 1'd0; + case (vns_roundrobin2_grant) + default: begin + vns_rhs_array_muxed19 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_311 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_312; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed20 <= 1'd0; + case (vns_roundrobin2_grant) + default: begin + vns_rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_312 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_313; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed21 <= 23'd0; + case (vns_roundrobin3_grant) + default: begin + vns_rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_313 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_314; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed22 <= 1'd0; + case (vns_roundrobin3_grant) + default: begin + vns_rhs_array_muxed22 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_314 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_315; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed23 <= 1'd0; + case (vns_roundrobin3_grant) + default: begin + vns_rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_315 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_316; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed24 <= 23'd0; + case (vns_roundrobin4_grant) + default: begin + vns_rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_316 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_317; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed25 <= 1'd0; + case (vns_roundrobin4_grant) + default: begin + vns_rhs_array_muxed25 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_317 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_318; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed26 <= 1'd0; + case (vns_roundrobin4_grant) + default: begin + vns_rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_318 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_319; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed27 <= 23'd0; + case (vns_roundrobin5_grant) + default: begin + vns_rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_319 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_320; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed28 <= 1'd0; + case (vns_roundrobin5_grant) + default: begin + vns_rhs_array_muxed28 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_320 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_321; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed29 <= 1'd0; + case (vns_roundrobin5_grant) + default: begin + vns_rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_321 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_322; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed30 <= 23'd0; + case (vns_roundrobin6_grant) + default: begin + vns_rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_322 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_323; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed31 <= 1'd0; + case (vns_roundrobin6_grant) + default: begin + vns_rhs_array_muxed31 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_323 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_324; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed32 <= 1'd0; + case (vns_roundrobin6_grant) + default: begin + vns_rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_324 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_325; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed33 <= 23'd0; + case (vns_roundrobin7_grant) + default: begin + vns_rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[25:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_325 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_326; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed34 <= 1'd0; + case (vns_roundrobin7_grant) + default: begin + vns_rhs_array_muxed34 <= soc_user_port_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_326 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_327; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed35 <= 1'd0; + case (vns_roundrobin7_grant) + default: begin + vns_rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_litedramcore_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_327 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_328; +// synthesis translate_on +always @(*) begin + vns_array_muxed0 <= 3'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed0 <= soc_litedramcore_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_328 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_329; +// synthesis translate_on +always @(*) begin + vns_array_muxed1 <= 16'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed1 <= soc_litedramcore_nop_a; + end + 1'd1: begin + vns_array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed1 <= soc_litedramcore_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_329 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_330; +// synthesis translate_on +always @(*) begin + vns_array_muxed2 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed2 <= 1'd0; + end + 1'd1: begin + vns_array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_330 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_331; +// synthesis translate_on +always @(*) begin + vns_array_muxed3 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed3 <= 1'd0; + end + 1'd1: begin + vns_array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_331 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_332; +// synthesis translate_on +always @(*) begin + vns_array_muxed4 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed4 <= 1'd0; + end + 1'd1: begin + vns_array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_332 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_333; +// synthesis translate_on +always @(*) begin + vns_array_muxed5 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed5 <= 1'd0; + end + 1'd1: begin + vns_array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_333 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_334; +// synthesis translate_on +always @(*) begin + vns_array_muxed6 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + vns_array_muxed6 <= 1'd0; + end + 1'd1: begin + vns_array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_334 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_335; +// synthesis translate_on +always @(*) begin + vns_array_muxed7 <= 3'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed7 <= soc_litedramcore_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_335 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_336; +// synthesis translate_on +always @(*) begin + vns_array_muxed8 <= 16'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed8 <= soc_litedramcore_nop_a; + end + 1'd1: begin + vns_array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed8 <= soc_litedramcore_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_336 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_337; +// synthesis translate_on +always @(*) begin + vns_array_muxed9 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed9 <= 1'd0; + end + 1'd1: begin + vns_array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_337 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_338; +// synthesis translate_on +always @(*) begin + vns_array_muxed10 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed10 <= 1'd0; + end + 1'd1: begin + vns_array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_338 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_339; +// synthesis translate_on +always @(*) begin + vns_array_muxed11 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed11 <= 1'd0; + end + 1'd1: begin + vns_array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_339 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_340; +// synthesis translate_on +always @(*) begin + vns_array_muxed12 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed12 <= 1'd0; + end + 1'd1: begin + vns_array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_340 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_341; +// synthesis translate_on +always @(*) begin + vns_array_muxed13 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + vns_array_muxed13 <= 1'd0; + end + 1'd1: begin + vns_array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_341 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_342; +// synthesis translate_on +always @(*) begin + vns_array_muxed14 <= 3'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed14 <= soc_litedramcore_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_342 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_343; +// synthesis translate_on +always @(*) begin + vns_array_muxed15 <= 16'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed15 <= soc_litedramcore_nop_a; + end + 1'd1: begin + vns_array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed15 <= soc_litedramcore_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_343 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_344; +// synthesis translate_on +always @(*) begin + vns_array_muxed16 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed16 <= 1'd0; + end + 1'd1: begin + vns_array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_344 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_345; +// synthesis translate_on +always @(*) begin + vns_array_muxed17 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed17 <= 1'd0; + end + 1'd1: begin + vns_array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_345 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_346; +// synthesis translate_on +always @(*) begin + vns_array_muxed18 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed18 <= 1'd0; + end + 1'd1: begin + vns_array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_346 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_347; +// synthesis translate_on +always @(*) begin + vns_array_muxed19 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed19 <= 1'd0; + end + 1'd1: begin + vns_array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_347 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_348; +// synthesis translate_on +always @(*) begin + vns_array_muxed20 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + vns_array_muxed20 <= 1'd0; + end + 1'd1: begin + vns_array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_348 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_349; +// synthesis translate_on +always @(*) begin + vns_array_muxed21 <= 3'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed21 <= soc_litedramcore_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_349 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_350; +// synthesis translate_on +always @(*) begin + vns_array_muxed22 <= 16'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed22 <= soc_litedramcore_nop_a; + end + 1'd1: begin + vns_array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed22 <= soc_litedramcore_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_350 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_351; +// synthesis translate_on +always @(*) begin + vns_array_muxed23 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed23 <= 1'd0; + end + 1'd1: begin + vns_array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_351 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_352; +// synthesis translate_on +always @(*) begin + vns_array_muxed24 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed24 <= 1'd0; + end + 1'd1: begin + vns_array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_352 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_353; +// synthesis translate_on +always @(*) begin + vns_array_muxed25 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed25 <= 1'd0; + end + 1'd1: begin + vns_array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_353 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_354; +// synthesis translate_on +always @(*) begin + vns_array_muxed26 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed26 <= 1'd0; + end + 1'd1: begin + vns_array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_354 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_355; +// synthesis translate_on +always @(*) begin + vns_array_muxed27 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + vns_array_muxed27 <= 1'd0; + end + 1'd1: begin + vns_array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_355 = dummy_s; +// synthesis translate_on +end +assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_locked) | soc_reset); +assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_locked) | soc_reset); +assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_locked) | soc_reset); +assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_locked) | soc_reset); + +always @(posedge iodelay_clk) begin + if ((soc_reset_counter != 1'd0)) begin + soc_reset_counter <= (soc_reset_counter - 1'd1); + end else begin + soc_ic_reset <= 1'd0; + end + if (iodelay_rst) begin + soc_reset_counter <= 4'd15; + soc_ic_reset <= 1'd1; + end +end + +always @(posedge sys_clk) begin + vns_state <= vns_next_state; + soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1); + soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1); + soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en; + soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); + soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); + soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); + soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); + soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en; + soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip0_value <= 1'd0; + end + soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip1_value <= 1'd0; + end + soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip2_value <= 1'd0; + end + soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip3_value <= 1'd0; + end + soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip4_value <= 1'd0; + end + soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip5_value <= 1'd0; + end + soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip6_value <= 1'd0; + end + soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip7_value <= 1'd0; + end + soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip8_value <= 1'd0; + end + soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip9_value <= 1'd0; + end + soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip10_value <= 1'd0; + end + soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip11_value <= 1'd0; + end + soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip12_value <= 1'd0; + end + soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip13_value <= 1'd0; + end + soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip14_value <= 1'd0; + end + soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[23:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip15_value <= 1'd0; + end + soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[23:8]}; + if (soc_litedramcore_inti_p0_rddata_valid) begin + soc_litedramcore_phaseinjector0_status <= soc_litedramcore_inti_p0_rddata; + end + if (soc_litedramcore_inti_p1_rddata_valid) begin + soc_litedramcore_phaseinjector1_status <= soc_litedramcore_inti_p1_rddata; + end + if (soc_litedramcore_inti_p2_rddata_valid) begin + soc_litedramcore_phaseinjector2_status <= soc_litedramcore_inti_p2_rddata; + end + if (soc_litedramcore_inti_p3_rddata_valid) begin + soc_litedramcore_phaseinjector3_status <= soc_litedramcore_inti_p3_rddata; + end + if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin + soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1); + end else begin + soc_litedramcore_timer_count1 <= 10'd781; + end + soc_litedramcore_postponer_req_o <= 1'd0; + if (soc_litedramcore_postponer_req_i) begin + soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1); + if ((soc_litedramcore_postponer_count == 1'd0)) begin + soc_litedramcore_postponer_count <= 1'd0; + soc_litedramcore_postponer_req_o <= 1'd1; + end + end + if (soc_litedramcore_sequencer_start0) begin + soc_litedramcore_sequencer_count <= 1'd0; + end else begin + if (soc_litedramcore_sequencer_done1) begin + if ((soc_litedramcore_sequencer_count != 1'd0)) begin + soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1); + end + end + end + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd0; + if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin + soc_litedramcore_cmd_payload_a <= 11'd1024; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd1; + end + if ((soc_litedramcore_sequencer_counter == 2'd3)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd1; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd0; + end + if ((soc_litedramcore_sequencer_counter == 7'd73)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd1; + end + if ((soc_litedramcore_sequencer_counter == 7'd73)) begin + soc_litedramcore_sequencer_counter <= 1'd0; + end else begin + if ((soc_litedramcore_sequencer_counter != 1'd0)) begin + soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1); + end else begin + if (soc_litedramcore_sequencer_start1) begin + soc_litedramcore_sequencer_counter <= 1'd1; + end + end + end + if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin + soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + soc_litedramcore_zqcs_executer_done <= 1'd0; + if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin + soc_litedramcore_cmd_payload_a <= 11'd1024; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd1; + end + if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd1; + end + if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin + soc_litedramcore_zqcs_executer_counter <= 1'd0; + end else begin + if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin + soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1); + end else begin + if (soc_litedramcore_zqcs_executer_start) begin + soc_litedramcore_zqcs_executer_counter <= 1'd1; + end + end + end + vns_refresher_state <= vns_refresher_next_state; + if (soc_litedramcore_bankmachine0_row_close) begin + soc_litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine0_row_open) begin + soc_litedramcore_bankmachine0_row_opened <= 1'd1; + soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]; + end + end + if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine0_cmd_buffer_source_first <= soc_litedramcore_bankmachine0_cmd_buffer_sink_first; + soc_litedramcore_bankmachine0_cmd_buffer_source_last <= soc_litedramcore_bankmachine0_cmd_buffer_sink_last; + soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine0_twtpcon_valid) begin + soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin + soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine0_trccon_valid) begin + soc_litedramcore_bankmachine0_trccon_count <= 3'd6; + if (1'd0) begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin + soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine0_trascon_valid) begin + soc_litedramcore_bankmachine0_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine0_state <= vns_bankmachine0_next_state; + if (soc_litedramcore_bankmachine1_row_close) begin + soc_litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine1_row_open) begin + soc_litedramcore_bankmachine1_row_opened <= 1'd1; + soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]; + end + end + if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine1_cmd_buffer_source_first <= soc_litedramcore_bankmachine1_cmd_buffer_sink_first; + soc_litedramcore_bankmachine1_cmd_buffer_source_last <= soc_litedramcore_bankmachine1_cmd_buffer_sink_last; + soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine1_twtpcon_valid) begin + soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin + soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine1_trccon_valid) begin + soc_litedramcore_bankmachine1_trccon_count <= 3'd6; + if (1'd0) begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin + soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine1_trascon_valid) begin + soc_litedramcore_bankmachine1_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine1_state <= vns_bankmachine1_next_state; + if (soc_litedramcore_bankmachine2_row_close) begin + soc_litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine2_row_open) begin + soc_litedramcore_bankmachine2_row_opened <= 1'd1; + soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]; + end + end + if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine2_cmd_buffer_source_first <= soc_litedramcore_bankmachine2_cmd_buffer_sink_first; + soc_litedramcore_bankmachine2_cmd_buffer_source_last <= soc_litedramcore_bankmachine2_cmd_buffer_sink_last; + soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine2_twtpcon_valid) begin + soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin + soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine2_trccon_valid) begin + soc_litedramcore_bankmachine2_trccon_count <= 3'd6; + if (1'd0) begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin + soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine2_trascon_valid) begin + soc_litedramcore_bankmachine2_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine2_state <= vns_bankmachine2_next_state; + if (soc_litedramcore_bankmachine3_row_close) begin + soc_litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine3_row_open) begin + soc_litedramcore_bankmachine3_row_opened <= 1'd1; + soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]; + end + end + if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine3_cmd_buffer_source_first <= soc_litedramcore_bankmachine3_cmd_buffer_sink_first; + soc_litedramcore_bankmachine3_cmd_buffer_source_last <= soc_litedramcore_bankmachine3_cmd_buffer_sink_last; + soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine3_twtpcon_valid) begin + soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin + soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine3_trccon_valid) begin + soc_litedramcore_bankmachine3_trccon_count <= 3'd6; + if (1'd0) begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin + soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine3_trascon_valid) begin + soc_litedramcore_bankmachine3_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine3_state <= vns_bankmachine3_next_state; + if (soc_litedramcore_bankmachine4_row_close) begin + soc_litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine4_row_open) begin + soc_litedramcore_bankmachine4_row_opened <= 1'd1; + soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]; + end + end + if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine4_cmd_buffer_source_first <= soc_litedramcore_bankmachine4_cmd_buffer_sink_first; + soc_litedramcore_bankmachine4_cmd_buffer_source_last <= soc_litedramcore_bankmachine4_cmd_buffer_sink_last; + soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine4_twtpcon_valid) begin + soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin + soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine4_trccon_valid) begin + soc_litedramcore_bankmachine4_trccon_count <= 3'd6; + if (1'd0) begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin + soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine4_trascon_valid) begin + soc_litedramcore_bankmachine4_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine4_state <= vns_bankmachine4_next_state; + if (soc_litedramcore_bankmachine5_row_close) begin + soc_litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine5_row_open) begin + soc_litedramcore_bankmachine5_row_opened <= 1'd1; + soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]; + end + end + if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine5_cmd_buffer_source_first <= soc_litedramcore_bankmachine5_cmd_buffer_sink_first; + soc_litedramcore_bankmachine5_cmd_buffer_source_last <= soc_litedramcore_bankmachine5_cmd_buffer_sink_last; + soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine5_twtpcon_valid) begin + soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin + soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine5_trccon_valid) begin + soc_litedramcore_bankmachine5_trccon_count <= 3'd6; + if (1'd0) begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin + soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine5_trascon_valid) begin + soc_litedramcore_bankmachine5_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine5_state <= vns_bankmachine5_next_state; + if (soc_litedramcore_bankmachine6_row_close) begin + soc_litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine6_row_open) begin + soc_litedramcore_bankmachine6_row_opened <= 1'd1; + soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]; + end + end + if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine6_cmd_buffer_source_first <= soc_litedramcore_bankmachine6_cmd_buffer_sink_first; + soc_litedramcore_bankmachine6_cmd_buffer_source_last <= soc_litedramcore_bankmachine6_cmd_buffer_sink_last; + soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine6_twtpcon_valid) begin + soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin + soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine6_trccon_valid) begin + soc_litedramcore_bankmachine6_trccon_count <= 3'd6; + if (1'd0) begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin + soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine6_trascon_valid) begin + soc_litedramcore_bankmachine6_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine6_state <= vns_bankmachine6_next_state; + if (soc_litedramcore_bankmachine7_row_close) begin + soc_litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine7_row_open) begin + soc_litedramcore_bankmachine7_row_opened <= 1'd1; + soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]; + end + end + if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin + soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; + soc_litedramcore_bankmachine7_cmd_buffer_source_first <= soc_litedramcore_bankmachine7_cmd_buffer_sink_first; + soc_litedramcore_bankmachine7_cmd_buffer_source_last <= soc_litedramcore_bankmachine7_cmd_buffer_sink_last; + soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; + soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; + end + if (soc_litedramcore_bankmachine7_twtpcon_valid) begin + soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin + soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine7_trccon_valid) begin + soc_litedramcore_bankmachine7_trccon_count <= 3'd6; + if (1'd0) begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin + soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine7_trascon_valid) begin + soc_litedramcore_bankmachine7_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine7_state <= vns_bankmachine7_next_state; + if ((~soc_litedramcore_en0)) begin + soc_litedramcore_time0 <= 5'd31; + end else begin + if ((~soc_litedramcore_max_time0)) begin + soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1); + end + end + if ((~soc_litedramcore_en1)) begin + soc_litedramcore_time1 <= 4'd15; + end else begin + if ((~soc_litedramcore_max_time1)) begin + soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1); + end + end + if (soc_litedramcore_choose_cmd_ce) begin + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (soc_litedramcore_choose_req_ce) begin + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + soc_litedramcore_dfi_p0_cs_n <= 1'd0; + soc_litedramcore_dfi_p0_bank <= vns_array_muxed0; + soc_litedramcore_dfi_p0_address <= vns_array_muxed1; + soc_litedramcore_dfi_p0_cas_n <= (~vns_array_muxed2); + soc_litedramcore_dfi_p0_ras_n <= (~vns_array_muxed3); + soc_litedramcore_dfi_p0_we_n <= (~vns_array_muxed4); + soc_litedramcore_dfi_p0_rddata_en <= vns_array_muxed5; + soc_litedramcore_dfi_p0_wrdata_en <= vns_array_muxed6; + soc_litedramcore_dfi_p1_cs_n <= 1'd0; + soc_litedramcore_dfi_p1_bank <= vns_array_muxed7; + soc_litedramcore_dfi_p1_address <= vns_array_muxed8; + soc_litedramcore_dfi_p1_cas_n <= (~vns_array_muxed9); + soc_litedramcore_dfi_p1_ras_n <= (~vns_array_muxed10); + soc_litedramcore_dfi_p1_we_n <= (~vns_array_muxed11); + soc_litedramcore_dfi_p1_rddata_en <= vns_array_muxed12; + soc_litedramcore_dfi_p1_wrdata_en <= vns_array_muxed13; + soc_litedramcore_dfi_p2_cs_n <= 1'd0; + soc_litedramcore_dfi_p2_bank <= vns_array_muxed14; + soc_litedramcore_dfi_p2_address <= vns_array_muxed15; + soc_litedramcore_dfi_p2_cas_n <= (~vns_array_muxed16); + soc_litedramcore_dfi_p2_ras_n <= (~vns_array_muxed17); + soc_litedramcore_dfi_p2_we_n <= (~vns_array_muxed18); + soc_litedramcore_dfi_p2_rddata_en <= vns_array_muxed19; + soc_litedramcore_dfi_p2_wrdata_en <= vns_array_muxed20; + soc_litedramcore_dfi_p3_cs_n <= 1'd0; + soc_litedramcore_dfi_p3_bank <= vns_array_muxed21; + soc_litedramcore_dfi_p3_address <= vns_array_muxed22; + soc_litedramcore_dfi_p3_cas_n <= (~vns_array_muxed23); + soc_litedramcore_dfi_p3_ras_n <= (~vns_array_muxed24); + soc_litedramcore_dfi_p3_we_n <= (~vns_array_muxed25); + soc_litedramcore_dfi_p3_rddata_en <= vns_array_muxed26; + soc_litedramcore_dfi_p3_wrdata_en <= vns_array_muxed27; + if (soc_litedramcore_trrdcon_valid) begin + soc_litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + soc_litedramcore_trrdcon_ready <= 1'd1; + end else begin + soc_litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_trrdcon_ready)) begin + soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1); + if ((soc_litedramcore_trrdcon_count == 1'd1)) begin + soc_litedramcore_trrdcon_ready <= 1'd1; + end + end + end + soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid}; + if ((soc_litedramcore_tfawcon_count < 3'd4)) begin + if ((soc_litedramcore_tfawcon_count == 2'd3)) begin + soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid); + end else begin + soc_litedramcore_tfawcon_ready <= 1'd1; + end + end + if (soc_litedramcore_tccdcon_valid) begin + soc_litedramcore_tccdcon_count <= 1'd0; + if (1'd1) begin + soc_litedramcore_tccdcon_ready <= 1'd1; + end else begin + soc_litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_tccdcon_ready)) begin + soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1); + if ((soc_litedramcore_tccdcon_count == 1'd1)) begin + soc_litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_twtrcon_valid) begin + soc_litedramcore_twtrcon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_twtrcon_ready <= 1'd1; + end else begin + soc_litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_twtrcon_ready)) begin + soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1); + if ((soc_litedramcore_twtrcon_count == 1'd1)) begin + soc_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + vns_multiplexer_state <= vns_multiplexer_next_state; + vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready)); + vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0; + vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1; + vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid)); + vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0; + vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1; + vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2; + vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3; + vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4; + vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5; + vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6; + vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7; + vns_interface0_bank_bus_dat_r <= 1'd0; + if (vns_csrbank0_sel) begin + case (vns_interface0_bank_bus_adr[0]) + 1'd0: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_done0_w; + end + 1'd1: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_init_error0_w; + end + endcase + end + if (vns_csrbank0_init_done0_re) begin + soc_init_done_storage <= vns_csrbank0_init_done0_r; + end + soc_init_done_re <= vns_csrbank0_init_done0_re; + if (vns_csrbank0_init_error0_re) begin + soc_init_error_storage <= vns_csrbank0_init_error0_r; + end + soc_init_error_re <= vns_csrbank0_init_error0_re; + vns_interface1_bank_bus_dat_r <= 1'd0; + if (vns_csrbank1_sel) begin + case (vns_interface1_bank_bus_adr[3:0]) + 1'd0: begin + vns_interface1_bank_bus_dat_r <= vns_csrbank1_half_sys8x_taps0_w; + end + 1'd1: begin + vns_interface1_bank_bus_dat_r <= vns_csrbank1_wlevel_en0_w; + end + 2'd2: begin + vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w; + end + 2'd3: begin + vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w; + end + 3'd4: begin + vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w; + end + 3'd5: begin + vns_interface1_bank_bus_dat_r <= vns_csrbank1_dly_sel0_w; + end + 3'd6: begin + vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w; + end + 3'd7: begin + vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w; + end + 4'd8: begin + vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w; + end + 4'd9: begin + vns_interface1_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w; + end + endcase + end + if (vns_csrbank1_half_sys8x_taps0_re) begin + soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank1_half_sys8x_taps0_r; + end + soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank1_half_sys8x_taps0_re; + if (vns_csrbank1_wlevel_en0_re) begin + soc_a7ddrphy_wlevel_en_storage <= vns_csrbank1_wlevel_en0_r; + end + soc_a7ddrphy_wlevel_en_re <= vns_csrbank1_wlevel_en0_re; + if (vns_csrbank1_dly_sel0_re) begin + soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank1_dly_sel0_r; + end + soc_a7ddrphy_dly_sel_re <= vns_csrbank1_dly_sel0_re; + vns_interface2_bank_bus_dat_r <= 1'd0; + if (vns_csrbank2_sel) begin + case (vns_interface2_bank_bus_adr[4:0]) + 1'd0: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_control0_w; + end + 1'd1: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_command0_w; + end + 2'd2: begin + vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_address0_w; + end + 3'd4: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_baddress0_w; + end + 3'd5: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_wrdata0_w; + end + 3'd6: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi0_rddata_w; + end + 3'd7: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_command0_w; + end + 4'd8: begin + vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w; + end + 4'd9: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_address0_w; + end + 4'd10: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_baddress0_w; + end + 4'd11: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_wrdata0_w; + end + 4'd12: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi1_rddata_w; + end + 4'd13: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_command0_w; + end + 4'd14: begin + vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w; + end + 4'd15: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_address0_w; + end + 5'd16: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_baddress0_w; + end + 5'd17: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_wrdata0_w; + end + 5'd18: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi2_rddata_w; + end + 5'd19: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_command0_w; + end + 5'd20: begin + vns_interface2_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w; + end + 5'd21: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_address0_w; + end + 5'd22: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_baddress0_w; + end + 5'd23: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_wrdata0_w; + end + 5'd24: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dfii_pi3_rddata_w; + end + endcase + end + if (vns_csrbank2_dfii_control0_re) begin + soc_litedramcore_storage[3:0] <= vns_csrbank2_dfii_control0_r; + end + soc_litedramcore_re <= vns_csrbank2_dfii_control0_re; + if (vns_csrbank2_dfii_pi0_command0_re) begin + soc_litedramcore_phaseinjector0_command_storage[5:0] <= vns_csrbank2_dfii_pi0_command0_r; + end + soc_litedramcore_phaseinjector0_command_re <= vns_csrbank2_dfii_pi0_command0_re; + if (vns_csrbank2_dfii_pi0_address0_re) begin + soc_litedramcore_phaseinjector0_address_storage[15:0] <= vns_csrbank2_dfii_pi0_address0_r; + end + soc_litedramcore_phaseinjector0_address_re <= vns_csrbank2_dfii_pi0_address0_re; + if (vns_csrbank2_dfii_pi0_baddress0_re) begin + soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= vns_csrbank2_dfii_pi0_baddress0_r; + end + soc_litedramcore_phaseinjector0_baddress_re <= vns_csrbank2_dfii_pi0_baddress0_re; + if (vns_csrbank2_dfii_pi0_wrdata0_re) begin + soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi0_wrdata0_r; + end + soc_litedramcore_phaseinjector0_wrdata_re <= vns_csrbank2_dfii_pi0_wrdata0_re; + if (vns_csrbank2_dfii_pi1_command0_re) begin + soc_litedramcore_phaseinjector1_command_storage[5:0] <= vns_csrbank2_dfii_pi1_command0_r; + end + soc_litedramcore_phaseinjector1_command_re <= vns_csrbank2_dfii_pi1_command0_re; + if (vns_csrbank2_dfii_pi1_address0_re) begin + soc_litedramcore_phaseinjector1_address_storage[15:0] <= vns_csrbank2_dfii_pi1_address0_r; + end + soc_litedramcore_phaseinjector1_address_re <= vns_csrbank2_dfii_pi1_address0_re; + if (vns_csrbank2_dfii_pi1_baddress0_re) begin + soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= vns_csrbank2_dfii_pi1_baddress0_r; + end + soc_litedramcore_phaseinjector1_baddress_re <= vns_csrbank2_dfii_pi1_baddress0_re; + if (vns_csrbank2_dfii_pi1_wrdata0_re) begin + soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi1_wrdata0_r; + end + soc_litedramcore_phaseinjector1_wrdata_re <= vns_csrbank2_dfii_pi1_wrdata0_re; + if (vns_csrbank2_dfii_pi2_command0_re) begin + soc_litedramcore_phaseinjector2_command_storage[5:0] <= vns_csrbank2_dfii_pi2_command0_r; + end + soc_litedramcore_phaseinjector2_command_re <= vns_csrbank2_dfii_pi2_command0_re; + if (vns_csrbank2_dfii_pi2_address0_re) begin + soc_litedramcore_phaseinjector2_address_storage[15:0] <= vns_csrbank2_dfii_pi2_address0_r; + end + soc_litedramcore_phaseinjector2_address_re <= vns_csrbank2_dfii_pi2_address0_re; + if (vns_csrbank2_dfii_pi2_baddress0_re) begin + soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= vns_csrbank2_dfii_pi2_baddress0_r; + end + soc_litedramcore_phaseinjector2_baddress_re <= vns_csrbank2_dfii_pi2_baddress0_re; + if (vns_csrbank2_dfii_pi2_wrdata0_re) begin + soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi2_wrdata0_r; + end + soc_litedramcore_phaseinjector2_wrdata_re <= vns_csrbank2_dfii_pi2_wrdata0_re; + if (vns_csrbank2_dfii_pi3_command0_re) begin + soc_litedramcore_phaseinjector3_command_storage[5:0] <= vns_csrbank2_dfii_pi3_command0_r; + end + soc_litedramcore_phaseinjector3_command_re <= vns_csrbank2_dfii_pi3_command0_re; + if (vns_csrbank2_dfii_pi3_address0_re) begin + soc_litedramcore_phaseinjector3_address_storage[15:0] <= vns_csrbank2_dfii_pi3_address0_r; + end + soc_litedramcore_phaseinjector3_address_re <= vns_csrbank2_dfii_pi3_address0_re; + if (vns_csrbank2_dfii_pi3_baddress0_re) begin + soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= vns_csrbank2_dfii_pi3_baddress0_r; + end + soc_litedramcore_phaseinjector3_baddress_re <= vns_csrbank2_dfii_pi3_baddress0_re; + if (vns_csrbank2_dfii_pi3_wrdata0_re) begin + soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= vns_csrbank2_dfii_pi3_wrdata0_r; + end + soc_litedramcore_phaseinjector3_wrdata_re <= vns_csrbank2_dfii_pi3_wrdata0_re; + if (sys_rst) begin + soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8; + soc_a7ddrphy_half_sys8x_taps_re <= 1'd0; + soc_a7ddrphy_wlevel_en_storage <= 1'd0; + soc_a7ddrphy_wlevel_en_re <= 1'd0; + soc_a7ddrphy_dly_sel_storage <= 2'd0; + soc_a7ddrphy_dly_sel_re <= 1'd0; + soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0; + soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0; + soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0; + soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0; + soc_a7ddrphy_dqs_oe_delayed <= 1'd0; + soc_a7ddrphy_dqspattern_o1 <= 8'd0; + soc_a7ddrphy_dq_oe_delayed <= 1'd0; + soc_a7ddrphy_bitslip0_value <= 4'd0; + soc_a7ddrphy_bitslip1_value <= 4'd0; + soc_a7ddrphy_bitslip2_value <= 4'd0; + soc_a7ddrphy_bitslip3_value <= 4'd0; + soc_a7ddrphy_bitslip4_value <= 4'd0; + soc_a7ddrphy_bitslip5_value <= 4'd0; + soc_a7ddrphy_bitslip6_value <= 4'd0; + soc_a7ddrphy_bitslip7_value <= 4'd0; + soc_a7ddrphy_bitslip8_value <= 4'd0; + soc_a7ddrphy_bitslip9_value <= 4'd0; + soc_a7ddrphy_bitslip10_value <= 4'd0; + soc_a7ddrphy_bitslip11_value <= 4'd0; + soc_a7ddrphy_bitslip12_value <= 4'd0; + soc_a7ddrphy_bitslip13_value <= 4'd0; + soc_a7ddrphy_bitslip14_value <= 4'd0; + soc_a7ddrphy_bitslip15_value <= 4'd0; + soc_a7ddrphy_rddata_en_last <= 8'd0; + soc_a7ddrphy_wrdata_en_last <= 4'd0; + soc_litedramcore_storage <= 4'd1; + soc_litedramcore_re <= 1'd0; + soc_litedramcore_phaseinjector0_command_storage <= 6'd0; + soc_litedramcore_phaseinjector0_command_re <= 1'd0; + soc_litedramcore_phaseinjector0_address_re <= 1'd0; + soc_litedramcore_phaseinjector0_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector0_status <= 32'd0; + soc_litedramcore_phaseinjector1_command_storage <= 6'd0; + soc_litedramcore_phaseinjector1_command_re <= 1'd0; + soc_litedramcore_phaseinjector1_address_re <= 1'd0; + soc_litedramcore_phaseinjector1_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector1_status <= 32'd0; + soc_litedramcore_phaseinjector2_command_storage <= 6'd0; + soc_litedramcore_phaseinjector2_command_re <= 1'd0; + soc_litedramcore_phaseinjector2_address_re <= 1'd0; + soc_litedramcore_phaseinjector2_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector2_status <= 32'd0; + soc_litedramcore_phaseinjector3_command_storage <= 6'd0; + soc_litedramcore_phaseinjector3_command_re <= 1'd0; + soc_litedramcore_phaseinjector3_address_re <= 1'd0; + soc_litedramcore_phaseinjector3_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector3_status <= 32'd0; + soc_litedramcore_dfi_p0_address <= 16'd0; + soc_litedramcore_dfi_p0_bank <= 3'd0; + soc_litedramcore_dfi_p0_cas_n <= 1'd1; + soc_litedramcore_dfi_p0_cs_n <= 1'd1; + soc_litedramcore_dfi_p0_ras_n <= 1'd1; + soc_litedramcore_dfi_p0_we_n <= 1'd1; + soc_litedramcore_dfi_p0_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p0_rddata_en <= 1'd0; + soc_litedramcore_dfi_p1_address <= 16'd0; + soc_litedramcore_dfi_p1_bank <= 3'd0; + soc_litedramcore_dfi_p1_cas_n <= 1'd1; + soc_litedramcore_dfi_p1_cs_n <= 1'd1; + soc_litedramcore_dfi_p1_ras_n <= 1'd1; + soc_litedramcore_dfi_p1_we_n <= 1'd1; + soc_litedramcore_dfi_p1_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p1_rddata_en <= 1'd0; + soc_litedramcore_dfi_p2_address <= 16'd0; + soc_litedramcore_dfi_p2_bank <= 3'd0; + soc_litedramcore_dfi_p2_cas_n <= 1'd1; + soc_litedramcore_dfi_p2_cs_n <= 1'd1; + soc_litedramcore_dfi_p2_ras_n <= 1'd1; + soc_litedramcore_dfi_p2_we_n <= 1'd1; + soc_litedramcore_dfi_p2_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p2_rddata_en <= 1'd0; + soc_litedramcore_dfi_p3_address <= 16'd0; + soc_litedramcore_dfi_p3_bank <= 3'd0; + soc_litedramcore_dfi_p3_cas_n <= 1'd1; + soc_litedramcore_dfi_p3_cs_n <= 1'd1; + soc_litedramcore_dfi_p3_ras_n <= 1'd1; + soc_litedramcore_dfi_p3_we_n <= 1'd1; + soc_litedramcore_dfi_p3_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p3_rddata_en <= 1'd0; + soc_litedramcore_timer_count1 <= 10'd781; + soc_litedramcore_postponer_req_o <= 1'd0; + soc_litedramcore_postponer_count <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd0; + soc_litedramcore_sequencer_counter <= 7'd0; + soc_litedramcore_sequencer_count <= 1'd0; + soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; + soc_litedramcore_zqcs_executer_done <= 1'd0; + soc_litedramcore_zqcs_executer_counter <= 5'd0; + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine0_row <= 16'd0; + soc_litedramcore_bankmachine0_row_opened <= 1'd0; + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine0_trccon_count <= 3'd0; + soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine0_trascon_count <= 3'd0; + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine1_row <= 16'd0; + soc_litedramcore_bankmachine1_row_opened <= 1'd0; + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine1_trccon_count <= 3'd0; + soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine1_trascon_count <= 3'd0; + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine2_row <= 16'd0; + soc_litedramcore_bankmachine2_row_opened <= 1'd0; + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine2_trccon_count <= 3'd0; + soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine2_trascon_count <= 3'd0; + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine3_row <= 16'd0; + soc_litedramcore_bankmachine3_row_opened <= 1'd0; + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine3_trccon_count <= 3'd0; + soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine3_trascon_count <= 3'd0; + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine4_row <= 16'd0; + soc_litedramcore_bankmachine4_row_opened <= 1'd0; + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine4_trccon_count <= 3'd0; + soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine4_trascon_count <= 3'd0; + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine5_row <= 16'd0; + soc_litedramcore_bankmachine5_row_opened <= 1'd0; + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine5_trccon_count <= 3'd0; + soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine5_trascon_count <= 3'd0; + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine6_row <= 16'd0; + soc_litedramcore_bankmachine6_row_opened <= 1'd0; + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine6_trccon_count <= 3'd0; + soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine6_trascon_count <= 3'd0; + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; + soc_litedramcore_bankmachine7_row <= 16'd0; + soc_litedramcore_bankmachine7_row_opened <= 1'd0; + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine7_trccon_count <= 3'd0; + soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine7_trascon_count <= 3'd0; + soc_litedramcore_choose_cmd_grant <= 3'd0; + soc_litedramcore_choose_req_grant <= 3'd0; + soc_litedramcore_trrdcon_ready <= 1'd0; + soc_litedramcore_trrdcon_count <= 1'd0; + soc_litedramcore_tfawcon_ready <= 1'd1; + soc_litedramcore_tfawcon_window <= 5'd0; + soc_litedramcore_tccdcon_ready <= 1'd0; + soc_litedramcore_tccdcon_count <= 1'd0; + soc_litedramcore_twtrcon_ready <= 1'd0; + soc_litedramcore_twtrcon_count <= 3'd0; + soc_litedramcore_time0 <= 5'd0; + soc_litedramcore_time1 <= 4'd0; + soc_init_done_storage <= 1'd0; + soc_init_done_re <= 1'd0; + soc_init_error_storage <= 1'd0; + soc_init_error_re <= 1'd0; + vns_state <= 1'd0; + vns_refresher_state <= 2'd0; + vns_bankmachine0_state <= 4'd0; + vns_bankmachine1_state <= 4'd0; + vns_bankmachine2_state <= 4'd0; + vns_bankmachine3_state <= 4'd0; + vns_bankmachine4_state <= 4'd0; + vns_bankmachine5_state <= 4'd0; + vns_bankmachine6_state <= 4'd0; + vns_bankmachine7_state <= 4'd0; + vns_multiplexer_state <= 4'd0; + vns_new_master_wdata_ready0 <= 1'd0; + vns_new_master_wdata_ready1 <= 1'd0; + vns_new_master_wdata_ready2 <= 1'd0; + vns_new_master_rdata_valid0 <= 1'd0; + vns_new_master_rdata_valid1 <= 1'd0; + vns_new_master_rdata_valid2 <= 1'd0; + vns_new_master_rdata_valid3 <= 1'd0; + vns_new_master_rdata_valid4 <= 1'd0; + vns_new_master_rdata_valid5 <= 1'd0; + vns_new_master_rdata_valid6 <= 1'd0; + vns_new_master_rdata_valid7 <= 1'd0; + vns_new_master_rdata_valid8 <= 1'd0; + end +end + +BUFG BUFG( + .I(soc_clkout0), + .O(soc_clkout_buf0) +); + +BUFG BUFG_1( + .I(soc_clkout1), + .O(soc_clkout_buf1) +); + +BUFG BUFG_2( + .I(soc_clkout2), + .O(soc_clkout_buf2) +); + +BUFG BUFG_3( + .I(soc_clkout3), + .O(soc_clkout_buf3) +); + +IDELAYCTRL IDELAYCTRL( + .REFCLK(iodelay_clk), + .RST(soc_ic_reset) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(1'd0), + .D2(1'd1), + .D3(1'd0), + .D4(1'd1), + .D5(1'd0), + .D6(1'd1), + .D7(1'd0), + .D8(1'd1), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_a7ddrphy_sd_clk_se_nodelay) +); + +OBUFDS OBUFDS( + .I(soc_a7ddrphy_sd_clk_se_nodelay), + .O(ddram_clk_p), + .OB(ddram_clk_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_1 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[0]), + .D2(soc_a7ddrphy_dfi_p0_address[0]), + .D3(soc_a7ddrphy_dfi_p1_address[0]), + .D4(soc_a7ddrphy_dfi_p1_address[0]), + .D5(soc_a7ddrphy_dfi_p2_address[0]), + .D6(soc_a7ddrphy_dfi_p2_address[0]), + .D7(soc_a7ddrphy_dfi_p3_address[0]), + .D8(soc_a7ddrphy_dfi_p3_address[0]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[1]), + .D2(soc_a7ddrphy_dfi_p0_address[1]), + .D3(soc_a7ddrphy_dfi_p1_address[1]), + .D4(soc_a7ddrphy_dfi_p1_address[1]), + .D5(soc_a7ddrphy_dfi_p2_address[1]), + .D6(soc_a7ddrphy_dfi_p2_address[1]), + .D7(soc_a7ddrphy_dfi_p3_address[1]), + .D8(soc_a7ddrphy_dfi_p3_address[1]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_3 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[2]), + .D2(soc_a7ddrphy_dfi_p0_address[2]), + .D3(soc_a7ddrphy_dfi_p1_address[2]), + .D4(soc_a7ddrphy_dfi_p1_address[2]), + .D5(soc_a7ddrphy_dfi_p2_address[2]), + .D6(soc_a7ddrphy_dfi_p2_address[2]), + .D7(soc_a7ddrphy_dfi_p3_address[2]), + .D8(soc_a7ddrphy_dfi_p3_address[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_4 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[3]), + .D2(soc_a7ddrphy_dfi_p0_address[3]), + .D3(soc_a7ddrphy_dfi_p1_address[3]), + .D4(soc_a7ddrphy_dfi_p1_address[3]), + .D5(soc_a7ddrphy_dfi_p2_address[3]), + .D6(soc_a7ddrphy_dfi_p2_address[3]), + .D7(soc_a7ddrphy_dfi_p3_address[3]), + .D8(soc_a7ddrphy_dfi_p3_address[3]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[3]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_5 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[4]), + .D2(soc_a7ddrphy_dfi_p0_address[4]), + .D3(soc_a7ddrphy_dfi_p1_address[4]), + .D4(soc_a7ddrphy_dfi_p1_address[4]), + .D5(soc_a7ddrphy_dfi_p2_address[4]), + .D6(soc_a7ddrphy_dfi_p2_address[4]), + .D7(soc_a7ddrphy_dfi_p3_address[4]), + .D8(soc_a7ddrphy_dfi_p3_address[4]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[4]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_6 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[5]), + .D2(soc_a7ddrphy_dfi_p0_address[5]), + .D3(soc_a7ddrphy_dfi_p1_address[5]), + .D4(soc_a7ddrphy_dfi_p1_address[5]), + .D5(soc_a7ddrphy_dfi_p2_address[5]), + .D6(soc_a7ddrphy_dfi_p2_address[5]), + .D7(soc_a7ddrphy_dfi_p3_address[5]), + .D8(soc_a7ddrphy_dfi_p3_address[5]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[5]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_7 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[6]), + .D2(soc_a7ddrphy_dfi_p0_address[6]), + .D3(soc_a7ddrphy_dfi_p1_address[6]), + .D4(soc_a7ddrphy_dfi_p1_address[6]), + .D5(soc_a7ddrphy_dfi_p2_address[6]), + .D6(soc_a7ddrphy_dfi_p2_address[6]), + .D7(soc_a7ddrphy_dfi_p3_address[6]), + .D8(soc_a7ddrphy_dfi_p3_address[6]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[6]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_8 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[7]), + .D2(soc_a7ddrphy_dfi_p0_address[7]), + .D3(soc_a7ddrphy_dfi_p1_address[7]), + .D4(soc_a7ddrphy_dfi_p1_address[7]), + .D5(soc_a7ddrphy_dfi_p2_address[7]), + .D6(soc_a7ddrphy_dfi_p2_address[7]), + .D7(soc_a7ddrphy_dfi_p3_address[7]), + .D8(soc_a7ddrphy_dfi_p3_address[7]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[7]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_9 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[8]), + .D2(soc_a7ddrphy_dfi_p0_address[8]), + .D3(soc_a7ddrphy_dfi_p1_address[8]), + .D4(soc_a7ddrphy_dfi_p1_address[8]), + .D5(soc_a7ddrphy_dfi_p2_address[8]), + .D6(soc_a7ddrphy_dfi_p2_address[8]), + .D7(soc_a7ddrphy_dfi_p3_address[8]), + .D8(soc_a7ddrphy_dfi_p3_address[8]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[8]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_10 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[9]), + .D2(soc_a7ddrphy_dfi_p0_address[9]), + .D3(soc_a7ddrphy_dfi_p1_address[9]), + .D4(soc_a7ddrphy_dfi_p1_address[9]), + .D5(soc_a7ddrphy_dfi_p2_address[9]), + .D6(soc_a7ddrphy_dfi_p2_address[9]), + .D7(soc_a7ddrphy_dfi_p3_address[9]), + .D8(soc_a7ddrphy_dfi_p3_address[9]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[9]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_11 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[10]), + .D2(soc_a7ddrphy_dfi_p0_address[10]), + .D3(soc_a7ddrphy_dfi_p1_address[10]), + .D4(soc_a7ddrphy_dfi_p1_address[10]), + .D5(soc_a7ddrphy_dfi_p2_address[10]), + .D6(soc_a7ddrphy_dfi_p2_address[10]), + .D7(soc_a7ddrphy_dfi_p3_address[10]), + .D8(soc_a7ddrphy_dfi_p3_address[10]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[10]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_12 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[11]), + .D2(soc_a7ddrphy_dfi_p0_address[11]), + .D3(soc_a7ddrphy_dfi_p1_address[11]), + .D4(soc_a7ddrphy_dfi_p1_address[11]), + .D5(soc_a7ddrphy_dfi_p2_address[11]), + .D6(soc_a7ddrphy_dfi_p2_address[11]), + .D7(soc_a7ddrphy_dfi_p3_address[11]), + .D8(soc_a7ddrphy_dfi_p3_address[11]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[11]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_13 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[12]), + .D2(soc_a7ddrphy_dfi_p0_address[12]), + .D3(soc_a7ddrphy_dfi_p1_address[12]), + .D4(soc_a7ddrphy_dfi_p1_address[12]), + .D5(soc_a7ddrphy_dfi_p2_address[12]), + .D6(soc_a7ddrphy_dfi_p2_address[12]), + .D7(soc_a7ddrphy_dfi_p3_address[12]), + .D8(soc_a7ddrphy_dfi_p3_address[12]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[12]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_14 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[13]), + .D2(soc_a7ddrphy_dfi_p0_address[13]), + .D3(soc_a7ddrphy_dfi_p1_address[13]), + .D4(soc_a7ddrphy_dfi_p1_address[13]), + .D5(soc_a7ddrphy_dfi_p2_address[13]), + .D6(soc_a7ddrphy_dfi_p2_address[13]), + .D7(soc_a7ddrphy_dfi_p3_address[13]), + .D8(soc_a7ddrphy_dfi_p3_address[13]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[13]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_15 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[14]), + .D2(soc_a7ddrphy_dfi_p0_address[14]), + .D3(soc_a7ddrphy_dfi_p1_address[14]), + .D4(soc_a7ddrphy_dfi_p1_address[14]), + .D5(soc_a7ddrphy_dfi_p2_address[14]), + .D6(soc_a7ddrphy_dfi_p2_address[14]), + .D7(soc_a7ddrphy_dfi_p3_address[14]), + .D8(soc_a7ddrphy_dfi_p3_address[14]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[14]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_16 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[15]), + .D2(soc_a7ddrphy_dfi_p0_address[15]), + .D3(soc_a7ddrphy_dfi_p1_address[15]), + .D4(soc_a7ddrphy_dfi_p1_address[15]), + .D5(soc_a7ddrphy_dfi_p2_address[15]), + .D6(soc_a7ddrphy_dfi_p2_address[15]), + .D7(soc_a7ddrphy_dfi_p3_address[15]), + .D8(soc_a7ddrphy_dfi_p3_address[15]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[15]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_17 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_bank[0]), + .D2(soc_a7ddrphy_dfi_p0_bank[0]), + .D3(soc_a7ddrphy_dfi_p1_bank[0]), + .D4(soc_a7ddrphy_dfi_p1_bank[0]), + .D5(soc_a7ddrphy_dfi_p2_bank[0]), + .D6(soc_a7ddrphy_dfi_p2_bank[0]), + .D7(soc_a7ddrphy_dfi_p3_bank[0]), + .D8(soc_a7ddrphy_dfi_p3_bank[0]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ba[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_18 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_bank[1]), + .D2(soc_a7ddrphy_dfi_p0_bank[1]), + .D3(soc_a7ddrphy_dfi_p1_bank[1]), + .D4(soc_a7ddrphy_dfi_p1_bank[1]), + .D5(soc_a7ddrphy_dfi_p2_bank[1]), + .D6(soc_a7ddrphy_dfi_p2_bank[1]), + .D7(soc_a7ddrphy_dfi_p3_bank[1]), + .D8(soc_a7ddrphy_dfi_p3_bank[1]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ba[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_19 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_bank[2]), + .D2(soc_a7ddrphy_dfi_p0_bank[2]), + .D3(soc_a7ddrphy_dfi_p1_bank[2]), + .D4(soc_a7ddrphy_dfi_p1_bank[2]), + .D5(soc_a7ddrphy_dfi_p2_bank[2]), + .D6(soc_a7ddrphy_dfi_p2_bank[2]), + .D7(soc_a7ddrphy_dfi_p3_bank[2]), + .D8(soc_a7ddrphy_dfi_p3_bank[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ba[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_20 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_ras_n), + .D2(soc_a7ddrphy_dfi_p0_ras_n), + .D3(soc_a7ddrphy_dfi_p1_ras_n), + .D4(soc_a7ddrphy_dfi_p1_ras_n), + .D5(soc_a7ddrphy_dfi_p2_ras_n), + .D6(soc_a7ddrphy_dfi_p2_ras_n), + .D7(soc_a7ddrphy_dfi_p3_ras_n), + .D8(soc_a7ddrphy_dfi_p3_ras_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ras_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_21 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_cas_n), + .D2(soc_a7ddrphy_dfi_p0_cas_n), + .D3(soc_a7ddrphy_dfi_p1_cas_n), + .D4(soc_a7ddrphy_dfi_p1_cas_n), + .D5(soc_a7ddrphy_dfi_p2_cas_n), + .D6(soc_a7ddrphy_dfi_p2_cas_n), + .D7(soc_a7ddrphy_dfi_p3_cas_n), + .D8(soc_a7ddrphy_dfi_p3_cas_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_cas_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_22 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_we_n), + .D2(soc_a7ddrphy_dfi_p0_we_n), + .D3(soc_a7ddrphy_dfi_p1_we_n), + .D4(soc_a7ddrphy_dfi_p1_we_n), + .D5(soc_a7ddrphy_dfi_p2_we_n), + .D6(soc_a7ddrphy_dfi_p2_we_n), + .D7(soc_a7ddrphy_dfi_p3_we_n), + .D8(soc_a7ddrphy_dfi_p3_we_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_we_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_23 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_cke), + .D2(soc_a7ddrphy_dfi_p0_cke), + .D3(soc_a7ddrphy_dfi_p1_cke), + .D4(soc_a7ddrphy_dfi_p1_cke), + .D5(soc_a7ddrphy_dfi_p2_cke), + .D6(soc_a7ddrphy_dfi_p2_cke), + .D7(soc_a7ddrphy_dfi_p3_cke), + .D8(soc_a7ddrphy_dfi_p3_cke), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_cke) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_24 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_odt), + .D2(soc_a7ddrphy_dfi_p0_odt), + .D3(soc_a7ddrphy_dfi_p1_odt), + .D4(soc_a7ddrphy_dfi_p1_odt), + .D5(soc_a7ddrphy_dfi_p2_odt), + .D6(soc_a7ddrphy_dfi_p2_odt), + .D7(soc_a7ddrphy_dfi_p3_odt), + .D8(soc_a7ddrphy_dfi_p3_odt), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_odt) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_25 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_reset_n), + .D2(soc_a7ddrphy_dfi_p0_reset_n), + .D3(soc_a7ddrphy_dfi_p1_reset_n), + .D4(soc_a7ddrphy_dfi_p1_reset_n), + .D5(soc_a7ddrphy_dfi_p2_reset_n), + .D6(soc_a7ddrphy_dfi_p2_reset_n), + .D7(soc_a7ddrphy_dfi_p3_reset_n), + .D8(soc_a7ddrphy_dfi_p3_reset_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_reset_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_26 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_cs_n), + .D2(soc_a7ddrphy_dfi_p0_cs_n), + .D3(soc_a7ddrphy_dfi_p1_cs_n), + .D4(soc_a7ddrphy_dfi_p1_cs_n), + .D5(soc_a7ddrphy_dfi_p2_cs_n), + .D6(soc_a7ddrphy_dfi_p2_cs_n), + .D7(soc_a7ddrphy_dfi_p3_cs_n), + .D8(soc_a7ddrphy_dfi_p3_cs_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_cs_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_27 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]), + .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]), + .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]), + .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]), + .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]), + .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]), + .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]), + .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_dm[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_28 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]), + .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]), + .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]), + .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]), + .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]), + .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]), + .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]), + .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_dm[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_29 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dqspattern_o1[0]), + .D2(soc_a7ddrphy_dqspattern_o1[1]), + .D3(soc_a7ddrphy_dqspattern_o1[2]), + .D4(soc_a7ddrphy_dqspattern_o1[3]), + .D5(soc_a7ddrphy_dqspattern_o1[4]), + .D6(soc_a7ddrphy_dqspattern_o1[5]), + .D7(soc_a7ddrphy_dqspattern_o1[6]), + .D8(soc_a7ddrphy_dqspattern_o1[7]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dqs_oe_delayed)), + .TCE(1'd1), + .OFB(soc_a7ddrphy0), + .OQ(soc_a7ddrphy_dqs_o_no_delay0), + .TQ(soc_a7ddrphy_dqs_t0) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("FIXED"), + .IDELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2 ( + .IDATAIN(soc_a7ddrphy_dqs_i[0]), + .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0]) +); + +IOBUFDS IOBUFDS( + .I(soc_a7ddrphy_dqs_o_no_delay0), + .T(soc_a7ddrphy_dqs_t0), + .IO(ddram_dqs_p[0]), + .IOB(ddram_dqs_n[0]), + .O(soc_a7ddrphy_dqs_i[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_30 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dqspattern_o1[0]), + .D2(soc_a7ddrphy_dqspattern_o1[1]), + .D3(soc_a7ddrphy_dqspattern_o1[2]), + .D4(soc_a7ddrphy_dqspattern_o1[3]), + .D5(soc_a7ddrphy_dqspattern_o1[4]), + .D6(soc_a7ddrphy_dqspattern_o1[5]), + .D7(soc_a7ddrphy_dqspattern_o1[6]), + .D8(soc_a7ddrphy_dqspattern_o1[7]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dqs_oe_delayed)), + .TCE(1'd1), + .OFB(soc_a7ddrphy1), + .OQ(soc_a7ddrphy_dqs_o_no_delay1), + .TQ(soc_a7ddrphy_dqs_t1) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("FIXED"), + .IDELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_1 ( + .IDATAIN(soc_a7ddrphy_dqs_i[1]), + .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1]) +); + +IOBUFDS IOBUFDS_1( + .I(soc_a7ddrphy_dqs_o_no_delay1), + .T(soc_a7ddrphy_dqs_t1), + .IO(ddram_dqs_p[1]), + .IOB(ddram_dqs_n[1]), + .O(soc_a7ddrphy_dqs_i[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_31 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[0]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[16]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[0]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[16]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[0]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[16]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[0]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[16]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay0), + .TQ(soc_a7ddrphy_dq_t0) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed0), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data0[7]), + .Q2(soc_a7ddrphy_dq_i_data0[6]), + .Q3(soc_a7ddrphy_dq_i_data0[5]), + .Q4(soc_a7ddrphy_dq_i_data0[4]), + .Q5(soc_a7ddrphy_dq_i_data0[3]), + .Q6(soc_a7ddrphy_dq_i_data0[2]), + .Q7(soc_a7ddrphy_dq_i_data0[1]), + .Q8(soc_a7ddrphy_dq_i_data0[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_2 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay0), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed0) +); + +IOBUF IOBUF( + .I(soc_a7ddrphy_dq_o_nodelay0), + .T(soc_a7ddrphy_dq_t0), + .IO(ddram_dq[0]), + .O(soc_a7ddrphy_dq_i_nodelay0) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_32 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[1]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[17]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[1]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[17]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[1]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[17]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[1]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[17]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay1), + .TQ(soc_a7ddrphy_dq_t1) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_1 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed1), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data1[7]), + .Q2(soc_a7ddrphy_dq_i_data1[6]), + .Q3(soc_a7ddrphy_dq_i_data1[5]), + .Q4(soc_a7ddrphy_dq_i_data1[4]), + .Q5(soc_a7ddrphy_dq_i_data1[3]), + .Q6(soc_a7ddrphy_dq_i_data1[2]), + .Q7(soc_a7ddrphy_dq_i_data1[1]), + .Q8(soc_a7ddrphy_dq_i_data1[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_3 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay1), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed1) +); + +IOBUF IOBUF_1( + .I(soc_a7ddrphy_dq_o_nodelay1), + .T(soc_a7ddrphy_dq_t1), + .IO(ddram_dq[1]), + .O(soc_a7ddrphy_dq_i_nodelay1) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_33 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[2]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[18]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[2]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[18]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[2]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[18]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[2]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[18]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay2), + .TQ(soc_a7ddrphy_dq_t2) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed2), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data2[7]), + .Q2(soc_a7ddrphy_dq_i_data2[6]), + .Q3(soc_a7ddrphy_dq_i_data2[5]), + .Q4(soc_a7ddrphy_dq_i_data2[4]), + .Q5(soc_a7ddrphy_dq_i_data2[3]), + .Q6(soc_a7ddrphy_dq_i_data2[2]), + .Q7(soc_a7ddrphy_dq_i_data2[1]), + .Q8(soc_a7ddrphy_dq_i_data2[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_4 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay2), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed2) +); + +IOBUF IOBUF_2( + .I(soc_a7ddrphy_dq_o_nodelay2), + .T(soc_a7ddrphy_dq_t2), + .IO(ddram_dq[2]), + .O(soc_a7ddrphy_dq_i_nodelay2) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_34 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[3]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[19]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[3]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[19]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[3]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[19]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[3]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[19]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay3), + .TQ(soc_a7ddrphy_dq_t3) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_3 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed3), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data3[7]), + .Q2(soc_a7ddrphy_dq_i_data3[6]), + .Q3(soc_a7ddrphy_dq_i_data3[5]), + .Q4(soc_a7ddrphy_dq_i_data3[4]), + .Q5(soc_a7ddrphy_dq_i_data3[3]), + .Q6(soc_a7ddrphy_dq_i_data3[2]), + .Q7(soc_a7ddrphy_dq_i_data3[1]), + .Q8(soc_a7ddrphy_dq_i_data3[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_5 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay3), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed3) +); + +IOBUF IOBUF_3( + .I(soc_a7ddrphy_dq_o_nodelay3), + .T(soc_a7ddrphy_dq_t3), + .IO(ddram_dq[3]), + .O(soc_a7ddrphy_dq_i_nodelay3) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_35 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[4]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[20]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[4]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[20]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[4]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[20]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[4]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[20]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay4), + .TQ(soc_a7ddrphy_dq_t4) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_4 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed4), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data4[7]), + .Q2(soc_a7ddrphy_dq_i_data4[6]), + .Q3(soc_a7ddrphy_dq_i_data4[5]), + .Q4(soc_a7ddrphy_dq_i_data4[4]), + .Q5(soc_a7ddrphy_dq_i_data4[3]), + .Q6(soc_a7ddrphy_dq_i_data4[2]), + .Q7(soc_a7ddrphy_dq_i_data4[1]), + .Q8(soc_a7ddrphy_dq_i_data4[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_6 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay4), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed4) +); + +IOBUF IOBUF_4( + .I(soc_a7ddrphy_dq_o_nodelay4), + .T(soc_a7ddrphy_dq_t4), + .IO(ddram_dq[4]), + .O(soc_a7ddrphy_dq_i_nodelay4) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_36 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[5]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[21]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[5]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[21]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[5]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[21]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[5]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[21]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay5), + .TQ(soc_a7ddrphy_dq_t5) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_5 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed5), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data5[7]), + .Q2(soc_a7ddrphy_dq_i_data5[6]), + .Q3(soc_a7ddrphy_dq_i_data5[5]), + .Q4(soc_a7ddrphy_dq_i_data5[4]), + .Q5(soc_a7ddrphy_dq_i_data5[3]), + .Q6(soc_a7ddrphy_dq_i_data5[2]), + .Q7(soc_a7ddrphy_dq_i_data5[1]), + .Q8(soc_a7ddrphy_dq_i_data5[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_7 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay5), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed5) +); + +IOBUF IOBUF_5( + .I(soc_a7ddrphy_dq_o_nodelay5), + .T(soc_a7ddrphy_dq_t5), + .IO(ddram_dq[5]), + .O(soc_a7ddrphy_dq_i_nodelay5) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_37 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[6]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[22]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[6]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[22]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[6]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[22]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[6]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[22]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay6), + .TQ(soc_a7ddrphy_dq_t6) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_6 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed6), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data6[7]), + .Q2(soc_a7ddrphy_dq_i_data6[6]), + .Q3(soc_a7ddrphy_dq_i_data6[5]), + .Q4(soc_a7ddrphy_dq_i_data6[4]), + .Q5(soc_a7ddrphy_dq_i_data6[3]), + .Q6(soc_a7ddrphy_dq_i_data6[2]), + .Q7(soc_a7ddrphy_dq_i_data6[1]), + .Q8(soc_a7ddrphy_dq_i_data6[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_8 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay6), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed6) +); + +IOBUF IOBUF_6( + .I(soc_a7ddrphy_dq_o_nodelay6), + .T(soc_a7ddrphy_dq_t6), + .IO(ddram_dq[6]), + .O(soc_a7ddrphy_dq_i_nodelay6) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_38 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[7]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[23]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[7]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[23]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[7]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[23]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[7]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[23]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay7), + .TQ(soc_a7ddrphy_dq_t7) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_7 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed7), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data7[7]), + .Q2(soc_a7ddrphy_dq_i_data7[6]), + .Q3(soc_a7ddrphy_dq_i_data7[5]), + .Q4(soc_a7ddrphy_dq_i_data7[4]), + .Q5(soc_a7ddrphy_dq_i_data7[3]), + .Q6(soc_a7ddrphy_dq_i_data7[2]), + .Q7(soc_a7ddrphy_dq_i_data7[1]), + .Q8(soc_a7ddrphy_dq_i_data7[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_9 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay7), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed7) +); + +IOBUF IOBUF_7( + .I(soc_a7ddrphy_dq_o_nodelay7), + .T(soc_a7ddrphy_dq_t7), + .IO(ddram_dq[7]), + .O(soc_a7ddrphy_dq_i_nodelay7) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_39 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[8]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[24]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[8]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[24]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[8]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[24]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[8]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[24]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay8), + .TQ(soc_a7ddrphy_dq_t8) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_8 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed8), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data8[7]), + .Q2(soc_a7ddrphy_dq_i_data8[6]), + .Q3(soc_a7ddrphy_dq_i_data8[5]), + .Q4(soc_a7ddrphy_dq_i_data8[4]), + .Q5(soc_a7ddrphy_dq_i_data8[3]), + .Q6(soc_a7ddrphy_dq_i_data8[2]), + .Q7(soc_a7ddrphy_dq_i_data8[1]), + .Q8(soc_a7ddrphy_dq_i_data8[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_10 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay8), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed8) +); + +IOBUF IOBUF_8( + .I(soc_a7ddrphy_dq_o_nodelay8), + .T(soc_a7ddrphy_dq_t8), + .IO(ddram_dq[8]), + .O(soc_a7ddrphy_dq_i_nodelay8) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_40 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[9]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[25]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[9]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[25]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[9]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[25]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[9]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[25]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay9), + .TQ(soc_a7ddrphy_dq_t9) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_9 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed9), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data9[7]), + .Q2(soc_a7ddrphy_dq_i_data9[6]), + .Q3(soc_a7ddrphy_dq_i_data9[5]), + .Q4(soc_a7ddrphy_dq_i_data9[4]), + .Q5(soc_a7ddrphy_dq_i_data9[3]), + .Q6(soc_a7ddrphy_dq_i_data9[2]), + .Q7(soc_a7ddrphy_dq_i_data9[1]), + .Q8(soc_a7ddrphy_dq_i_data9[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_11 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay9), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed9) +); + +IOBUF IOBUF_9( + .I(soc_a7ddrphy_dq_o_nodelay9), + .T(soc_a7ddrphy_dq_t9), + .IO(ddram_dq[9]), + .O(soc_a7ddrphy_dq_i_nodelay9) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_41 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[10]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[26]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[10]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[26]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[10]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[26]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[10]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[26]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay10), + .TQ(soc_a7ddrphy_dq_t10) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_10 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed10), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data10[7]), + .Q2(soc_a7ddrphy_dq_i_data10[6]), + .Q3(soc_a7ddrphy_dq_i_data10[5]), + .Q4(soc_a7ddrphy_dq_i_data10[4]), + .Q5(soc_a7ddrphy_dq_i_data10[3]), + .Q6(soc_a7ddrphy_dq_i_data10[2]), + .Q7(soc_a7ddrphy_dq_i_data10[1]), + .Q8(soc_a7ddrphy_dq_i_data10[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_12 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay10), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed10) +); + +IOBUF IOBUF_10( + .I(soc_a7ddrphy_dq_o_nodelay10), + .T(soc_a7ddrphy_dq_t10), + .IO(ddram_dq[10]), + .O(soc_a7ddrphy_dq_i_nodelay10) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_42 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[11]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[27]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[11]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[27]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[11]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[27]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[11]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[27]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay11), + .TQ(soc_a7ddrphy_dq_t11) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_11 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed11), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data11[7]), + .Q2(soc_a7ddrphy_dq_i_data11[6]), + .Q3(soc_a7ddrphy_dq_i_data11[5]), + .Q4(soc_a7ddrphy_dq_i_data11[4]), + .Q5(soc_a7ddrphy_dq_i_data11[3]), + .Q6(soc_a7ddrphy_dq_i_data11[2]), + .Q7(soc_a7ddrphy_dq_i_data11[1]), + .Q8(soc_a7ddrphy_dq_i_data11[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_13 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay11), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed11) +); + +IOBUF IOBUF_11( + .I(soc_a7ddrphy_dq_o_nodelay11), + .T(soc_a7ddrphy_dq_t11), + .IO(ddram_dq[11]), + .O(soc_a7ddrphy_dq_i_nodelay11) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_43 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[12]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[28]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[12]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[28]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[12]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[28]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[12]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[28]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay12), + .TQ(soc_a7ddrphy_dq_t12) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_12 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed12), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data12[7]), + .Q2(soc_a7ddrphy_dq_i_data12[6]), + .Q3(soc_a7ddrphy_dq_i_data12[5]), + .Q4(soc_a7ddrphy_dq_i_data12[4]), + .Q5(soc_a7ddrphy_dq_i_data12[3]), + .Q6(soc_a7ddrphy_dq_i_data12[2]), + .Q7(soc_a7ddrphy_dq_i_data12[1]), + .Q8(soc_a7ddrphy_dq_i_data12[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_14 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay12), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed12) +); + +IOBUF IOBUF_12( + .I(soc_a7ddrphy_dq_o_nodelay12), + .T(soc_a7ddrphy_dq_t12), + .IO(ddram_dq[12]), + .O(soc_a7ddrphy_dq_i_nodelay12) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_44 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[13]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[29]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[13]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[29]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[13]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[29]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[13]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[29]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay13), + .TQ(soc_a7ddrphy_dq_t13) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_13 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed13), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data13[7]), + .Q2(soc_a7ddrphy_dq_i_data13[6]), + .Q3(soc_a7ddrphy_dq_i_data13[5]), + .Q4(soc_a7ddrphy_dq_i_data13[4]), + .Q5(soc_a7ddrphy_dq_i_data13[3]), + .Q6(soc_a7ddrphy_dq_i_data13[2]), + .Q7(soc_a7ddrphy_dq_i_data13[1]), + .Q8(soc_a7ddrphy_dq_i_data13[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_15 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay13), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed13) +); + +IOBUF IOBUF_13( + .I(soc_a7ddrphy_dq_o_nodelay13), + .T(soc_a7ddrphy_dq_t13), + .IO(ddram_dq[13]), + .O(soc_a7ddrphy_dq_i_nodelay13) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_45 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[14]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[30]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[14]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[30]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[14]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[30]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[14]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[30]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay14), + .TQ(soc_a7ddrphy_dq_t14) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_14 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed14), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data14[7]), + .Q2(soc_a7ddrphy_dq_i_data14[6]), + .Q3(soc_a7ddrphy_dq_i_data14[5]), + .Q4(soc_a7ddrphy_dq_i_data14[4]), + .Q5(soc_a7ddrphy_dq_i_data14[3]), + .Q6(soc_a7ddrphy_dq_i_data14[2]), + .Q7(soc_a7ddrphy_dq_i_data14[1]), + .Q8(soc_a7ddrphy_dq_i_data14[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_16 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay14), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed14) +); + +IOBUF IOBUF_14( + .I(soc_a7ddrphy_dq_o_nodelay14), + .T(soc_a7ddrphy_dq_t14), + .IO(ddram_dq[14]), + .O(soc_a7ddrphy_dq_i_nodelay14) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_46 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[15]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[31]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[15]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[31]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[15]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[31]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[15]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[31]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay15), + .TQ(soc_a7ddrphy_dq_t15) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_15 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed15), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data15[7]), + .Q2(soc_a7ddrphy_dq_i_data15[6]), + .Q3(soc_a7ddrphy_dq_i_data15[5]), + .Q4(soc_a7ddrphy_dq_i_data15[4]), + .Q5(soc_a7ddrphy_dq_i_data15[3]), + .Q6(soc_a7ddrphy_dq_i_data15[2]), + .Q7(soc_a7ddrphy_dq_i_data15[1]), + .Q8(soc_a7ddrphy_dq_i_data15[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_17 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay15), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed15) +); + +IOBUF IOBUF_15( + .I(soc_a7ddrphy_dq_o_nodelay15), + .T(soc_a7ddrphy_dq_t15), + .IO(ddram_dq[15]), + .O(soc_a7ddrphy_dq_i_nodelay15) +); + +reg [25:0] storage[0:15]; +reg [25:0] memdat; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +reg [25:0] storage_1[0:15]; +reg [25:0] memdat_1; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_1 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +reg [25:0] storage_2[0:15]; +reg [25:0] memdat_2; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_2 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +reg [25:0] storage_3[0:15]; +reg [25:0] memdat_3; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_3 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +reg [25:0] storage_4[0:15]; +reg [25:0] memdat_4; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_4 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +reg [25:0] storage_5[0:15]; +reg [25:0] memdat_5; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +reg [25:0] storage_6[0:15]; +reg [25:0] memdat_6; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +reg [25:0] storage_7[0:15]; +reg [25:0] memdat_7; +always @(posedge sys_clk) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + +PLLE2_ADV #( + .CLKFBOUT_MULT(4'd8), + .CLKIN1_PERIOD(5.0), + .CLKOUT0_DIVIDE(4'd8), + .CLKOUT0_PHASE(1'd0), + .CLKOUT1_DIVIDE(5'd16), + .CLKOUT1_PHASE(1'd0), + .CLKOUT2_DIVIDE(3'd4), + .CLKOUT2_PHASE(1'd0), + .CLKOUT3_DIVIDE(3'd4), + .CLKOUT3_PHASE(7'd90), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01), + .STARTUP_WAIT("FALSE") +) PLLE2_ADV ( + .CLKFBIN(vns_pll_fb), + .CLKIN1(soc_clkin), + .RST(soc_reset), + .CLKFBOUT(vns_pll_fb), + .CLKOUT0(soc_clkout0), + .CLKOUT1(soc_clkout1), + .CLKOUT2(soc_clkout2), + .CLKOUT3(soc_clkout3), + .LOCKED(soc_locked) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE ( + .C(iodelay_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_1 ( + .C(iodelay_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .Q(iodelay_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_2 ( + .C(sys_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl1), + .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_3 ( + .C(sys_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl1), + .Q(sys_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_4 ( + .C(sys4x_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl2), + .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_5 ( + .C(sys4x_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl2), + .Q(vns_xilinxasyncresetsynchronizerimpl2_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_6 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl3), + .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_7 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl3), + .Q(vns_xilinxasyncresetsynchronizerimpl3_expr) +); + +endmodule diff --git a/microwatt.core b/microwatt.core index 15786fe..8bb5103 100644 --- a/microwatt.core +++ b/microwatt.core @@ -85,6 +85,12 @@ filesets: - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008} + acorn_cle_215: + files: + - fpga/acorn-cle-215.xdc : {file_type : xdc} + - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} + - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008} + arty_a7: files: - fpga/arty_a7.xdc : {file_type : xdc} @@ -122,6 +128,39 @@ targets: vivado: {part : xc7a100tcsg324-1} toplevel : toplevel + acorn-cle-215-nodram: + default_tool: vivado + filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific] + parameters : + - memory_size + - ram_init_file + - clk_input + - clk_frequency + - disable_flatten_core + - spi_flash_offset=10485760 + - log_length=2048 + - uart_is_16550 + tools: + vivado: {part : xc7a200tsbg484-2} + toplevel : toplevel + + acorn-cle-215: + default_tool: vivado + filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific] + parameters : + - memory_size + - ram_init_file + - use_litedram=true + - disable_flatten_core + - no_bram + - spi_flash_offset=10485760 + - log_length=2048 + - uart_is_16550 + generate: [litedram_acorn_cle_215] + tools: + vivado: {part : xc7a200tsbg484-2} + toplevel : toplevel + nexys_video-nodram: default_tool: vivado filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific] @@ -262,6 +301,10 @@ generate: generator: litedram_gen parameters: {board : nexys-video} + litedram_acorn_cle_215: + generator: litedram_gen + parameters: {board : acorn-cle-215} + parameters: memory_size: datatype : int From 679c547e5fb6cc9e35a06cc3872c193daed83e1f Mon Sep 17 00:00:00 2001 From: Boris Shingarov Date: Sun, 12 Jul 2020 14:07:21 -0400 Subject: [PATCH 2/2] fpga: Add support for Genesys2 Signed-off-by: Boris Shingarov --- fpga/genesys2.xdc | 463 ++++ fpga/top-genesys2.vhdl | 322 +++ litedram/gen-src/genesys2.yml | 2 +- litedram/generated/genesys2/litedram_core.v | 2144 +++++++++---------- microwatt.core | 44 + 5 files changed, 1902 insertions(+), 1073 deletions(-) create mode 100644 fpga/genesys2.xdc create mode 100644 fpga/top-genesys2.vhdl diff --git a/fpga/genesys2.xdc b/fpga/genesys2.xdc new file mode 100644 index 0000000..826e5f4 --- /dev/null +++ b/fpga/genesys2.xdc @@ -0,0 +1,463 @@ +#### Genesys-2 Rev.H + +## Clock & Reset +set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { clk200_n }] +set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { clk200_p }] +create_clock -period 5.000 -name tc_clk100_p -waveform {0.000 2.500} [get_ports clk200_p] +create_clock -period 5.000 -name tc_clk100_n -waveform {2.500 5.000} [get_ports clk200_n] + +set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }] + +## UART +set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }] +set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }] + +## LEDs +set_property -dict { PACKAGE_PIN T28 IOSTANDARD LVCMOS33 } [get_ports { led0 }] +set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { led1 }] +set_property -dict { PACKAGE_PIN U30 IOSTANDARD LVCMOS33 } [get_ports { led2 }] +set_property -dict { PACKAGE_PIN U29 IOSTANDARD LVCMOS33 } [get_ports { led3 }] + +## QSPI +set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_cs_n }] +set_property -dict { PACKAGE_PIN P24 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_mosi }] +set_property -dict { PACKAGE_PIN R25 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_miso }] +set_property -dict { PACKAGE_PIN R20 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n }] +set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }] + + +## DRAM + +# ddram:0.a +set_property LOC AC12 [get_ports {ddram_a[0]}] +set_property SLEW FAST [get_ports {ddram_a[0]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}] + +# ddram:0.a +set_property LOC AE8 [get_ports {ddram_a[1]}] +set_property SLEW FAST [get_ports {ddram_a[1]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}] + +# ddram:0.a +set_property LOC AD8 [get_ports {ddram_a[2]}] +set_property SLEW FAST [get_ports {ddram_a[2]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}] + +# ddram:0.a +set_property LOC AC10 [get_ports {ddram_a[3]}] +set_property SLEW FAST [get_ports {ddram_a[3]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}] + +# ddram:0.a +set_property LOC AD9 [get_ports {ddram_a[4]}] +set_property SLEW FAST [get_ports {ddram_a[4]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}] + +# ddram:0.a +set_property LOC AA13 [get_ports {ddram_a[5]}] +set_property SLEW FAST [get_ports {ddram_a[5]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}] + +# ddram:0.a +set_property LOC AA10 [get_ports {ddram_a[6]}] +set_property SLEW FAST [get_ports {ddram_a[6]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}] + +# ddram:0.a +set_property LOC AA11 [get_ports {ddram_a[7]}] +set_property SLEW FAST [get_ports {ddram_a[7]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}] + +# ddram:0.a +set_property LOC Y10 [get_ports {ddram_a[8]}] +set_property SLEW FAST [get_ports {ddram_a[8]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}] + +# ddram:0.a +set_property LOC Y11 [get_ports {ddram_a[9]}] +set_property SLEW FAST [get_ports {ddram_a[9]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}] + +# ddram:0.a +set_property LOC AB8 [get_ports {ddram_a[10]}] +set_property SLEW FAST [get_ports {ddram_a[10]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}] + +# ddram:0.a +set_property LOC AA8 [get_ports {ddram_a[11]}] +set_property SLEW FAST [get_ports {ddram_a[11]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}] + +# ddram:0.a +set_property LOC AB12 [get_ports {ddram_a[12]}] +set_property SLEW FAST [get_ports {ddram_a[12]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}] + +# ddram:0.a +set_property LOC AA12 [get_ports {ddram_a[13]}] +set_property SLEW FAST [get_ports {ddram_a[13]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}] + +# ddram:0.a +set_property LOC AH9 [get_ports {ddram_a[14]}] +set_property SLEW FAST [get_ports {ddram_a[14]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_a[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}] + +# ddram:0.ba +set_property LOC AE9 [get_ports {ddram_ba[0]}] +set_property SLEW FAST [get_ports {ddram_ba[0]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_ba[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}] + +# ddram:0.ba +set_property LOC AB10 [get_ports {ddram_ba[1]}] +set_property SLEW FAST [get_ports {ddram_ba[1]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_ba[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}] + +# ddram:0.ba +set_property LOC AC11 [get_ports {ddram_ba[2]}] +set_property SLEW FAST [get_ports {ddram_ba[2]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_ba[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}] + +# ddram:0.ras_n +set_property LOC AE11 [get_ports {ddram_ras_n}] +set_property SLEW FAST [get_ports {ddram_ras_n}] +set_property VCCAUX_IO HIGH [get_ports {ddram_ras_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}] + +# ddram:0.cas_n +set_property LOC AF11 [get_ports {ddram_cas_n}] +set_property SLEW FAST [get_ports {ddram_cas_n}] +set_property VCCAUX_IO HIGH [get_ports {ddram_cas_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}] + +# ddram:0.we_n +set_property LOC AG13 [get_ports {ddram_we_n}] +set_property SLEW FAST [get_ports {ddram_we_n}] +set_property VCCAUX_IO HIGH [get_ports {ddram_we_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}] + +# ddram:0.cs_n +set_property LOC AH12 [get_ports {ddram_cs_n}] +set_property SLEW FAST [get_ports {ddram_cs_n}] +set_property VCCAUX_IO HIGH [get_ports {ddram_cs_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_cs_n}] + +# ddram:0.dm +set_property LOC AD4 [get_ports {ddram_dm[0]}] +set_property SLEW FAST [get_ports {ddram_dm[0]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dm[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[0]}] + +# ddram:0.dm +set_property LOC AF3 [get_ports {ddram_dm[1]}] +set_property SLEW FAST [get_ports {ddram_dm[1]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dm[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[1]}] + +# ddram:0.dm +set_property LOC AH4 [get_ports {ddram_dm[2]}] +set_property SLEW FAST [get_ports {ddram_dm[2]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dm[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[2]}] + +# ddram:0.dm +set_property LOC AF8 [get_ports {ddram_dm[3]}] +set_property SLEW FAST [get_ports {ddram_dm[3]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dm[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[3]}] + +# ddram:0.dq +set_property LOC AD3 [get_ports {ddram_dq[0]}] +set_property SLEW FAST [get_ports {ddram_dq[0]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[0]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[0]}] + +# ddram:0.dq +set_property LOC AC2 [get_ports {ddram_dq[1]}] +set_property SLEW FAST [get_ports {ddram_dq[1]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[1]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[1]}] + +# ddram:0.dq +set_property LOC AC1 [get_ports {ddram_dq[2]}] +set_property SLEW FAST [get_ports {ddram_dq[2]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[2]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[2]}] + +# ddram:0.dq +set_property LOC AC5 [get_ports {ddram_dq[3]}] +set_property SLEW FAST [get_ports {ddram_dq[3]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[3]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[3]}] + +# ddram:0.dq +set_property LOC AC4 [get_ports {ddram_dq[4]}] +set_property SLEW FAST [get_ports {ddram_dq[4]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[4]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[4]}] + +# ddram:0.dq +set_property LOC AD6 [get_ports {ddram_dq[5]}] +set_property SLEW FAST [get_ports {ddram_dq[5]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[5]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[5]}] + +# ddram:0.dq +set_property LOC AE6 [get_ports {ddram_dq[6]}] +set_property SLEW FAST [get_ports {ddram_dq[6]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[6]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[6]}] + +# ddram:0.dq +set_property LOC AC7 [get_ports {ddram_dq[7]}] +set_property SLEW FAST [get_ports {ddram_dq[7]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[7]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[7]}] + +# ddram:0.dq +set_property LOC AF2 [get_ports {ddram_dq[8]}] +set_property SLEW FAST [get_ports {ddram_dq[8]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[8]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[8]}] + +# ddram:0.dq +set_property LOC AE1 [get_ports {ddram_dq[9]}] +set_property SLEW FAST [get_ports {ddram_dq[9]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[9]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[9]}] + +# ddram:0.dq +set_property LOC AF1 [get_ports {ddram_dq[10]}] +set_property SLEW FAST [get_ports {ddram_dq[10]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[10]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[10]}] + +# ddram:0.dq +set_property LOC AE4 [get_ports {ddram_dq[11]}] +set_property SLEW FAST [get_ports {ddram_dq[11]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[11]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[11]}] + +# ddram:0.dq +set_property LOC AE3 [get_ports {ddram_dq[12]}] +set_property SLEW FAST [get_ports {ddram_dq[12]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[12]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[12]}] + +# ddram:0.dq +set_property LOC AE5 [get_ports {ddram_dq[13]}] +set_property SLEW FAST [get_ports {ddram_dq[13]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[13]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[13]}] + +# ddram:0.dq +set_property LOC AF5 [get_ports {ddram_dq[14]}] +set_property SLEW FAST [get_ports {ddram_dq[14]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[14]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[14]}] + +# ddram:0.dq +set_property LOC AF6 [get_ports {ddram_dq[15]}] +set_property SLEW FAST [get_ports {ddram_dq[15]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[15]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[15]}] + +# ddram:0.dq +set_property LOC AJ4 [get_ports {ddram_dq[16]}] +set_property SLEW FAST [get_ports {ddram_dq[16]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[16]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[16]}] + +# ddram:0.dq +set_property LOC AH6 [get_ports {ddram_dq[17]}] +set_property SLEW FAST [get_ports {ddram_dq[17]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[17]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[17]}] + +# ddram:0.dq +set_property LOC AH5 [get_ports {ddram_dq[18]}] +set_property SLEW FAST [get_ports {ddram_dq[18]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[18]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[18]}] + +# ddram:0.dq +set_property LOC AH2 [get_ports {ddram_dq[19]}] +set_property SLEW FAST [get_ports {ddram_dq[19]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[19]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[19]}] + +# ddram:0.dq +set_property LOC AJ2 [get_ports {ddram_dq[20]}] +set_property SLEW FAST [get_ports {ddram_dq[20]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[20]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[20]}] + +# ddram:0.dq +set_property LOC AJ1 [get_ports {ddram_dq[21]}] +set_property SLEW FAST [get_ports {ddram_dq[21]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[21]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[21]}] + +# ddram:0.dq +set_property LOC AK1 [get_ports {ddram_dq[22]}] +set_property SLEW FAST [get_ports {ddram_dq[22]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[22]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[22]}] + +# ddram:0.dq +set_property LOC AJ3 [get_ports {ddram_dq[23]}] +set_property SLEW FAST [get_ports {ddram_dq[23]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[23]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[23]}] + +# ddram:0.dq +set_property LOC AF7 [get_ports {ddram_dq[24]}] +set_property SLEW FAST [get_ports {ddram_dq[24]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[24]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[24]}] + +# ddram:0.dq +set_property LOC AG7 [get_ports {ddram_dq[25]}] +set_property SLEW FAST [get_ports {ddram_dq[25]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[25]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[25]}] + +# ddram:0.dq +set_property LOC AJ6 [get_ports {ddram_dq[26]}] +set_property SLEW FAST [get_ports {ddram_dq[26]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[26]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[26]}] + +# ddram:0.dq +set_property LOC AK6 [get_ports {ddram_dq[27]}] +set_property SLEW FAST [get_ports {ddram_dq[27]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[27]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[27]}] + +# ddram:0.dq +set_property LOC AJ8 [get_ports {ddram_dq[28]}] +set_property SLEW FAST [get_ports {ddram_dq[28]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[28]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[28]}] + +# ddram:0.dq +set_property LOC AK8 [get_ports {ddram_dq[29]}] +set_property SLEW FAST [get_ports {ddram_dq[29]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[29]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[29]}] + +# ddram:0.dq +set_property LOC AK5 [get_ports {ddram_dq[30]}] +set_property SLEW FAST [get_ports {ddram_dq[30]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[30]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[30]}] + +# ddram:0.dq +set_property LOC AK4 [get_ports {ddram_dq[31]}] +set_property SLEW FAST [get_ports {ddram_dq[31]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dq[31]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[31]}] + +# ddram:0.dqs_p +set_property LOC AD2 [get_ports {ddram_dqs_p[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[0]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}] + +# ddram:0.dqs_p +set_property LOC AG4 [get_ports {ddram_dqs_p[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[1]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}] + +# ddram:0.dqs_p +set_property LOC AG2 [get_ports {ddram_dqs_p[2]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[2]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_p[2]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[2]}] + +# ddram:0.dqs_p +set_property LOC AH7 [get_ports {ddram_dqs_p[3]}] +set_property SLEW FAST [get_ports {ddram_dqs_p[3]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_p[3]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[3]}] + +# ddram:0.dqs_n +set_property LOC AD1 [get_ports {ddram_dqs_n[0]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[0]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}] + +# ddram:0.dqs_n +set_property LOC AG3 [get_ports {ddram_dqs_n[1]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[1]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}] + +# ddram:0.dqs_n +set_property LOC AH1 [get_ports {ddram_dqs_n[2]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[2]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_n[2]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[2]}] + +# ddram:0.dqs_n +set_property LOC AJ7 [get_ports {ddram_dqs_n[3]}] +set_property SLEW FAST [get_ports {ddram_dqs_n[3]}] +set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_n[3]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[3]}] + +# ddram:0.clk_p +set_property LOC AB9 [get_ports {ddram_clk_p}] +set_property SLEW FAST [get_ports {ddram_clk_p}] +set_property VCCAUX_IO HIGH [get_ports {ddram_clk_p}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}] + +# ddram:0.clk_n +set_property LOC AC9 [get_ports {ddram_clk_n}] +set_property SLEW FAST [get_ports {ddram_clk_n}] +set_property VCCAUX_IO HIGH [get_ports {ddram_clk_n}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}] + +# ddram:0.cke +set_property LOC AJ9 [get_ports {ddram_cke}] +set_property SLEW FAST [get_ports {ddram_cke}] +set_property VCCAUX_IO HIGH [get_ports {ddram_cke}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}] + +# ddram:0.odt +set_property LOC AK9 [get_ports {ddram_odt}] +set_property SLEW FAST [get_ports {ddram_odt}] +set_property VCCAUX_IO HIGH [get_ports {ddram_odt}] +set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}] + +# ddram:0.reset_n +set_property LOC AG5 [get_ports {ddram_reset_n}] +set_property SLEW FAST [get_ports {ddram_reset_n}] +set_property VCCAUX_IO HIGH [get_ports {ddram_reset_n}] +set_property IOSTANDARD LVCMOS15 [get_ports {ddram_reset_n}] + + +set_property INTERNAL_VREF 0.750 [get_iobanks 34] + +# False path constraints +set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}] +set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] +set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]] diff --git a/fpga/top-genesys2.vhdl b/fpga/top-genesys2.vhdl new file mode 100644 index 0000000..fcd190f --- /dev/null +++ b/fpga/top-genesys2.vhdl @@ -0,0 +1,322 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +library work; +use work.wishbone_types.all; + +entity toplevel is + generic ( + MEMORY_SIZE : integer := 16384; + RAM_INIT_FILE : string := "firmware.hex"; + RESET_LOW : boolean := true; + CLK_FREQUENCY : positive := 100000000; + USE_LITEDRAM : boolean := false; + NO_BRAM : boolean := false; + DISABLE_FLATTEN_CORE : boolean := false; + SPI_FLASH_OFFSET : integer := 10485760; + SPI_FLASH_DEF_CKDV : natural := 1; + SPI_FLASH_DEF_QUAD : boolean := true; + LOG_LENGTH : natural := 2048; + UART_IS_16550 : boolean := true + ); + port( + clk200_p : in std_ulogic; + clk200_n : in std_ulogic; + ext_rst : in std_ulogic; + + -- UART0 signals: + uart_main_tx : out std_ulogic; + uart_main_rx : in std_ulogic; + + -- LEDs + led0 : out std_logic; + led1 : out std_logic; + led2 : out std_logic; + led3 : out std_logic; + + -- SPI + spi_flash_cs_n : out std_ulogic; + spi_flash_mosi : inout std_ulogic; + spi_flash_miso : inout std_ulogic; + spi_flash_wp_n : inout std_ulogic; + spi_flash_hold_n : inout std_ulogic; + + -- DRAM wires + ddram_a : out std_logic_vector(14 downto 0); + ddram_ba : out std_logic_vector(2 downto 0); + ddram_ras_n : out std_logic; + ddram_cas_n : out std_logic; + ddram_we_n : out std_logic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_logic_vector(3 downto 0); + ddram_dq : inout std_logic_vector(31 downto 0); + ddram_dqs_p : inout std_logic_vector(3 downto 0); + ddram_dqs_n : inout std_logic_vector(3 downto 0); + ddram_clk_p : out std_logic; + ddram_clk_n : out std_logic; + ddram_cke : out std_logic; + ddram_odt : out std_logic; + ddram_reset_n : out std_logic + ); +end entity toplevel; + +architecture behaviour of toplevel is + + -- Internal clock + signal ext_clk : std_ulogic; + + -- Reset signals: + signal soc_rst : std_ulogic; + signal pll_rst : std_ulogic; + + -- Internal clock signals: + signal system_clk : std_ulogic; + signal system_clk_locked : std_ulogic; + + -- DRAM main data wishbone connection + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + + -- DRAM control wishbone connection + signal wb_ext_io_in : wb_io_master_out; + signal wb_ext_io_out : wb_io_slave_out; + signal wb_ext_is_dram_csr : std_ulogic; + signal wb_ext_is_dram_init : std_ulogic; + + -- Control/status + signal core_alt_reset : std_ulogic; + + -- SPI flash + signal spi_sck : std_ulogic; + signal spi_cs_n : std_ulogic; + signal spi_sdat_o : std_ulogic_vector(3 downto 0); + signal spi_sdat_oe : std_ulogic_vector(3 downto 0); + signal spi_sdat_i : std_ulogic_vector(3 downto 0); + + -- Fixup various memory sizes based on generics + function get_bram_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return 0; + else + return MEMORY_SIZE; + end if; + end function; + + function get_payload_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return MEMORY_SIZE; + else + return 0; + end if; + end function; + + constant BRAM_SIZE : natural := get_bram_size; + constant PAYLOAD_SIZE : natural := get_payload_size; +begin + + -- Main SoC + soc0: entity work.soc + generic map( + MEMORY_SIZE => BRAM_SIZE, + RAM_INIT_FILE => RAM_INIT_FILE, + SIM => false, + CLK_FREQ => CLK_FREQUENCY, + HAS_DRAM => USE_LITEDRAM, + DRAM_SIZE => 1024 * 1024 * 1024, + DRAM_INIT_SIZE => PAYLOAD_SIZE, + DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE, + HAS_SPI_FLASH => true, + SPI_FLASH_DLINES => 4, + SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, + SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV, + SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD, + LOG_LENGTH => LOG_LENGTH, + UART0_IS_16550 => UART_IS_16550 + ) + port map ( + -- System signals + system_clk => system_clk, + rst => soc_rst, + + -- UART signals + uart0_txd => uart_main_tx, + uart0_rxd => uart_main_rx, + + -- SPI signals + spi_flash_sck => spi_sck, + spi_flash_cs_n => spi_cs_n, + spi_flash_sdat_o => spi_sdat_o, + spi_flash_sdat_oe => spi_sdat_oe, + spi_flash_sdat_i => spi_sdat_i, + + -- DRAM wishbone + wb_dram_in => wb_dram_in, + wb_dram_out => wb_dram_out, + wb_ext_io_in => wb_ext_io_in, + wb_ext_io_out => wb_ext_io_out, + wb_ext_is_dram_csr => wb_ext_is_dram_csr, + wb_ext_is_dram_init => wb_ext_is_dram_init, + alt_reset => core_alt_reset + ); + + -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2 + -- primitive of the FPGA as it's not a normal pin + -- + spi_flash_cs_n <= spi_cs_n; + spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z'; + spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z'; + spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z'; + spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z'; + spi_sdat_i(0) <= spi_flash_mosi; + spi_sdat_i(1) <= spi_flash_miso; + spi_sdat_i(2) <= spi_flash_wp_n; + spi_sdat_i(3) <= spi_flash_hold_n; + + STARTUPE2_INST: STARTUPE2 + port map ( + CLK => '0', + GSR => '0', + GTS => '0', + KEYCLEARB => '0', + PACK => '0', + USRCCLKO => spi_sck, + USRCCLKTS => '0', + USRDONEO => '1', + USRDONETS => '0' + ); + + clk200: IBUFDS + port map ( + i => clk200_p, + ib => clk200_n, + o => ext_clk + ); + + nodram: if not USE_LITEDRAM generate + signal ddram_clk_dummy : std_ulogic; + begin + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst, + pll_rst_out => pll_rst, + rst_out => soc_rst + ); + + clkgen: entity work.clock_generator + generic map( + CLK_INPUT_HZ => 200000000, + CLK_OUTPUT_HZ => CLK_FREQUENCY + ) + port map( + ext_clk => ext_clk, + pll_rst_in => pll_rst, + pll_clk_out => system_clk, + pll_locked_out => system_clk_locked + ); + + led0 <= soc_rst; + led1 <= pll_rst; + led2 <= not system_clk_locked; + led3 <= '0'; + core_alt_reset <= '0'; + + -- Vivado barfs on those differential signals if left + -- unconnected. So instanciate a diff. buffer and feed + -- it a constant '0'. + dummy_dram_clk: OBUFDS + port map ( + O => ddram_clk_p, + OB => ddram_clk_n, + I => ddram_clk_dummy + ); + ddram_clk_dummy <= '0'; + + end generate; + + has_dram: if USE_LITEDRAM generate + signal dram_init_done : std_ulogic; + signal dram_init_error : std_ulogic; + signal dram_sys_rst : std_ulogic; + begin + + -- Eventually dig out the frequency from the generator + -- but for now, assert it's 100Mhz + assert CLK_FREQUENCY = 100000000; + + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW, + PLL_RESET_BITS => 18, + SOC_RESET_BITS => 1 + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => '1', + ext_rst_in => ext_rst, + pll_rst_out => pll_rst, + rst_out => open + ); + + dram: entity work.litedram_wrapper + generic map( + DRAM_ABITS => 25, + DRAM_ALINES => 15, + DRAM_DLINES => 32, + DRAM_PORT_WIDTH => 256, + PAYLOAD_FILE => RAM_INIT_FILE, + PAYLOAD_SIZE => PAYLOAD_SIZE + ) + port map( + clk_in => ext_clk, + rst => pll_rst, + system_clk => system_clk, + system_reset => soc_rst, + core_alt_reset => core_alt_reset, + pll_locked => system_clk_locked, + + wb_in => wb_dram_in, + wb_out => wb_dram_out, + wb_ctrl_in => wb_ext_io_in, + wb_ctrl_out => wb_ext_io_out, + wb_ctrl_is_csr => wb_ext_is_dram_csr, + wb_ctrl_is_init => wb_ext_is_dram_init, + + init_done => dram_init_done, + init_error => dram_init_error, + + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => ddram_cs_n, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_dqs_n => ddram_dqs_n, + ddram_clk_p => ddram_clk_p, + ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + ddram_reset_n => ddram_reset_n + ); + + led0 <= soc_rst; + led1 <= pll_rst; + led2 <= not dram_init_done or dram_init_error; + led3 <= not dram_init_error; -- Make it blink ? + end generate; +end architecture behaviour; diff --git a/litedram/gen-src/genesys2.yml b/litedram/gen-src/genesys2.yml index 9f2108b..6cf8ac1 100644 --- a/litedram/gen-src/genesys2.yml +++ b/litedram/gen-src/genesys2.yml @@ -9,7 +9,7 @@ "memtype": "DDR3", # DRAM type # PHY ---------------------------------------------------------------------- - "cmd_latency": 0, # Command additional latency + "cmd_latency": 1, # Command additional latency "sdram_module": "MT41J256M16", # SDRAM modules of the board or SO-DIMM "sdram_module_nb": 4, # Number of byte groups "sdram_rank_nb": 1, # Number of ranks diff --git a/litedram/generated/genesys2/litedram_core.v b/litedram/generated/genesys2/litedram_core.v index a0f6e8a..2afd926 100644 --- a/litedram/generated/genesys2/litedram_core.v +++ b/litedram/generated/genesys2/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:33:24 +// Auto-generated by Migen (--------) & LiteX (2ec4604c) on 2020-08-06 07:16:18 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -2120,14 +2120,12 @@ end reg dummy_d_1; // synthesis translate_on always @(*) begin - soc_litedramcore_adr <= 14'd0; + soc_litedramcore_wishbone_ack <= 1'd0; case (vns_state) 1'd1: begin + soc_litedramcore_wishbone_ack <= 1'd1; end default: begin - if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - soc_litedramcore_adr <= soc_litedramcore_wishbone_adr; - end end endcase // synthesis translate_off @@ -2139,13 +2137,13 @@ end reg dummy_d_2; // synthesis translate_on always @(*) begin - soc_litedramcore_we <= 1'd0; + soc_litedramcore_adr <= 14'd0; case (vns_state) 1'd1: begin end default: begin if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin - soc_litedramcore_we <= (soc_litedramcore_wishbone_we & (soc_litedramcore_wishbone_sel != 1'd0)); + soc_litedramcore_adr <= soc_litedramcore_wishbone_adr; end end endcase @@ -2158,12 +2156,14 @@ end reg dummy_d_3; // synthesis translate_on always @(*) begin - soc_litedramcore_wishbone_ack <= 1'd0; + soc_litedramcore_we <= 1'd0; case (vns_state) 1'd1: begin - soc_litedramcore_wishbone_ack <= 1'd1; end default: begin + if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin + soc_litedramcore_we <= (soc_litedramcore_wishbone_we & (soc_litedramcore_wishbone_sel != 1'd0)); + end end endcase // synthesis translate_off @@ -2506,7 +2506,7 @@ assign soc_k7ddrphy_bitslip29_i = soc_k7ddrphy_dq_i_data29; assign soc_k7ddrphy_bitslip30_i = soc_k7ddrphy_dq_i_data30; assign soc_k7ddrphy_bitslip31_i = soc_k7ddrphy_dq_i_data31; assign soc_k7ddrphy_rddata_en = {soc_k7ddrphy_rddata_en_last, soc_k7ddrphy_dfi_p2_rddata_en}; -assign soc_k7ddrphy_wrdata_en = {soc_k7ddrphy_wrdata_en_last, soc_k7ddrphy_dfi_p3_wrdata_en}; +assign soc_k7ddrphy_wrdata_en = {soc_k7ddrphy_wrdata_en_last, soc_k7ddrphy_dfi_p2_wrdata_en}; assign soc_k7ddrphy_dq_oe = soc_k7ddrphy_wrdata_en[2]; // synthesis translate_off @@ -4601,11 +4601,11 @@ assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_v reg dummy_d_42; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_ras_n <= 1'd1; + soc_litedramcore_master_p0_address <= 15'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n; + soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address; end else begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n; + soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_42 = dummy_s; @@ -4616,10 +4616,11 @@ end reg dummy_d_43; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p1_rddata <= 64'd0; + soc_litedramcore_master_p0_bank <= 3'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata; + soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank; end else begin + soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_43 = dummy_s; @@ -4630,11 +4631,11 @@ end reg dummy_d_44; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_we_n <= 1'd1; + soc_litedramcore_master_p0_cas_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n; + soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n; end else begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n; + soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_44 = dummy_s; @@ -4645,10 +4646,11 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p1_rddata_valid <= 1'd0; + soc_litedramcore_master_p0_cs_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n; end else begin + soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -4659,11 +4661,11 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cke <= 1'd0; + soc_litedramcore_master_p0_ras_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke; + soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n; end else begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke; + soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -4674,11 +4676,10 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_odt <= 1'd0; + soc_litedramcore_slave_p0_rddata <= 64'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt; + soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata; end else begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -4689,11 +4690,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_reset_n <= 1'd0; + soc_litedramcore_master_p0_we_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n; + soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n; end else begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n; + soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -4704,11 +4705,10 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_act_n <= 1'd1; + soc_litedramcore_slave_p0_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n; + soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; end else begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -4719,11 +4719,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata <= 64'd0; + soc_litedramcore_master_p0_cke <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata; + soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke; end else begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata; + soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -4734,10 +4734,11 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_rddata <= 64'd0; + soc_litedramcore_master_p0_odt <= 1'd0; if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt; end else begin - soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata; + soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -4748,11 +4749,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata_en <= 1'd0; + soc_litedramcore_master_p0_reset_n <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en; + soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n; end else begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en; + soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -4763,10 +4764,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_rddata_valid <= 1'd0; + soc_litedramcore_master_p0_act_n <= 1'd1; if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n; end else begin - soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -4777,11 +4779,11 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_wrdata_mask <= 8'd0; + soc_litedramcore_master_p0_wrdata <= 64'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask; + soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata; end else begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask; + soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -4792,11 +4794,10 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_rddata_en <= 1'd0; + soc_litedramcore_inti_p1_rddata <= 64'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en; end else begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en; + soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -4807,11 +4808,11 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_address <= 15'd0; + soc_litedramcore_master_p0_wrdata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address; + soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en; end else begin - soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address; + soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -4822,11 +4823,10 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_bank <= 3'd0; + soc_litedramcore_inti_p1_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank; end else begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank; + soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_57 = dummy_s; @@ -4837,11 +4837,11 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cas_n <= 1'd1; + soc_litedramcore_master_p0_wrdata_mask <= 8'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n; + soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask; end else begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n; + soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -4852,11 +4852,11 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cs_n <= 1'd1; + soc_litedramcore_master_p0_rddata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n; + soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en; end else begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n; + soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_59 = dummy_s; @@ -4867,11 +4867,11 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_ras_n <= 1'd1; + soc_litedramcore_master_p1_address <= 15'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n; + soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address; end else begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n; + soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -4882,10 +4882,10 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p2_rddata <= 64'd0; + soc_litedramcore_inti_p0_rddata <= 64'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata; end else begin + soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_61 = dummy_s; @@ -4896,11 +4896,11 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_we_n <= 1'd1; + soc_litedramcore_master_p1_bank <= 3'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n; + soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank; end else begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n; + soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -4911,10 +4911,11 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p2_rddata_valid <= 1'd0; + soc_litedramcore_master_p1_cas_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n; end else begin + soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -4925,11 +4926,11 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_cke <= 1'd0; + soc_litedramcore_master_p1_cs_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke; + soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n; end else begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke; + soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -4940,11 +4941,11 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_odt <= 1'd0; + soc_litedramcore_master_p1_ras_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt; + soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n; end else begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt; + soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -4955,11 +4956,10 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_reset_n <= 1'd0; + soc_litedramcore_slave_p1_rddata <= 64'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n; + soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata; end else begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -4970,11 +4970,11 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_act_n <= 1'd1; + soc_litedramcore_master_p1_we_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n; + soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n; end else begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n; + soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -4985,11 +4985,10 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata <= 64'd0; + soc_litedramcore_slave_p1_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata; + soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; end else begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -5000,10 +4999,11 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_rddata <= 64'd0; + soc_litedramcore_master_p1_cke <= 1'd0; if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke; end else begin - soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata; + soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -5014,11 +5014,10 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata_en <= 1'd0; + soc_litedramcore_inti_p0_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en; end else begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en; + soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -5029,10 +5028,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_rddata_valid <= 1'd0; + soc_litedramcore_master_p1_odt <= 1'd0; if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt; end else begin - soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -5043,11 +5043,11 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_wrdata_mask <= 8'd0; + soc_litedramcore_master_p1_reset_n <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask; + soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n; end else begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask; + soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -5058,11 +5058,11 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p2_rddata_en <= 1'd0; + soc_litedramcore_master_p1_act_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en; + soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n; end else begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en; + soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -5073,11 +5073,11 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_address <= 15'd0; + soc_litedramcore_master_p1_wrdata <= 64'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address; + soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata; end else begin - soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address; + soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -5088,11 +5088,10 @@ end reg dummy_d_75; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_bank <= 3'd0; + soc_litedramcore_inti_p2_rddata <= 64'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank; end else begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank; + soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_75 = dummy_s; @@ -5103,11 +5102,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cas_n <= 1'd1; + soc_litedramcore_master_p1_wrdata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n; + soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en; end else begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n; + soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -5118,11 +5117,10 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cs_n <= 1'd1; + soc_litedramcore_inti_p2_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n; end else begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n; + soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_77 = dummy_s; @@ -5133,11 +5131,11 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_ras_n <= 1'd1; + soc_litedramcore_master_p1_wrdata_mask <= 8'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n; + soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask; end else begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n; + soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -5148,10 +5146,11 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p3_rddata <= 64'd0; + soc_litedramcore_master_p1_rddata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata; + soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en; end else begin + soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_79 = dummy_s; @@ -5162,11 +5161,11 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_we_n <= 1'd1; + soc_litedramcore_master_p2_address <= 15'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n; + soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address; end else begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n; + soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -5177,10 +5176,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p3_rddata_valid <= 1'd0; + soc_litedramcore_master_p2_bank <= 3'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank; end else begin + soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -5191,11 +5191,11 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_cke <= 1'd0; + soc_litedramcore_master_p2_cas_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke; + soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n; end else begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke; + soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -5206,11 +5206,11 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_odt <= 1'd0; + soc_litedramcore_master_p2_cs_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt; + soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n; end else begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt; + soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -5221,11 +5221,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_reset_n <= 1'd0; + soc_litedramcore_master_p2_ras_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n; + soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n; end else begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n; + soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -5236,11 +5236,10 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_act_n <= 1'd1; + soc_litedramcore_slave_p2_rddata <= 64'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n; + soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata; end else begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -5251,11 +5250,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata <= 64'd0; + soc_litedramcore_master_p2_we_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata; + soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n; end else begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata; + soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -5266,10 +5265,10 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_rddata <= 64'd0; + soc_litedramcore_slave_p2_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; end else begin - soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -5280,11 +5279,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata_en <= 1'd0; + soc_litedramcore_master_p2_cke <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en; + soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke; end else begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en; + soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -5295,10 +5294,11 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_rddata_valid <= 1'd0; + soc_litedramcore_master_p2_odt <= 1'd0; if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt; end else begin - soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; + soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -5309,11 +5309,11 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_wrdata_mask <= 8'd0; + soc_litedramcore_master_p2_reset_n <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask; + soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n; end else begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask; + soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -5324,11 +5324,11 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p3_rddata_en <= 1'd0; + soc_litedramcore_master_p2_act_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en; + soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n; end else begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en; + soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -5339,11 +5339,11 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_address <= 15'd0; + soc_litedramcore_master_p2_wrdata <= 64'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address; + soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata; end else begin - soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address; + soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -5354,11 +5354,10 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_bank <= 3'd0; + soc_litedramcore_inti_p3_rddata <= 64'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank; end else begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank; + soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_93 = dummy_s; @@ -5369,11 +5368,11 @@ end reg dummy_d_94; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cas_n <= 1'd1; + soc_litedramcore_master_p2_wrdata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n; + soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en; end else begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n; + soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_94 = dummy_s; @@ -5384,11 +5383,10 @@ end reg dummy_d_95; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cs_n <= 1'd1; + soc_litedramcore_inti_p3_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n; end else begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n; + soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_95 = dummy_s; @@ -5399,11 +5397,11 @@ end reg dummy_d_96; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_ras_n <= 1'd1; + soc_litedramcore_master_p2_wrdata_mask <= 8'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n; + soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask; end else begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n; + soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_96 = dummy_s; @@ -5414,10 +5412,11 @@ end reg dummy_d_97; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p0_rddata <= 64'd0; + soc_litedramcore_master_p2_rddata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata; + soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en; end else begin + soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_97 = dummy_s; @@ -5428,11 +5427,11 @@ end reg dummy_d_98; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_we_n <= 1'd1; + soc_litedramcore_master_p3_address <= 15'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n; + soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address; end else begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n; + soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_98 = dummy_s; @@ -5443,10 +5442,11 @@ end reg dummy_d_99; // synthesis translate_on always @(*) begin - soc_litedramcore_slave_p0_rddata_valid <= 1'd0; + soc_litedramcore_master_p3_bank <= 3'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; + soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank; end else begin + soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_99 = dummy_s; @@ -5457,11 +5457,11 @@ end reg dummy_d_100; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_cke <= 1'd0; + soc_litedramcore_master_p3_cas_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke; + soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n; end else begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke; + soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_100 = dummy_s; @@ -5472,11 +5472,11 @@ end reg dummy_d_101; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_odt <= 1'd0; + soc_litedramcore_master_p3_cs_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt; + soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n; end else begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt; + soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_101 = dummy_s; @@ -5487,11 +5487,11 @@ end reg dummy_d_102; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_reset_n <= 1'd0; + soc_litedramcore_master_p3_ras_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n; + soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n; end else begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n; + soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_102 = dummy_s; @@ -5502,11 +5502,10 @@ end reg dummy_d_103; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_act_n <= 1'd1; + soc_litedramcore_slave_p3_rddata <= 64'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n; + soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata; end else begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_103 = dummy_s; @@ -5517,11 +5516,11 @@ end reg dummy_d_104; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata <= 64'd0; + soc_litedramcore_master_p3_we_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata; + soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n; end else begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata; + soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_104 = dummy_s; @@ -5532,10 +5531,10 @@ end reg dummy_d_105; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_rddata <= 64'd0; + soc_litedramcore_slave_p3_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin + soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; end else begin - soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_105 = dummy_s; @@ -5546,11 +5545,11 @@ end reg dummy_d_106; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata_en <= 1'd0; + soc_litedramcore_master_p3_cke <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en; + soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke; end else begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en; + soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke; end // synthesis translate_off dummy_d_106 = dummy_s; @@ -5561,10 +5560,11 @@ end reg dummy_d_107; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_rddata_valid <= 1'd0; + soc_litedramcore_master_p3_odt <= 1'd0; if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt; end else begin - soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_107 = dummy_s; @@ -5575,11 +5575,11 @@ end reg dummy_d_108; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_wrdata_mask <= 8'd0; + soc_litedramcore_master_p3_reset_n <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask; + soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n; end else begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask; + soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_108 = dummy_s; @@ -5590,11 +5590,11 @@ end reg dummy_d_109; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p0_rddata_en <= 1'd0; + soc_litedramcore_master_p3_act_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en; + soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n; end else begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en; + soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_109 = dummy_s; @@ -5605,11 +5605,11 @@ end reg dummy_d_110; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_address <= 15'd0; + soc_litedramcore_master_p3_wrdata <= 64'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address; + soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata; end else begin - soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address; + soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_110 = dummy_s; @@ -5620,11 +5620,11 @@ end reg dummy_d_111; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_bank <= 3'd0; + soc_litedramcore_master_p3_wrdata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank; + soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en; end else begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank; + soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_111 = dummy_s; @@ -5635,11 +5635,11 @@ end reg dummy_d_112; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cas_n <= 1'd1; + soc_litedramcore_master_p3_wrdata_mask <= 8'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n; + soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask; end else begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n; + soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off dummy_d_112 = dummy_s; @@ -5650,11 +5650,11 @@ end reg dummy_d_113; // synthesis translate_on always @(*) begin - soc_litedramcore_master_p1_cs_n <= 1'd1; + soc_litedramcore_master_p3_rddata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n; + soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en; end else begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n; + soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en; end // synthesis translate_off dummy_d_113 = dummy_s; @@ -5677,11 +5677,11 @@ assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n; reg dummy_d_114; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_ras_n <= 1'd1; + soc_litedramcore_inti_p0_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]); + soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}}; end else begin - soc_litedramcore_inti_p0_ras_n <= 1'd1; + soc_litedramcore_inti_p0_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_114 = dummy_s; @@ -5692,11 +5692,11 @@ end reg dummy_d_115; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_we_n <= 1'd1; + soc_litedramcore_inti_p0_ras_n <= 1'd1; if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]); + soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]); end else begin - soc_litedramcore_inti_p0_we_n <= 1'd1; + soc_litedramcore_inti_p0_ras_n <= 1'd1; end // synthesis translate_off dummy_d_115 = dummy_s; @@ -5707,11 +5707,11 @@ end reg dummy_d_116; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_cas_n <= 1'd1; + soc_litedramcore_inti_p0_we_n <= 1'd1; if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]); + soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]); end else begin - soc_litedramcore_inti_p0_cas_n <= 1'd1; + soc_litedramcore_inti_p0_we_n <= 1'd1; end // synthesis translate_off dummy_d_116 = dummy_s; @@ -5722,11 +5722,11 @@ end reg dummy_d_117; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p0_cs_n <= 1'd1; + soc_litedramcore_inti_p0_cas_n <= 1'd1; if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}}; + soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]); end else begin - soc_litedramcore_inti_p0_cs_n <= {1{1'd1}}; + soc_litedramcore_inti_p0_cas_n <= 1'd1; end // synthesis translate_off dummy_d_117 = dummy_s; @@ -5743,11 +5743,11 @@ assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0; reg dummy_d_118; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_ras_n <= 1'd1; + soc_litedramcore_inti_p1_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]); + soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}}; end else begin - soc_litedramcore_inti_p1_ras_n <= 1'd1; + soc_litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_118 = dummy_s; @@ -5758,11 +5758,11 @@ end reg dummy_d_119; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_we_n <= 1'd1; + soc_litedramcore_inti_p1_ras_n <= 1'd1; if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]); + soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]); end else begin - soc_litedramcore_inti_p1_we_n <= 1'd1; + soc_litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off dummy_d_119 = dummy_s; @@ -5773,11 +5773,11 @@ end reg dummy_d_120; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_cas_n <= 1'd1; + soc_litedramcore_inti_p1_we_n <= 1'd1; if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]); + soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]); end else begin - soc_litedramcore_inti_p1_cas_n <= 1'd1; + soc_litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off dummy_d_120 = dummy_s; @@ -5788,11 +5788,11 @@ end reg dummy_d_121; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p1_cs_n <= 1'd1; + soc_litedramcore_inti_p1_cas_n <= 1'd1; if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}}; + soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]); end else begin - soc_litedramcore_inti_p1_cs_n <= {1{1'd1}}; + soc_litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off dummy_d_121 = dummy_s; @@ -5809,11 +5809,11 @@ assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0; reg dummy_d_122; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_ras_n <= 1'd1; + soc_litedramcore_inti_p2_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]); + soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}}; end else begin - soc_litedramcore_inti_p2_ras_n <= 1'd1; + soc_litedramcore_inti_p2_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_122 = dummy_s; @@ -5824,11 +5824,11 @@ end reg dummy_d_123; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_we_n <= 1'd1; + soc_litedramcore_inti_p2_ras_n <= 1'd1; if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]); + soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]); end else begin - soc_litedramcore_inti_p2_we_n <= 1'd1; + soc_litedramcore_inti_p2_ras_n <= 1'd1; end // synthesis translate_off dummy_d_123 = dummy_s; @@ -5839,11 +5839,11 @@ end reg dummy_d_124; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_cas_n <= 1'd1; + soc_litedramcore_inti_p2_we_n <= 1'd1; if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]); + soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]); end else begin - soc_litedramcore_inti_p2_cas_n <= 1'd1; + soc_litedramcore_inti_p2_we_n <= 1'd1; end // synthesis translate_off dummy_d_124 = dummy_s; @@ -5854,11 +5854,11 @@ end reg dummy_d_125; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p2_cs_n <= 1'd1; + soc_litedramcore_inti_p2_cas_n <= 1'd1; if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}}; + soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]); end else begin - soc_litedramcore_inti_p2_cs_n <= {1{1'd1}}; + soc_litedramcore_inti_p2_cas_n <= 1'd1; end // synthesis translate_off dummy_d_125 = dummy_s; @@ -5875,11 +5875,11 @@ assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0; reg dummy_d_126; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_ras_n <= 1'd1; + soc_litedramcore_inti_p3_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]); + soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}}; end else begin - soc_litedramcore_inti_p3_ras_n <= 1'd1; + soc_litedramcore_inti_p3_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_126 = dummy_s; @@ -5890,11 +5890,11 @@ end reg dummy_d_127; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_we_n <= 1'd1; + soc_litedramcore_inti_p3_ras_n <= 1'd1; if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]); + soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]); end else begin - soc_litedramcore_inti_p3_we_n <= 1'd1; + soc_litedramcore_inti_p3_ras_n <= 1'd1; end // synthesis translate_off dummy_d_127 = dummy_s; @@ -5905,11 +5905,11 @@ end reg dummy_d_128; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_cas_n <= 1'd1; + soc_litedramcore_inti_p3_we_n <= 1'd1; if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]); + soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]); end else begin - soc_litedramcore_inti_p3_cas_n <= 1'd1; + soc_litedramcore_inti_p3_we_n <= 1'd1; end // synthesis translate_off dummy_d_128 = dummy_s; @@ -5920,11 +5920,11 @@ end reg dummy_d_129; // synthesis translate_on always @(*) begin - soc_litedramcore_inti_p3_cs_n <= 1'd1; + soc_litedramcore_inti_p3_cas_n <= 1'd1; if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}}; + soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]); end else begin - soc_litedramcore_inti_p3_cs_n <= {1{1'd1}}; + soc_litedramcore_inti_p3_cas_n <= 1'd1; end // synthesis translate_off dummy_d_129 = dummy_s; @@ -6049,25 +6049,16 @@ end reg dummy_d_131; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_valid <= 1'd0; + soc_litedramcore_sequencer_start0 <= 1'd0; case (vns_refresher_state) 1'd1: begin - soc_litedramcore_cmd_valid <= 1'd1; + if (soc_litedramcore_cmd_ready) begin + soc_litedramcore_sequencer_start0 <= 1'd1; + end end 2'd2: begin - soc_litedramcore_cmd_valid <= 1'd1; - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - end else begin - soc_litedramcore_cmd_valid <= 1'd0; - end - end end 2'd3: begin - soc_litedramcore_cmd_valid <= 1'd1; - if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_valid <= 1'd0; - end end default: begin end @@ -6081,19 +6072,25 @@ end reg dummy_d_132; // synthesis translate_on always @(*) begin - soc_litedramcore_zqcs_executer_start <= 1'd0; + soc_litedramcore_cmd_valid <= 1'd0; case (vns_refresher_state) 1'd1: begin + soc_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin + soc_litedramcore_cmd_valid <= 1'd1; if (soc_litedramcore_sequencer_done0) begin if (soc_litedramcore_wants_zqcs) begin - soc_litedramcore_zqcs_executer_start <= 1'd1; end else begin + soc_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin + soc_litedramcore_cmd_valid <= 1'd1; + if (soc_litedramcore_zqcs_executer_done) begin + soc_litedramcore_cmd_valid <= 1'd0; + end end default: begin end @@ -6107,22 +6104,19 @@ end reg dummy_d_133; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_last <= 1'd0; + soc_litedramcore_zqcs_executer_start <= 1'd0; case (vns_refresher_state) 1'd1: begin end 2'd2: begin if (soc_litedramcore_sequencer_done0) begin if (soc_litedramcore_wants_zqcs) begin + soc_litedramcore_zqcs_executer_start <= 1'd1; end else begin - soc_litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin - if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_last <= 1'd1; - end end default: begin end @@ -6136,16 +6130,22 @@ end reg dummy_d_134; // synthesis translate_on always @(*) begin - soc_litedramcore_sequencer_start0 <= 1'd0; + soc_litedramcore_cmd_last <= 1'd0; case (vns_refresher_state) 1'd1: begin - if (soc_litedramcore_cmd_ready) begin - soc_litedramcore_sequencer_start0 <= 1'd1; - end end 2'd2: begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + end else begin + soc_litedramcore_cmd_last <= 1'd1; + end + end end 2'd3: begin + if (soc_litedramcore_zqcs_executer_done) begin + soc_litedramcore_cmd_last <= 1'd1; + end end default: begin end @@ -6314,7 +6314,7 @@ end reg dummy_d_139; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin end @@ -6338,10 +6338,7 @@ always @(*) begin if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine0_row_opened) begin if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6359,41 +6356,32 @@ end reg dummy_d_140; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end endcase // synthesis translate_off dummy_d_140 = dummy_s; @@ -6404,9 +6392,12 @@ end reg dummy_d_141; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -6429,8 +6420,8 @@ always @(*) begin if (soc_litedramcore_bankmachine0_row_opened) begin if (soc_litedramcore_bankmachine0_row_hit) begin if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -6449,18 +6440,18 @@ end reg dummy_d_142; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine0_twtpcon_ready) begin - soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -6482,21 +6473,22 @@ end reg dummy_d_143; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6507,18 +6499,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6530,16 +6510,13 @@ end reg dummy_d_144; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_open <= 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_open <= 1'd1; - end end 3'd4: begin end @@ -6552,6 +6529,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -6563,18 +6555,15 @@ end reg dummy_d_145; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_close <= 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -6585,6 +6574,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -6596,7 +6600,7 @@ end reg dummy_d_146; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin end @@ -6620,7 +6624,10 @@ always @(*) begin if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine0_row_opened) begin if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready; + end else begin + end end else begin end end else begin @@ -6638,19 +6645,13 @@ end reg dummy_d_147; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -6663,6 +6664,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -6674,18 +6690,18 @@ end reg dummy_d_148; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine0_twtpcon_ready) begin + soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6707,16 +6723,19 @@ end reg dummy_d_149; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6734,10 +6753,7 @@ always @(*) begin if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine0_row_opened) begin if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; end else begin end end else begin @@ -6755,22 +6771,18 @@ end reg dummy_d_150; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + soc_litedramcore_bankmachine0_row_open <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + soc_litedramcore_bankmachine0_row_open <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6792,15 +6804,18 @@ end reg dummy_d_151; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + soc_litedramcore_bankmachine0_row_close <= 1'd0; case (vns_bankmachine0_state) 1'd1: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -6811,21 +6826,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6992,7 +6992,7 @@ end reg dummy_d_156; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin end @@ -7016,10 +7016,7 @@ always @(*) begin if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine1_row_opened) begin if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7037,13 +7034,19 @@ end reg dummy_d_157; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -7056,21 +7059,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7082,16 +7070,16 @@ end reg dummy_d_158; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -7104,6 +7092,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7115,13 +7118,16 @@ end reg dummy_d_159; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -7134,21 +7140,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7160,18 +7151,22 @@ end reg dummy_d_160; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine1_twtpcon_ready) begin - soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7193,19 +7188,13 @@ end reg dummy_d_161; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7223,7 +7212,10 @@ always @(*) begin if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine1_row_opened) begin if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -7241,16 +7233,13 @@ end reg dummy_d_162; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_open <= 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_open <= 1'd1; - end end 3'd4: begin end @@ -7263,6 +7252,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7274,18 +7278,15 @@ end reg dummy_d_163; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_row_close <= 1'd0; + soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -7296,6 +7297,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7307,7 +7323,7 @@ end reg dummy_d_164; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin end @@ -7331,7 +7347,10 @@ always @(*) begin if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine1_row_opened) begin if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready; + end end else begin end end else begin @@ -7349,21 +7368,18 @@ end reg dummy_d_165; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine1_twtpcon_ready) begin + soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7385,16 +7401,19 @@ end reg dummy_d_166; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + soc_litedramcore_bankmachine1_cmd_valid <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -7412,10 +7431,7 @@ always @(*) begin if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine1_row_opened) begin if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin @@ -7433,22 +7449,18 @@ end reg dummy_d_167; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + soc_litedramcore_bankmachine1_row_open <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + soc_litedramcore_bankmachine1_row_open <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7470,15 +7482,18 @@ end reg dummy_d_168; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + soc_litedramcore_bankmachine1_row_close <= 1'd0; case (vns_bankmachine1_state) 1'd1: begin + soc_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + soc_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -7489,21 +7504,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7670,7 +7670,7 @@ end reg dummy_d_173; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin end @@ -7694,10 +7694,7 @@ always @(*) begin if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine2_row_opened) begin if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7715,13 +7712,19 @@ end reg dummy_d_174; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -7734,21 +7737,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7760,9 +7748,12 @@ end reg dummy_d_175; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -7785,8 +7776,8 @@ always @(*) begin if (soc_litedramcore_bankmachine2_row_opened) begin if (soc_litedramcore_bankmachine2_row_hit) begin if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -7805,18 +7796,18 @@ end reg dummy_d_176; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine2_twtpcon_ready) begin - soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7838,21 +7829,22 @@ end reg dummy_d_177; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7863,18 +7855,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7886,16 +7866,13 @@ end reg dummy_d_178; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -7908,6 +7885,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7919,16 +7911,13 @@ end reg dummy_d_179; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_open <= 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_open <= 1'd1; - end end 3'd4: begin end @@ -7941,6 +7930,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7952,18 +7956,15 @@ end reg dummy_d_180; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_row_close <= 1'd0; + soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -7974,6 +7975,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7985,7 +8001,7 @@ end reg dummy_d_181; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin end @@ -8009,7 +8025,10 @@ always @(*) begin if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine2_row_opened) begin if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready; + end end else begin end end else begin @@ -8027,21 +8046,18 @@ end reg dummy_d_182; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine2_twtpcon_ready) begin + soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8063,16 +8079,19 @@ end reg dummy_d_183; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + soc_litedramcore_bankmachine2_cmd_valid <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -8090,10 +8109,7 @@ always @(*) begin if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine2_row_opened) begin if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -8111,22 +8127,18 @@ end reg dummy_d_184; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + soc_litedramcore_bankmachine2_row_open <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + soc_litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8148,15 +8160,18 @@ end reg dummy_d_185; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + soc_litedramcore_bankmachine2_row_close <= 1'd0; case (vns_bankmachine2_state) 1'd1: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -8167,21 +8182,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -8348,7 +8348,7 @@ end reg dummy_d_190; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin end @@ -8372,10 +8372,7 @@ always @(*) begin if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine3_row_opened) begin if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8393,13 +8390,19 @@ end reg dummy_d_191; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -8412,21 +8415,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -8438,9 +8426,12 @@ end reg dummy_d_192; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -8463,8 +8454,8 @@ always @(*) begin if (soc_litedramcore_bankmachine3_row_opened) begin if (soc_litedramcore_bankmachine3_row_hit) begin if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -8483,18 +8474,18 @@ end reg dummy_d_193; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine3_twtpcon_ready) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8516,21 +8507,22 @@ end reg dummy_d_194; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8541,18 +8533,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -8564,16 +8544,13 @@ end reg dummy_d_195; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_open <= 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_open <= 1'd1; - end end 3'd4: begin end @@ -8586,6 +8563,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8597,18 +8589,15 @@ end reg dummy_d_196; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_close <= 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -8619,6 +8608,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8630,16 +8634,13 @@ end reg dummy_d_197; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -8652,6 +8653,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8663,7 +8679,7 @@ end reg dummy_d_198; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin end @@ -8687,7 +8703,10 @@ always @(*) begin if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine3_row_opened) begin if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; + end end else begin end end else begin @@ -8705,21 +8724,18 @@ end reg dummy_d_199; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine3_twtpcon_ready) begin + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8741,16 +8757,19 @@ end reg dummy_d_200; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + soc_litedramcore_bankmachine3_cmd_valid <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -8768,10 +8787,7 @@ always @(*) begin if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine3_row_opened) begin if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -8789,22 +8805,18 @@ end reg dummy_d_201; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + soc_litedramcore_bankmachine3_row_open <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + soc_litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8826,15 +8838,18 @@ end reg dummy_d_202; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + soc_litedramcore_bankmachine3_row_close <= 1'd0; case (vns_bankmachine3_state) 1'd1: begin + soc_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + soc_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -8845,21 +8860,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9026,7 +9026,7 @@ end reg dummy_d_207; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin end @@ -9050,10 +9050,7 @@ always @(*) begin if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine4_row_opened) begin if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9071,13 +9068,19 @@ end reg dummy_d_208; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -9090,21 +9093,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9116,9 +9104,12 @@ end reg dummy_d_209; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -9141,8 +9132,8 @@ always @(*) begin if (soc_litedramcore_bankmachine4_row_opened) begin if (soc_litedramcore_bankmachine4_row_hit) begin if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -9161,18 +9152,18 @@ end reg dummy_d_210; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine4_twtpcon_ready) begin - soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9194,21 +9185,22 @@ end reg dummy_d_211; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9219,18 +9211,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9242,16 +9222,13 @@ end reg dummy_d_212; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_open <= 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_open <= 1'd1; - end end 3'd4: begin end @@ -9264,6 +9241,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9275,18 +9267,15 @@ end reg dummy_d_213; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_close <= 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -9297,6 +9286,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9308,7 +9312,7 @@ end reg dummy_d_214; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin end @@ -9332,7 +9336,10 @@ always @(*) begin if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine4_row_opened) begin if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready; + end else begin + end end else begin end end else begin @@ -9350,19 +9357,13 @@ end reg dummy_d_215; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -9375,6 +9376,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9386,18 +9402,18 @@ end reg dummy_d_216; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end 2'd3: begin end 3'd4: begin + if (soc_litedramcore_bankmachine4_twtpcon_ready) begin + soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9408,21 +9424,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9434,22 +9435,21 @@ end reg dummy_d_217; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + soc_litedramcore_bankmachine4_cmd_valid <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9460,6 +9460,18 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9471,7 +9483,7 @@ end reg dummy_d_218; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + soc_litedramcore_bankmachine4_row_open <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin end @@ -9479,7 +9491,7 @@ always @(*) begin end 2'd3: begin if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + soc_litedramcore_bankmachine4_row_open <= 1'd1; end end 3'd4: begin @@ -9504,15 +9516,18 @@ end reg dummy_d_219; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + soc_litedramcore_bankmachine4_row_close <= 1'd0; case (vns_bankmachine4_state) 1'd1: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -9523,21 +9538,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9704,7 +9704,7 @@ end reg dummy_d_224; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; case (vns_bankmachine5_state) 1'd1: begin end @@ -9728,10 +9728,7 @@ always @(*) begin if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine5_row_opened) begin if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9749,13 +9746,19 @@ end reg dummy_d_225; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; case (vns_bankmachine5_state) 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -9768,21 +9771,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9794,9 +9782,12 @@ end reg dummy_d_226; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; case (vns_bankmachine5_state) 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -9819,8 +9810,8 @@ always @(*) begin if (soc_litedramcore_bankmachine5_row_opened) begin if (soc_litedramcore_bankmachine5_row_hit) begin if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -9872,18 +9863,22 @@ end reg dummy_d_228; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; case (vns_bankmachine5_state) 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine5_twtpcon_ready) begin - soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9905,19 +9900,13 @@ end reg dummy_d_229; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; case (vns_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -9935,7 +9924,10 @@ always @(*) begin if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine5_row_opened) begin if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -9953,16 +9945,13 @@ end reg dummy_d_230; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_open <= 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (vns_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_open <= 1'd1; - end end 3'd4: begin end @@ -9975,6 +9964,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9986,18 +9990,15 @@ end reg dummy_d_231; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_row_close <= 1'd0; + soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (vns_bankmachine5_state) 1'd1: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -10008,6 +10009,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -10019,7 +10035,7 @@ end reg dummy_d_232; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; case (vns_bankmachine5_state) 1'd1: begin end @@ -10043,7 +10059,10 @@ always @(*) begin if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine5_row_opened) begin if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready; + end end else begin end end else begin @@ -10061,21 +10080,18 @@ end reg dummy_d_233; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (vns_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine5_twtpcon_ready) begin + soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -10097,16 +10113,19 @@ end reg dummy_d_234; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + soc_litedramcore_bankmachine5_cmd_valid <= 1'd0; case (vns_bankmachine5_state) 1'd1: begin if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -10124,10 +10143,7 @@ always @(*) begin if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine5_row_opened) begin if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -10145,22 +10161,18 @@ end reg dummy_d_235; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + soc_litedramcore_bankmachine5_row_open <= 1'd0; case (vns_bankmachine5_state) 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + soc_litedramcore_bankmachine5_row_open <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10182,15 +10194,18 @@ end reg dummy_d_236; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + soc_litedramcore_bankmachine5_row_close <= 1'd0; case (vns_bankmachine5_state) 1'd1: begin + soc_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + soc_litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -10201,21 +10216,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -10382,7 +10382,7 @@ end reg dummy_d_241; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin end @@ -10406,10 +10406,7 @@ always @(*) begin if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine6_row_opened) begin if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -10427,13 +10424,19 @@ end reg dummy_d_242; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -10446,21 +10449,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -10472,9 +10460,12 @@ end reg dummy_d_243; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -10497,8 +10488,8 @@ always @(*) begin if (soc_litedramcore_bankmachine6_row_opened) begin if (soc_litedramcore_bankmachine6_row_hit) begin if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -10517,18 +10508,18 @@ end reg dummy_d_244; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine6_twtpcon_ready) begin - soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -10550,21 +10541,22 @@ end reg dummy_d_245; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10575,18 +10567,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -10598,16 +10578,13 @@ end reg dummy_d_246; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -10620,6 +10597,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -10631,16 +10623,13 @@ end reg dummy_d_247; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_open <= 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_open <= 1'd1; - end end 3'd4: begin end @@ -10653,6 +10642,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -10664,18 +10668,15 @@ end reg dummy_d_248; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_row_close <= 1'd0; + soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -10686,6 +10687,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -10697,7 +10713,7 @@ end reg dummy_d_249; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin end @@ -10721,7 +10737,10 @@ always @(*) begin if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine6_row_opened) begin if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready; + end end else begin end end else begin @@ -10739,21 +10758,18 @@ end reg dummy_d_250; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine6_twtpcon_ready) begin + soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -10775,16 +10791,19 @@ end reg dummy_d_251; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + soc_litedramcore_bankmachine6_cmd_valid <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -10802,10 +10821,7 @@ always @(*) begin if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine6_row_opened) begin if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin end end else begin @@ -10823,22 +10839,18 @@ end reg dummy_d_252; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + soc_litedramcore_bankmachine6_row_open <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + soc_litedramcore_bankmachine6_row_open <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10860,15 +10872,18 @@ end reg dummy_d_253; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + soc_litedramcore_bankmachine6_row_close <= 1'd0; case (vns_bankmachine6_state) 1'd1: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -10879,21 +10894,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -11060,7 +11060,7 @@ end reg dummy_d_258; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin end @@ -11084,10 +11084,7 @@ always @(*) begin if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine7_row_opened) begin if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -11105,13 +11102,19 @@ end reg dummy_d_259; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -11124,21 +11127,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -11150,9 +11138,12 @@ end reg dummy_d_260; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -11175,8 +11166,8 @@ always @(*) begin if (soc_litedramcore_bankmachine7_row_opened) begin if (soc_litedramcore_bankmachine7_row_hit) begin if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin - soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -11195,18 +11186,18 @@ end reg dummy_d_261; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine7_twtpcon_ready) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -11228,21 +11219,22 @@ end reg dummy_d_262; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -11253,18 +11245,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -11276,16 +11256,13 @@ end reg dummy_d_263; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -11298,6 +11275,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -11309,16 +11301,13 @@ end reg dummy_d_264; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_open <= 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_open <= 1'd1; - end end 3'd4: begin end @@ -11331,6 +11320,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -11342,18 +11346,15 @@ end reg dummy_d_265; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_row_close <= 1'd0; + soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -11364,6 +11365,21 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -11375,7 +11391,7 @@ end reg dummy_d_266; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin end @@ -11399,7 +11415,10 @@ always @(*) begin if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine7_row_opened) begin if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; + end end else begin end end else begin @@ -11417,21 +11436,18 @@ end reg dummy_d_267; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine7_twtpcon_ready) begin + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -11453,16 +11469,19 @@ end reg dummy_d_268; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + soc_litedramcore_bankmachine7_cmd_valid <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -11480,10 +11499,7 @@ always @(*) begin if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine7_row_opened) begin if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -11501,22 +11517,18 @@ end reg dummy_d_269; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + soc_litedramcore_bankmachine7_row_open <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + soc_litedramcore_bankmachine7_row_open <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -11538,15 +11550,18 @@ end reg dummy_d_270; // synthesis translate_on always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + soc_litedramcore_bankmachine7_row_close <= 1'd0; case (vns_bankmachine7_state) 1'd1: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -11557,21 +11572,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -11946,12 +11946,13 @@ end reg dummy_d_288; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel2 <= 2'd0; + soc_litedramcore_steerer_sel0 <= 2'd0; case (vns_multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel2 <= 1'd1; + soc_litedramcore_steerer_sel0 <= 1'd0; end 2'd2: begin + soc_litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -11970,7 +11971,7 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel2 <= 2'd2; + soc_litedramcore_steerer_sel0 <= 1'd0; end endcase // synthesis translate_off @@ -11982,13 +11983,10 @@ end reg dummy_d_289; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_want_activates <= 1'd0; + soc_litedramcore_en1 <= 1'd0; case (vns_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; - end + soc_litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -12009,10 +12007,6 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; - end end endcase // synthesis translate_off @@ -12024,10 +12018,10 @@ end reg dummy_d_290; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel3 <= 2'd0; + soc_litedramcore_steerer_sel1 <= 2'd0; case (vns_multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel3 <= 2'd2; + soc_litedramcore_steerer_sel1 <= 1'd1; end 2'd2: begin end @@ -12048,7 +12042,7 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel3 <= 1'd0; + soc_litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off @@ -12060,9 +12054,10 @@ end reg dummy_d_291; // synthesis translate_on always @(*) begin - soc_litedramcore_en0 <= 1'd0; + soc_litedramcore_steerer_sel2 <= 2'd0; case (vns_multiplexer_state) 1'd1: begin + soc_litedramcore_steerer_sel2 <= 2'd2; end 2'd2: begin end @@ -12083,7 +12078,7 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_en0 <= 1'd1; + soc_litedramcore_steerer_sel2 <= 2'd2; end endcase // synthesis translate_off @@ -12095,12 +12090,15 @@ end reg dummy_d_292; // synthesis translate_on always @(*) begin - soc_litedramcore_cmd_ready <= 1'd0; + soc_litedramcore_choose_cmd_want_activates <= 1'd0; case (vns_multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + end end 2'd2: begin - soc_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -12119,6 +12117,10 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + end end endcase // synthesis translate_off @@ -12130,13 +12132,10 @@ end reg dummy_d_293; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_cmd_cmd_ready <= 1'd0; + soc_litedramcore_steerer_sel3 <= 2'd0; case (vns_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); - end + soc_litedramcore_steerer_sel3 <= 1'd0; end 2'd2: begin end @@ -12157,10 +12156,7 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); - end + soc_litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off @@ -12172,7 +12168,7 @@ end reg dummy_d_294; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_want_reads <= 1'd0; + soc_litedramcore_en0 <= 1'd0; case (vns_multiplexer_state) 1'd1: begin end @@ -12195,7 +12191,7 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_choose_req_want_reads <= 1'd1; + soc_litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off @@ -12207,12 +12203,12 @@ end reg dummy_d_295; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_want_writes <= 1'd0; + soc_litedramcore_cmd_ready <= 1'd0; case (vns_multiplexer_state) 1'd1: begin - soc_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin + soc_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -12242,13 +12238,12 @@ end reg dummy_d_296; // synthesis translate_on always @(*) begin - soc_litedramcore_choose_req_cmd_ready <= 1'd0; + soc_litedramcore_choose_cmd_cmd_ready <= 1'd0; case (vns_multiplexer_state) 1'd1: begin if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); end end 2'd2: begin @@ -12271,9 +12266,8 @@ always @(*) begin end default: begin if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); end end endcase @@ -12286,10 +12280,9 @@ end reg dummy_d_297; // synthesis translate_on always @(*) begin - soc_litedramcore_en1 <= 1'd0; + soc_litedramcore_choose_req_want_reads <= 1'd0; case (vns_multiplexer_state) 1'd1: begin - soc_litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -12310,6 +12303,7 @@ always @(*) begin 4'd10: begin end default: begin + soc_litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off @@ -12321,13 +12315,12 @@ end reg dummy_d_298; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel0 <= 2'd0; + soc_litedramcore_choose_req_want_writes <= 1'd0; case (vns_multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel0 <= 1'd0; + soc_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin - soc_litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -12346,7 +12339,6 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel0 <= 1'd0; end endcase // synthesis translate_off @@ -12358,10 +12350,14 @@ end reg dummy_d_299; // synthesis translate_on always @(*) begin - soc_litedramcore_steerer_sel1 <= 2'd0; + soc_litedramcore_choose_req_cmd_ready <= 1'd0; case (vns_multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel1 <= 1'd0; + if (1'd0) begin + soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + end else begin + soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + end end 2'd2: begin end @@ -12382,7 +12378,11 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel1 <= 1'd1; + if (1'd0) begin + soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + end else begin + soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + end end endcase // synthesis translate_off diff --git a/microwatt.core b/microwatt.core index 8bb5103..a2d37df 100644 --- a/microwatt.core +++ b/microwatt.core @@ -91,6 +91,12 @@ filesets: - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008} + genesys2: + files: + - fpga/genesys2.xdc : {file_type : xdc} + - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} + - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008} + arty_a7: files: - fpga/arty_a7.xdc : {file_type : xdc} @@ -144,6 +150,23 @@ targets: vivado: {part : xc7a200tsbg484-2} toplevel : toplevel + genesys2-nodram: + default_tool: vivado + filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific] + parameters : + - memory_size + - ram_init_file + - clk_frequency + - use_litedram=false + - no_bram=false + - disable_flatten_core + - spi_flash_offset=10485760 + - log_length=2048 + - uart_is_16550=false + tools: + vivado: {part : xc7k325tffg900-2} + toplevel : toplevel + acorn-cle-215: default_tool: vivado filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific] @@ -161,6 +184,23 @@ targets: vivado: {part : xc7a200tsbg484-2} toplevel : toplevel + genesys2: + default_tool: vivado + filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific] + parameters : + - memory_size + - ram_init_file + - use_litedram=true + - disable_flatten_core + - no_bram + - spi_flash_offset=10485760 + - log_length=2048 + - uart_is_16550=false + generate: [litedram_genesys2] + tools: + vivado: {part : xc7k325tffg900-2} + toplevel : toplevel + nexys_video-nodram: default_tool: vivado filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific] @@ -305,6 +345,10 @@ generate: generator: litedram_gen parameters: {board : acorn-cle-215} + litedram_genesys2: + generator: litedram_gen + parameters: {board : genesys2} + parameters: memory_size: datatype : int