From 803ee9ef3594d3810e63a994ea45ca244c28958e Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 14 May 2020 10:12:44 +1000 Subject: [PATCH 01/10] Makefile: Improve clean a bit Signed-off-by: Benjamin Herrenschmidt --- Makefile | 4 +++- hello_world/Makefile | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b9ad461..749f771 100644 --- a/Makefile +++ b/Makefile @@ -163,11 +163,13 @@ _clean: clean: _clean make -f scripts/mw_debug/Makefile clean + make -f hello_world/Makefile clean distclean: _clean - rm -f *~ fpga/~ + rm -f *~ fpga/*~ lib/*~ console/*~ include/*~ rm -rf litedram/build rm -f litedram/extras/*~ rm -f litedram/gen-src/*~ rm -f litedram/gen-src/sdram_init/*~ make -f scripts/mw_debug/Makefile distclean + make -f hello_world/Makefile distclean diff --git a/hello_world/Makefile b/hello_world/Makefile index 4c7d3ac..dd51bd3 100644 --- a/hello_world/Makefile +++ b/hello_world/Makefile @@ -29,3 +29,6 @@ hello_world.hex: hello_world.bin clean: @rm -f *.o hello_world.elf hello_world.bin hello_world.hex +distclean: clean + rm -f *~ + From bd42580a4217b6a66e0842d370f57b5022e6f9f1 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 14 May 2020 12:30:11 +1000 Subject: [PATCH 02/10] pp_fifo: Fix full fifo losing all data on simultaneous push & pop The pp_fifo decides whether top = bottom means empty or full based on whether the previous operation was a push or a pop. If the fifo performs both in one cycle, it sets the previous op to pop. That means that a full fifo being added a character and removed one at the same time becomes empty. Instead, just leave the previous op alone. If the fifo was empty, it remains so, if it was full ditto. Signed-off-by: Benjamin Herrenschmidt --- fpga/pp_fifo.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/pp_fifo.vhd b/fpga/pp_fifo.vhd index ee9b701..553a499 100644 --- a/fpga/pp_fifo.vhd +++ b/fpga/pp_fifo.vhd @@ -78,7 +78,7 @@ begin prev_op <= FIFO_POP; else if push = '1' and pop = '1' then - prev_op <= FIFO_POP; + -- Keep the same value for prev_op elsif push = '1' then prev_op <= FIFO_PUSH; elsif pop = '1' then From 13e84b0bbb7a0ce2bd935bf3c36e601f85c6f8b0 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 14 May 2020 14:26:14 +1000 Subject: [PATCH 03/10] pp_soc_uart: Fix rx synchronizers and ensure stable tx init state The rx synchronizers were ... non existent. Someone forgot to add a if rising_edge(clk) to the process. For tx, ensure that we have a default value so that TX stays high from TPGA configuration to the reset being sampled on the first clock cycle. Signed-off-by: Benjamin Herrenschmidt --- fpga/pp_soc_uart.vhd | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/fpga/pp_soc_uart.vhd b/fpga/pp_soc_uart.vhd index 429bec4..8c4c93c 100644 --- a/fpga/pp_soc_uart.vhd +++ b/fpga/pp_soc_uart.vhd @@ -111,6 +111,7 @@ architecture behaviour of pp_soc_uart is signal rxd2 : std_logic := '1'; signal rxd3 : std_logic := '1'; + signal txd2 : std_ulogic := '1'; begin irq <= (irq_recv_enable and (not recv_buffer_empty)) @@ -123,9 +124,12 @@ begin -- Add a few FFs on the RX input to avoid metastability issues process (clk) is begin - rxd3 <= rxd2; - rxd2 <= rxd; + if rising_edge(clk) then + rxd3 <= rxd2; + rxd2 <= rxd; + end if; end process; + txd <= txd2; uart_receive: process(clk) begin @@ -202,7 +206,7 @@ begin begin if rising_edge(clk) then if reset = '1' then - txd <= '1'; + txd2 <= '1'; tx_state <= IDLE; send_buffer_pop <= '0'; tx_current_bit <= 0; @@ -210,26 +214,26 @@ begin case tx_state is when IDLE => if send_buffer_empty = '0' and uart_tx_clk = '1' then - txd <= '0'; + txd2 <= '0'; send_buffer_pop <= '1'; tx_current_bit <= 0; tx_state <= TRANSMIT; elsif uart_tx_clk = '1' then - txd <= '1'; + txd2 <= '1'; end if; when TRANSMIT => if send_buffer_pop = '1' then send_buffer_pop <= '0'; elsif uart_tx_clk = '1' and tx_current_bit = 7 then - txd <= tx_byte(tx_current_bit); + txd2 <= tx_byte(tx_current_bit); tx_state <= STOPBIT; elsif uart_tx_clk = '1' then - txd <= tx_byte(tx_current_bit); + txd2 <= tx_byte(tx_current_bit); tx_current_bit <= tx_current_bit + 1; end if; when STOPBIT => if uart_tx_clk = '1' then - txd <= '1'; + txd2 <= '1'; tx_state <= IDLE; end if; end case; From c19b5b8cc7470c68243ceed6339f831747c0be40 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 20:27:15 +1000 Subject: [PATCH 04/10] litedram: Update to new LiteX/LiteDRAM version Things have changed a bit in upstream LiteX. LiteDRAM now exposes a wishbone for the CSRs for example. Signed-off-by: Benjamin Herrenschmidt --- fpga/top-arty.vhdl | 6 +- fpga/top-nexys-video.vhdl | 6 +- include/console.h | 3 + include/microwatt_soc.h | 3 + lib/console.c | 2 + litedram/gen-src/arty.yml | 4 +- litedram/gen-src/generate.py | 3 +- litedram/gen-src/nexys-video.yml | 3 +- litedram/gen-src/sdram_init/Makefile | 4 +- litedram/gen-src/sdram_init/include/system.h | 30 +- litedram/gen-src/sdram_init/main.c | 105 +- litedram/gen-src/wrapper-mw-init.vhdl | 119 +- litedram/gen-src/wrapper-self-init.vhdl | 8 +- litedram/generated/arty/litedram-wrapper.vhdl | 130 +- litedram/generated/arty/litedram_core.init | 1551 +++---- litedram/generated/arty/litedram_core.v | 2875 +++++++----- .../nexys-video/litedram-wrapper.vhdl | 130 +- .../generated/nexys-video/litedram_core.init | 920 ++-- .../generated/nexys-video/litedram_core.v | 4011 ++++++++++------- soc.vhdl | 14 +- 20 files changed, 5523 insertions(+), 4404 deletions(-) diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index fbea534..9150f82 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -68,7 +68,7 @@ architecture behaviour of toplevel is -- DRAM wishbone connection signal wb_dram_in : wishbone_master_out; signal wb_dram_out : wishbone_slave_out; - signal wb_dram_csr : std_ulogic; + signal wb_dram_ctrl : std_ulogic; signal wb_dram_init : std_ulogic; -- Control/status @@ -104,7 +104,7 @@ begin uart0_rxd => uart_main_rx, wb_dram_in => wb_dram_in, wb_dram_out => wb_dram_out, - wb_dram_csr => wb_dram_csr, + wb_dram_ctrl => wb_dram_ctrl, wb_dram_init => wb_dram_init, alt_reset => core_alt_reset ); @@ -194,7 +194,7 @@ begin wb_in => wb_dram_in, wb_out => wb_dram_out, - wb_is_csr => wb_dram_csr, + wb_is_ctrl => wb_dram_ctrl, wb_is_init => wb_dram_init, serial_tx => uart_pmod_tx, diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index c0e3659..7cabfa6 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -60,7 +60,7 @@ architecture behaviour of toplevel is -- DRAM wishbone connection signal wb_dram_in : wishbone_master_out; signal wb_dram_out : wishbone_slave_out; - signal wb_dram_csr : std_ulogic; + signal wb_dram_ctrl : std_ulogic; signal wb_dram_init : std_ulogic; -- Control/status @@ -87,7 +87,7 @@ begin uart0_rxd => uart_main_rx, wb_dram_in => wb_dram_in, wb_dram_out => wb_dram_out, - wb_dram_csr => wb_dram_csr, + wb_dram_ctrl => wb_dram_ctrl, wb_dram_init => wb_dram_init, alt_reset => core_alt_reset ); @@ -175,7 +175,7 @@ begin wb_in => wb_dram_in, wb_out => wb_dram_out, - wb_is_csr => wb_dram_csr, + wb_is_ctrl => wb_dram_ctrl, wb_is_init => wb_dram_init, serial_tx => open, diff --git a/include/console.h b/include/console.h index cfd9dc1..e871c67 100644 --- a/include/console.h +++ b/include/console.h @@ -6,4 +6,7 @@ void potato_uart_irq_dis(void); int getchar(void); int putchar(int c); int puts(const char *str); + +#ifndef __USE_LIBC size_t strlen(const char *s); +#endif diff --git a/include/microwatt_soc.h b/include/microwatt_soc.h index 35add6b..16871a4 100644 --- a/include/microwatt_soc.h +++ b/include/microwatt_soc.h @@ -31,4 +31,7 @@ #define POTATO_CONSOLE_CLOCK_DIV 0x18 #define POTATO_CONSOLE_IRQ_EN 0x20 +/* Definition for the LiteDRAM control registers */ +#define DRAM_CTRL_BASE 0xc0100000 + #endif /* __MICROWATT_SOC_H */ diff --git a/lib/console.c b/lib/console.c index fa2ade3..a75d9a0 100644 --- a/lib/console.c +++ b/lib/console.c @@ -120,6 +120,7 @@ int puts(const char *str) return 0; } +#ifndef __USE_LIBC size_t strlen(const char *s) { size_t len = 0; @@ -129,3 +130,4 @@ size_t strlen(const char *s) return len; } +#endif diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml index a84f964..a4c982b 100644 --- a/litedram/gen-src/arty.yml +++ b/litedram/gen-src/arty.yml @@ -37,7 +37,5 @@ }, # CSR Port ----------------------------------------------------------------- - "csr_expose": "False", # expose access to CSR (I/O) ports - "csr_align" : 32, # CSR alignment - "csr_base" : 0xc0100000 # For cpu=None only + "csr_base" : 0xc0100000, # For cpu=None only } diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 4c24cae..3ec8690 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -104,8 +104,7 @@ def generate_one(t, mw_init): # Override values for mw_init if mw_init: core_config["cpu"] = None - core_config["csr_expose"] = True - core_config["csr_align"] = 64 + core_config["csr_alignment"] = 64 # Generate core if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: diff --git a/litedram/gen-src/nexys-video.yml b/litedram/gen-src/nexys-video.yml index 640ccab..23c1ce4 100644 --- a/litedram/gen-src/nexys-video.yml +++ b/litedram/gen-src/nexys-video.yml @@ -37,6 +37,5 @@ }, # CSR Port ----------------------------------------------------------------- - "csr_expose": "False", # expose access to CSR (I/O) ports - "csr_align" : 32, # 64-bit alignment + "csr_base" : 0xc0100000, # For cpu=None only } diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile index 367b89d..4bc3e7b 100644 --- a/litedram/gen-src/sdram_init/Makefile +++ b/litedram/gen-src/sdram_init/Makefile @@ -21,7 +21,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy #### Flags -CPPFLAGS = -nostdinc +CPPFLAGS = -nostdinc -D__USE_LIBC CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../../include CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include) CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks @@ -36,7 +36,7 @@ define Q endef else define Q - @echo " [$1] $(3)" + @echo " [$1] " $(shell basename $3) @$(2) endef endif diff --git a/litedram/gen-src/sdram_init/include/system.h b/litedram/gen-src/sdram_init/include/system.h index 879f4ca..ded9b10 100644 --- a/litedram/gen-src/sdram_init/include/system.h +++ b/litedram/gen-src/sdram_init/include/system.h @@ -1,9 +1,18 @@ -static inline void flush_cpu_dcache(void) { } -static inline void flush_l2_cache(void) { } +#ifndef __SYSTEM_H +#define __SYSTEM_H + +#include "microwatt_soc.h" +#include "io.h" + +#define CSR_ACCESSORS_DEFINED +#define CSR_BASE DRAM_CTRL_BASE +#define CONFIG_CPU_NOP "nop" -#define CONFIG_CPU_NOP "nop" -#define CONFIG_CLOCK_FREQUENCY 100000000 +extern void flush_cpu_dcache(void); +extern void flush_cpu_icache(void); +static inline void flush_l2_cache(void) { } +/* Fake timer stuff. LiteX should abstract this */ static inline void timer0_en_write(int e) { } static inline void timer0_reload_write(int r) { } static inline void timer0_load_write(int l) { } @@ -15,3 +24,16 @@ static inline uint64_t timer0_value_read(void) __asm__ volatile ("mfdec %0" : "=r" (val)); return val; } + +static inline void csr_write_simple(unsigned long v, unsigned long a) +{ + return writel(v, a); +} + +static inline unsigned long csr_read_simple(unsigned long a) +{ + return readl(a); +} + +#endif /* __SYSTEM_H */ + diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index e36b1da..b40c4df 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -10,89 +10,7 @@ #include "microwatt_soc.h" #include "io.h" #include "sdram.h" - -/* - * Core UART functions to implement for a port - */ - -static uint64_t potato_uart_base; - -#define PROC_FREQ 100000000 -#define UART_FREQ 115200 - -static uint8_t potato_uart_reg_read(int offset) -{ - return readb(potato_uart_base + offset); -} - -static void potato_uart_reg_write(int offset, uint8_t val) -{ - writeb(val, potato_uart_base + offset); -} - -static bool potato_uart_rx_empty(void) -{ - uint8_t val = potato_uart_reg_read(POTATO_CONSOLE_STATUS); - - return (val & POTATO_CONSOLE_STATUS_RX_EMPTY) != 0; -} - -static int potato_uart_tx_full(void) -{ - uint8_t val = potato_uart_reg_read(POTATO_CONSOLE_STATUS); - - return (val & POTATO_CONSOLE_STATUS_TX_FULL) != 0; -} - -static char potato_uart_read(void) -{ - return potato_uart_reg_read(POTATO_CONSOLE_RX); -} - -static void potato_uart_write(char c) -{ - potato_uart_reg_write(POTATO_CONSOLE_TX, c); -} - -static unsigned long potato_uart_divisor(unsigned long proc_freq, - unsigned long uart_freq) -{ - return proc_freq / (uart_freq * 16) - 1; -} - -void potato_uart_init(void) -{ - potato_uart_base = UART_BASE; - - potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, - potato_uart_divisor(PROC_FREQ, UART_FREQ)); -} - -int getchar(void) -{ - while (potato_uart_rx_empty()) - /* Do nothing */ ; - - return potato_uart_read(); -} - -int putchar(int c) -{ - while (potato_uart_tx_full()) - /* Do Nothing */; - - potato_uart_write(c); - return c; -} - -void putstr(const char *str, unsigned long len) -{ - for (unsigned long i = 0; i < len; i++) { - if (str[i] == '\n') - putchar('\r'); - putchar(str[i]); - } -} +#include "console.h" int _printf(const char *fmt, ...) { @@ -103,26 +21,33 @@ int _printf(const char *fmt, ...) va_start(ap, fmt); count = vsnprintf(buffer, sizeof(buffer), fmt, ap); va_end(ap); - putstr(buffer, count); + puts(buffer); return count; } -void flush_cpu_dcache(void) { } -void flush_cpu_icache(void) { } -void flush_l2_cache(void) { } +void flush_cpu_dcache(void) +{ +} + +void flush_cpu_icache(void) +{ + __asm__ volatile ("icbi 0,0; isync" : : : "memory"); +} void main(void) { unsigned long long ftr, val; int i; + /* Init the UART */ + potato_uart_init(); + /* * Let things settle ... not sure why but the UART is * not happy otherwise. The PLL might need to settle ? */ - potato_uart_init(); - for (i = 0; i < 100000; i++) - potato_uart_reg_read(POTATO_CONSOLE_STATUS); + for (i = 0; i < 10000; i++) + readb(UART_BASE + POTATO_CONSOLE_STATUS); printf("\n\nWelcome to Microwatt !\n\n"); /* TODO: Add core version information somewhere in syscon, possibly diff --git a/litedram/gen-src/wrapper-mw-init.vhdl b/litedram/gen-src/wrapper-mw-init.vhdl index 46ae4b1..f13edeb 100644 --- a/litedram/gen-src/wrapper-mw-init.vhdl +++ b/litedram/gen-src/wrapper-mw-init.vhdl @@ -25,7 +25,7 @@ entity litedram_wrapper is -- Wishbone ports: wb_in : in wishbone_master_out; wb_out : out wishbone_slave_out; - wb_is_csr : in std_ulogic; + wb_is_ctrl : in std_ulogic; wb_is_init : in std_ulogic; -- Init core serial debug @@ -58,32 +58,39 @@ end entity litedram_wrapper; architecture behaviour of litedram_wrapper is component litedram_core port ( - clk : in std_ulogic; - rst : in std_ulogic; - pll_locked : out std_ulogic; - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic; - init_done : out std_ulogic; - init_error : out std_ulogic; - user_clk : out std_ulogic; - user_rst : out std_ulogic; - csr_port0_adr : in std_ulogic_vector(13 downto 0); - csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(31 downto 0); - csr_port0_dat_r : out std_ulogic_vector(31 downto 0); + clk : in std_ulogic; + rst : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -114,18 +121,19 @@ architecture behaviour of litedram_wrapper is signal dram_user_reset : std_ulogic; - signal csr_port0_adr : std_ulogic_vector(13 downto 0); - signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); - signal csr_port_read_comb : std_ulogic_vector(63 downto 0); - signal csr_valid : std_ulogic; - signal csr_write_valid : std_ulogic; + signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); + signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); + signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0); + signal wb_ctrl_sel : std_ulogic_vector(3 downto 0); + signal wb_ctrl_cyc : std_ulogic; + signal wb_ctrl_stb : std_ulogic; + signal wb_ctrl_ack : std_ulogic; + signal wb_ctrl_we : std_ulogic; signal wb_init_in : wishbone_master_out; signal wb_init_out : wishbone_slave_out; - type state_t is (CMD, MWRITE, MREAD, CSR); + type state_t is (CMD, MWRITE, MREAD); signal state : state_t; constant INIT_RAM_SIZE : integer := 16384; @@ -192,7 +200,7 @@ begin ad3 <= wb_in.adr(3); -- DRAM data interface signals - user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) + user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_ctrl and not wb_is_init) when state = CMD else '0'; user_port0_cmd_we <= wb_in.we when state = CMD else '0'; user_port0_wdata_valid <= '1' when state = MWRITE else '0'; @@ -202,21 +210,21 @@ begin user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else "00000000" & wb_in.sel; - -- DRAM CSR interface signals. We only support access to the bottom byte - csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; - csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(31 downto 0); - csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; + -- DRAM ctrl interface signals + wb_ctrl_adr <= x"0000" & wb_in.adr(15 downto 2); + wb_ctrl_dat_w <= wb_in.dat(31 downto 0); + wb_ctrl_sel <= wb_in.sel(3 downto 0); + wb_ctrl_cyc <= wb_in.cyc and wb_is_ctrl; + wb_ctrl_stb <= wb_in.stb and wb_is_ctrl; + wb_ctrl_we <= wb_in.we; -- Wishbone out signals - wb_out.ack <= '1' when state = CSR else + wb_out.ack <= wb_ctrl_ack when wb_is_ctrl ='1' else wb_init_out.ack when wb_is_init = '1' else user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000" & csr_port0_dat_r; - wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else + wb_out.dat <= (x"00000000" & wb_ctrl_dat_r) when wb_is_ctrl = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(63 downto 0); @@ -239,9 +247,7 @@ begin else case state is when CMD => - if csr_valid = '1' then - state <= CSR; - elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then + if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then state <= MWRITE when wb_in.we = '1' else MREAD; end if; when MWRITE => @@ -252,8 +258,6 @@ begin if user_port0_rdata_valid = '1' then state <= CMD; end if; - when CSR => - state <= CMD; end case; end if; end if; @@ -283,10 +287,17 @@ begin init_error => init_error, user_clk => system_clk, user_rst => dram_user_reset, - csr_port0_adr => csr_port0_adr, - csr_port0_we => csr_port0_we, - csr_port0_dat_w => csr_port0_dat_w, - csr_port0_dat_r => csr_port0_dat_r, + wb_ctrl_adr => wb_ctrl_adr, + wb_ctrl_dat_w => wb_ctrl_dat_w, + wb_ctrl_dat_r => wb_ctrl_dat_r, + wb_ctrl_sel => wb_ctrl_sel, + wb_ctrl_cyc => wb_ctrl_cyc, + wb_ctrl_stb => wb_ctrl_stb, + wb_ctrl_ack => wb_ctrl_ack, + wb_ctrl_we => wb_ctrl_we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, user_port_native_0_cmd_valid => user_port0_cmd_valid, user_port_native_0_cmd_ready => user_port0_cmd_ready, user_port_native_0_cmd_we => user_port0_cmd_we, diff --git a/litedram/gen-src/wrapper-self-init.vhdl b/litedram/gen-src/wrapper-self-init.vhdl index 0664866..34e69e3 100644 --- a/litedram/gen-src/wrapper-self-init.vhdl +++ b/litedram/gen-src/wrapper-self-init.vhdl @@ -25,7 +25,7 @@ entity litedram_wrapper is -- Wishbone ports: wb_in : in wishbone_master_out; wb_out : out wishbone_slave_out; - wb_is_csr : in std_ulogic; + wb_is_ctrl : in std_ulogic; wb_is_init : in std_ulogic; -- Init core serial debug @@ -123,7 +123,7 @@ begin ad3 <= wb_in.adr(3); -- DRAM interface signals - user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) + user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_ctrl and not wb_is_init) when state = CMD else '0'; user_port0_cmd_we <= wb_in.we when state = CMD else '0'; user_port0_wdata_valid <= '1' when state = MWRITE else '0'; @@ -134,10 +134,10 @@ begin "00000000" & wb_in.sel; -- Wishbone out signals. CSR and init memory do nothing, just ack - wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else + wb_out.ack <= '1' when (wb_is_ctrl = '1' or wb_is_init = '1') else user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else + wb_out.dat <= (others => '0') when (wb_is_ctrl = '1' or wb_is_init = '1') else user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(63 downto 0); wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; diff --git a/litedram/generated/arty/litedram-wrapper.vhdl b/litedram/generated/arty/litedram-wrapper.vhdl index 46ae4b1..fd9f3bd 100644 --- a/litedram/generated/arty/litedram-wrapper.vhdl +++ b/litedram/generated/arty/litedram-wrapper.vhdl @@ -25,7 +25,7 @@ entity litedram_wrapper is -- Wishbone ports: wb_in : in wishbone_master_out; wb_out : out wishbone_slave_out; - wb_is_csr : in std_ulogic; + wb_is_ctrl : in std_ulogic; wb_is_init : in std_ulogic; -- Init core serial debug @@ -58,32 +58,39 @@ end entity litedram_wrapper; architecture behaviour of litedram_wrapper is component litedram_core port ( - clk : in std_ulogic; - rst : in std_ulogic; - pll_locked : out std_ulogic; - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic; - init_done : out std_ulogic; - init_error : out std_ulogic; - user_clk : out std_ulogic; - user_rst : out std_ulogic; - csr_port0_adr : in std_ulogic_vector(13 downto 0); - csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(31 downto 0); - csr_port0_dat_r : out std_ulogic_vector(31 downto 0); + clk : in std_ulogic; + rst : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -112,20 +119,19 @@ architecture behaviour of litedram_wrapper is signal ad3 : std_ulogic; - signal dram_user_reset : std_ulogic; - - signal csr_port0_adr : std_ulogic_vector(13 downto 0); - signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); - signal csr_port_read_comb : std_ulogic_vector(63 downto 0); - signal csr_valid : std_ulogic; - signal csr_write_valid : std_ulogic; + signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); + signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); + signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0); + signal wb_ctrl_sel : std_ulogic_vector(3 downto 0); + signal wb_ctrl_cyc : std_ulogic; + signal wb_ctrl_stb : std_ulogic; + signal wb_ctrl_ack : std_ulogic; + signal wb_ctrl_we : std_ulogic; signal wb_init_in : wishbone_master_out; signal wb_init_out : wishbone_slave_out; - type state_t is (CMD, MWRITE, MREAD, CSR); + type state_t is (CMD, MWRITE, MREAD); signal state : state_t; constant INIT_RAM_SIZE : integer := 16384; @@ -192,7 +198,7 @@ begin ad3 <= wb_in.adr(3); -- DRAM data interface signals - user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) + user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_ctrl and not wb_is_init) when state = CMD else '0'; user_port0_cmd_we <= wb_in.we when state = CMD else '0'; user_port0_wdata_valid <= '1' when state = MWRITE else '0'; @@ -202,31 +208,28 @@ begin user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else "00000000" & wb_in.sel; - -- DRAM CSR interface signals. We only support access to the bottom byte - csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; - csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(31 downto 0); - csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; + -- DRAM ctrl interface signals + wb_ctrl_adr <= x"0000" & wb_in.adr(15 downto 2); + wb_ctrl_dat_w <= wb_in.dat(31 downto 0); + wb_ctrl_sel <= wb_in.sel(3 downto 0); + wb_ctrl_cyc <= wb_in.cyc and wb_is_ctrl; + wb_ctrl_stb <= wb_in.stb and wb_is_ctrl; + wb_ctrl_we <= wb_in.we; -- Wishbone out signals - wb_out.ack <= '1' when state = CSR else + wb_out.ack <= wb_ctrl_ack when wb_is_ctrl ='1' else wb_init_out.ack when wb_is_init = '1' else user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000" & csr_port0_dat_r; - wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else + wb_out.dat <= (x"00000000" & wb_ctrl_dat_r) when wb_is_ctrl = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(63 downto 0); -- We don't do pipelining yet. wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - -- Reset ignored, the reset controller use the pll lock signal, - -- and alternate core reset address set when DRAM is not initialized. - -- - system_reset <= '0'; + -- Use alternate core reset address set when DRAM is not initialized. core_alt_reset <= not init_done; -- State machine @@ -234,14 +237,12 @@ begin begin if rising_edge(system_clk) then - if dram_user_reset = '1' then + if system_reset = '1' then state <= CMD; else case state is when CMD => - if csr_valid = '1' then - state <= CSR; - elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then + if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then state <= MWRITE when wb_in.we = '1' else MREAD; end if; when MWRITE => @@ -252,8 +253,6 @@ begin if user_port0_rdata_valid = '1' then state <= CMD; end if; - when CSR => - state <= CMD; end case; end if; end if; @@ -282,11 +281,18 @@ begin init_done => init_done, init_error => init_error, user_clk => system_clk, - user_rst => dram_user_reset, - csr_port0_adr => csr_port0_adr, - csr_port0_we => csr_port0_we, - csr_port0_dat_w => csr_port0_dat_w, - csr_port0_dat_r => csr_port0_dat_r, + user_rst => system_reset, + wb_ctrl_adr => wb_ctrl_adr, + wb_ctrl_dat_w => wb_ctrl_dat_w, + wb_ctrl_dat_r => wb_ctrl_dat_r, + wb_ctrl_sel => wb_ctrl_sel, + wb_ctrl_cyc => wb_ctrl_cyc, + wb_ctrl_stb => wb_ctrl_stb, + wb_ctrl_ack => wb_ctrl_ack, + wb_ctrl_we => wb_ctrl_we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, user_port_native_0_cmd_valid => user_port0_cmd_valid, user_port_native_0_cmd_ready => user_port0_cmd_ready, user_port_native_0_cmd_we => user_port0_cmd_we, diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 4f7ad0f..508f707 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ffff782107c6 3d80000060213f00 798c07c6618c0000 -618c1168658cffff +618c108c658cffff 4e8004217d8903a6 0000000048000002 0000000000000000 @@ -510,124 +510,113 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -38429e003c4c0001 -600000003d20c000 -7929002061292000 -3d40c000f92280a8 -614a201839200035 -7c0004ac794a0020 -4e8000207d2057aa -0000000000000000 -3c4c000100000000 -6000000038429dbc -39290010e92280a8 -7d204eaa7c0004ac -4082ffe871290008 -e92280a860000000 -7c604faa7c0004ac -000000004e800020 -0000000000000000 -38429d783c4c0001 +38429f003c4c0001 fbc1fff07c0802a6 -7fc32214fbe1fff8 -f80100107c7f1b78 -7fbff040f821ffd1 -38210030409e000c -893f000048001ab4 -409e000c2f89000a -4bffff813860000d -3bff0001887f0000 -4bffffd04bffff75 +f8010010fbe1fff8 +3be10020f821fe91 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+7d455378993e0000 +39290001e9210060 +4bfffb24f9210060 +0100000000000000 +f9c1ff7000001280 +fa01ff80f9e1ff78 +fa41ff90fa21ff88 +fa81ffa0fa61ff98 +fac1ffb0faa1ffa8 +fb01ffc0fae1ffb8 +fb41ffd0fb21ffc8 +fb81ffe0fb61ffd8 +fbc1fff0fba1ffe8 +f8010010fbe1fff8 +e9c1ff704e800020 +ea01ff80e9e1ff78 +ea41ff90ea21ff88 +ea81ffa0ea61ff98 +eac1ffb0eaa1ffa8 +eb01ffc0eae1ffb8 +eb41ffd0eb21ffc8 +eb81ffe0eb61ffd8 +eba1ffe8e8010010 +ebc1fff07c0803a6 +4e800020ebe1fff8 +e8010010ebc1fff0 +7c0803a6ebe1fff8 +000000004e800020 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1415,9 +1447,9 @@ ebe1fff8e8010010 203a4b4c43202020 7a484d20646c6c25 000000000000000a -6564346264343964 +6138393331393333 0000000000000000 -0036656663396364 +0033306536316430 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1469,12 +1501,13 @@ ebe1fff8e8010010 00000a2e2e2e4d41 76656c2064616552 000a3a676e696c65 -642562202c64256d -00000000007c203a +302562202c64256d +0000007c203a6432 0000000000006425 000000000000207c 256d203a74736562 -0020642562202c64 +6432302562202c64 +0000000000000020 0000000078323025 6f6e204d41524453 207265646e752077 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 18cb7f1..991adbd 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:11 +// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 09:40:26 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -22,10 +22,17 @@ module litedram_core( output wire ddram_reset_n, output wire init_done, output wire init_error, - input wire [13:0] csr_port0_adr, - input wire csr_port0_we, - input wire [31:0] csr_port0_dat_w, - output wire [31:0] csr_port0_dat_r, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, @@ -41,6 +48,21 @@ module litedram_core( output wire [127:0] user_port_native_0_rdata_data ); +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +wire [31:0] litedramcore_dat_w; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +wire [31:0] litedramcore_wishbone_dat_r; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; @@ -185,8 +207,8 @@ wire a7ddrphy_dq_t0; wire [7:0] a7ddrphy_dq_i_data0; wire [7:0] a7ddrphy_bitslip0_i; reg [7:0] a7ddrphy_bitslip0_o = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value = 3'd0; -reg [15:0] a7ddrphy_bitslip0_r = 16'd0; +reg [3:0] a7ddrphy_bitslip0_value = 4'd0; +reg [23:0] a7ddrphy_bitslip0_r = 24'd0; wire a7ddrphy_dq_o_nodelay1; wire a7ddrphy_dq_i_nodelay1; wire a7ddrphy_dq_i_delayed1; @@ -194,8 +216,8 @@ wire a7ddrphy_dq_t1; wire [7:0] a7ddrphy_dq_i_data1; wire [7:0] a7ddrphy_bitslip1_i; reg [7:0] a7ddrphy_bitslip1_o = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value = 3'd0; -reg [15:0] a7ddrphy_bitslip1_r = 16'd0; +reg [3:0] a7ddrphy_bitslip1_value = 4'd0; +reg [23:0] a7ddrphy_bitslip1_r = 24'd0; wire a7ddrphy_dq_o_nodelay2; wire a7ddrphy_dq_i_nodelay2; wire a7ddrphy_dq_i_delayed2; @@ -203,8 +225,8 @@ wire a7ddrphy_dq_t2; wire [7:0] a7ddrphy_dq_i_data2; wire [7:0] a7ddrphy_bitslip2_i; reg [7:0] a7ddrphy_bitslip2_o = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value = 3'd0; -reg [15:0] a7ddrphy_bitslip2_r = 16'd0; +reg [3:0] a7ddrphy_bitslip2_value = 4'd0; +reg [23:0] a7ddrphy_bitslip2_r = 24'd0; wire a7ddrphy_dq_o_nodelay3; wire a7ddrphy_dq_i_nodelay3; wire a7ddrphy_dq_i_delayed3; @@ -212,8 +234,8 @@ wire a7ddrphy_dq_t3; wire [7:0] a7ddrphy_dq_i_data3; wire [7:0] a7ddrphy_bitslip3_i; reg [7:0] a7ddrphy_bitslip3_o = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value = 3'd0; -reg [15:0] a7ddrphy_bitslip3_r = 16'd0; +reg [3:0] a7ddrphy_bitslip3_value = 4'd0; +reg [23:0] a7ddrphy_bitslip3_r = 24'd0; wire a7ddrphy_dq_o_nodelay4; wire a7ddrphy_dq_i_nodelay4; wire a7ddrphy_dq_i_delayed4; @@ -221,8 +243,8 @@ wire a7ddrphy_dq_t4; wire [7:0] a7ddrphy_dq_i_data4; wire [7:0] a7ddrphy_bitslip4_i; reg [7:0] a7ddrphy_bitslip4_o = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value = 3'd0; -reg [15:0] a7ddrphy_bitslip4_r = 16'd0; +reg [3:0] a7ddrphy_bitslip4_value = 4'd0; +reg [23:0] a7ddrphy_bitslip4_r = 24'd0; wire a7ddrphy_dq_o_nodelay5; wire a7ddrphy_dq_i_nodelay5; wire a7ddrphy_dq_i_delayed5; @@ -230,8 +252,8 @@ wire a7ddrphy_dq_t5; wire [7:0] a7ddrphy_dq_i_data5; wire [7:0] a7ddrphy_bitslip5_i; reg [7:0] a7ddrphy_bitslip5_o = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value = 3'd0; -reg [15:0] a7ddrphy_bitslip5_r = 16'd0; +reg [3:0] a7ddrphy_bitslip5_value = 4'd0; +reg [23:0] a7ddrphy_bitslip5_r = 24'd0; wire a7ddrphy_dq_o_nodelay6; wire a7ddrphy_dq_i_nodelay6; wire a7ddrphy_dq_i_delayed6; @@ -239,8 +261,8 @@ wire a7ddrphy_dq_t6; wire [7:0] a7ddrphy_dq_i_data6; wire [7:0] a7ddrphy_bitslip6_i; reg [7:0] a7ddrphy_bitslip6_o = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value = 3'd0; -reg [15:0] a7ddrphy_bitslip6_r = 16'd0; +reg [3:0] a7ddrphy_bitslip6_value = 4'd0; +reg [23:0] a7ddrphy_bitslip6_r = 24'd0; wire a7ddrphy_dq_o_nodelay7; wire a7ddrphy_dq_i_nodelay7; wire a7ddrphy_dq_i_delayed7; @@ -248,8 +270,8 @@ wire a7ddrphy_dq_t7; wire [7:0] a7ddrphy_dq_i_data7; wire [7:0] a7ddrphy_bitslip7_i; reg [7:0] a7ddrphy_bitslip7_o = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value = 3'd0; -reg [15:0] a7ddrphy_bitslip7_r = 16'd0; +reg [3:0] a7ddrphy_bitslip7_value = 4'd0; +reg [23:0] a7ddrphy_bitslip7_r = 24'd0; wire a7ddrphy_dq_o_nodelay8; wire a7ddrphy_dq_i_nodelay8; wire a7ddrphy_dq_i_delayed8; @@ -257,8 +279,8 @@ wire a7ddrphy_dq_t8; wire [7:0] a7ddrphy_dq_i_data8; wire [7:0] a7ddrphy_bitslip8_i; reg [7:0] a7ddrphy_bitslip8_o = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value = 3'd0; -reg [15:0] a7ddrphy_bitslip8_r = 16'd0; +reg [3:0] a7ddrphy_bitslip8_value = 4'd0; +reg [23:0] a7ddrphy_bitslip8_r = 24'd0; wire a7ddrphy_dq_o_nodelay9; wire a7ddrphy_dq_i_nodelay9; wire a7ddrphy_dq_i_delayed9; @@ -266,8 +288,8 @@ wire a7ddrphy_dq_t9; wire [7:0] a7ddrphy_dq_i_data9; wire [7:0] a7ddrphy_bitslip9_i; reg [7:0] a7ddrphy_bitslip9_o = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value = 3'd0; -reg [15:0] a7ddrphy_bitslip9_r = 16'd0; +reg [3:0] a7ddrphy_bitslip9_value = 4'd0; +reg [23:0] a7ddrphy_bitslip9_r = 24'd0; wire a7ddrphy_dq_o_nodelay10; wire a7ddrphy_dq_i_nodelay10; wire a7ddrphy_dq_i_delayed10; @@ -275,8 +297,8 @@ wire a7ddrphy_dq_t10; wire [7:0] a7ddrphy_dq_i_data10; wire [7:0] a7ddrphy_bitslip10_i; reg [7:0] a7ddrphy_bitslip10_o = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value = 3'd0; -reg [15:0] a7ddrphy_bitslip10_r = 16'd0; +reg [3:0] a7ddrphy_bitslip10_value = 4'd0; +reg [23:0] a7ddrphy_bitslip10_r = 24'd0; wire a7ddrphy_dq_o_nodelay11; wire a7ddrphy_dq_i_nodelay11; wire a7ddrphy_dq_i_delayed11; @@ -284,8 +306,8 @@ wire a7ddrphy_dq_t11; wire [7:0] a7ddrphy_dq_i_data11; wire [7:0] a7ddrphy_bitslip11_i; reg [7:0] a7ddrphy_bitslip11_o = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value = 3'd0; -reg [15:0] a7ddrphy_bitslip11_r = 16'd0; +reg [3:0] a7ddrphy_bitslip11_value = 4'd0; +reg [23:0] a7ddrphy_bitslip11_r = 24'd0; wire a7ddrphy_dq_o_nodelay12; wire a7ddrphy_dq_i_nodelay12; wire a7ddrphy_dq_i_delayed12; @@ -293,8 +315,8 @@ wire a7ddrphy_dq_t12; wire [7:0] a7ddrphy_dq_i_data12; wire [7:0] a7ddrphy_bitslip12_i; reg [7:0] a7ddrphy_bitslip12_o = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value = 3'd0; -reg [15:0] a7ddrphy_bitslip12_r = 16'd0; +reg [3:0] a7ddrphy_bitslip12_value = 4'd0; +reg [23:0] a7ddrphy_bitslip12_r = 24'd0; wire a7ddrphy_dq_o_nodelay13; wire a7ddrphy_dq_i_nodelay13; wire a7ddrphy_dq_i_delayed13; @@ -302,8 +324,8 @@ wire a7ddrphy_dq_t13; wire [7:0] a7ddrphy_dq_i_data13; wire [7:0] a7ddrphy_bitslip13_i; reg [7:0] a7ddrphy_bitslip13_o = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value = 3'd0; -reg [15:0] a7ddrphy_bitslip13_r = 16'd0; +reg [3:0] a7ddrphy_bitslip13_value = 4'd0; +reg [23:0] a7ddrphy_bitslip13_r = 24'd0; wire a7ddrphy_dq_o_nodelay14; wire a7ddrphy_dq_i_nodelay14; wire a7ddrphy_dq_i_delayed14; @@ -311,8 +333,8 @@ wire a7ddrphy_dq_t14; wire [7:0] a7ddrphy_dq_i_data14; wire [7:0] a7ddrphy_bitslip14_i; reg [7:0] a7ddrphy_bitslip14_o = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value = 3'd0; -reg [15:0] a7ddrphy_bitslip14_r = 16'd0; +reg [3:0] a7ddrphy_bitslip14_value = 4'd0; +reg [23:0] a7ddrphy_bitslip14_r = 24'd0; wire a7ddrphy_dq_o_nodelay15; wire a7ddrphy_dq_i_nodelay15; wire a7ddrphy_dq_i_delayed15; @@ -320,8 +342,8 @@ wire a7ddrphy_dq_t15; wire [7:0] a7ddrphy_dq_i_data15; wire [7:0] a7ddrphy_bitslip15_i; reg [7:0] a7ddrphy_bitslip15_o = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value = 3'd0; -reg [15:0] a7ddrphy_bitslip15_r = 16'd0; +reg [3:0] a7ddrphy_bitslip15_value = 4'd0; +reg [23:0] a7ddrphy_bitslip15_r = 24'd0; wire [7:0] a7ddrphy_rddata_en; reg [7:0] a7ddrphy_rddata_en_last = 8'd0; wire [3:0] a7ddrphy_wrdata_en; @@ -1483,10 +1505,17 @@ reg init_done_storage = 1'd0; reg init_done_re = 1'd0; reg init_error_storage = 1'd0; reg init_error_re = 1'd0; -wire [13:0] csr_port_adr; -wire csr_port_we; -wire [31:0] csr_port_dat_w; -wire [31:0] csr_port_dat_r; +wire [29:0] wb_bus_adr; +wire [31:0] wb_bus_dat_w; +wire [31:0] wb_bus_dat_r; +wire [3:0] wb_bus_sel; +wire wb_bus_cyc; +wire wb_bus_stb; +wire wb_bus_ack; +wire wb_bus_we; +wire [2:0] wb_bus_cti; +wire [1:0] wb_bus_bte; +wire wb_bus_err; wire user_port_cmd_valid; wire user_port_cmd_ready; wire user_port_cmd_payload_we; @@ -1498,6 +1527,8 @@ wire [15:0] user_port_wdata_payload_we; wire user_port_rdata_valid; wire user_port_rdata_ready; wire [127:0] user_port_rdata_payload_data; +reg state = 1'd0; +reg next_state = 1'd0; wire pll_fb0; wire pll_fb1; reg [1:0] refresher_state = 2'd0; @@ -1774,10 +1805,17 @@ initial dummy_s <= 1'd0; // synthesis translate_on assign init_done = init_done_storage; assign init_error = init_error_storage; -assign csr_port_adr = csr_port0_adr; -assign csr_port_we = csr_port0_we; -assign csr_port_dat_w = csr_port0_dat_w; -assign csr_port0_dat_r = csr_port_dat_r; +assign wb_bus_adr = wb_ctrl_adr; +assign wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_bus_dat_r; +assign wb_bus_sel = wb_ctrl_sel; +assign wb_bus_cyc = wb_ctrl_cyc; +assign wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = wb_bus_ack; +assign wb_bus_we = wb_ctrl_we; +assign wb_bus_cti = wb_ctrl_cti; +assign wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; assign user_port_cmd_valid = user_port_native_0_cmd_valid; @@ -1791,6 +1829,84 @@ assign user_port_wdata_payload_data = user_port_native_0_wdata_data; assign user_port_native_0_rdata_valid = user_port_rdata_valid; assign user_port_rdata_ready = user_port_native_0_rdata_ready; assign user_port_native_0_rdata_data = user_port_rdata_payload_data; +assign litedramcore_dat_w = litedramcore_wishbone_dat_w; +assign litedramcore_wishbone_dat_r = litedramcore_dat_r; + +// synthesis translate_off +reg dummy_d; +// synthesis translate_on +always @(*) begin + next_state <= 1'd0; + next_state <= state; + case (state) + 1'd1: begin + next_state <= 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + next_state <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_1; +// synthesis translate_on +always @(*) begin + litedramcore_wishbone_ack <= 1'd0; + case (state) + 1'd1: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_1 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_2; +// synthesis translate_on +always @(*) begin + litedramcore_adr <= 14'd0; + case (state) + 1'd1: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr <= litedramcore_wishbone_adr; + end + end + endcase +// synthesis translate_off + dummy_d_2 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_3; +// synthesis translate_on +always @(*) begin + litedramcore_we <= 1'd0; + case (state) + 1'd1: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we <= litedramcore_wishbone_we; + end + end + endcase +// synthesis translate_off + dummy_d_3 = dummy_s; +// synthesis translate_on +end assign sys_pll_reset = rst; assign pll_locked = sys_pll_locked; assign iodelay_pll_reset = rst; @@ -1803,7 +1919,7 @@ assign iodelay_clk = s7pll1_clkout_buf; assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0; // synthesis translate_off -reg dummy_d; +reg dummy_d_4; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p0_rddata <= 32'd0; @@ -1840,12 +1956,12 @@ always @(*) begin a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0]; a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1]; // synthesis translate_off - dummy_d = dummy_s; + dummy_d_4 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_1; +reg dummy_d_5; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p1_rddata <= 32'd0; @@ -1882,12 +1998,12 @@ always @(*) begin a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2]; a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3]; // synthesis translate_off - dummy_d_1 = dummy_s; + dummy_d_5 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_2; +reg dummy_d_6; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p2_rddata <= 32'd0; @@ -1924,12 +2040,12 @@ always @(*) begin a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4]; a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5]; // synthesis translate_off - dummy_d_2 = dummy_s; + dummy_d_6 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_3; +reg dummy_d_7; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p3_rddata <= 32'd0; @@ -1966,7 +2082,7 @@ always @(*) begin a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6]; a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7]; // synthesis translate_off - dummy_d_3 = dummy_s; + dummy_d_7 = dummy_s; // synthesis translate_on end assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1; @@ -1989,7 +2105,7 @@ assign a7ddrphy_wrdata_en = {a7ddrphy_wrdata_en_last, a7ddrphy_dfi_p3_wrdata_en} assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2]; // synthesis translate_off -reg dummy_d_4; +reg dummy_d_8; // synthesis translate_on always @(*) begin a7ddrphy_dqs_oe <= 1'd0; @@ -1999,14 +2115,14 @@ always @(*) begin a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; end // synthesis translate_off - dummy_d_4 = dummy_s; + dummy_d_8 = dummy_s; // synthesis translate_on end assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2])); assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2])); // synthesis translate_off -reg dummy_d_5; +reg dummy_d_9; // synthesis translate_on always @(*) begin a7ddrphy_dqspattern_o0 <= 8'd0; @@ -2024,12 +2140,12 @@ always @(*) begin end end // synthesis translate_off - dummy_d_5 = dummy_s; + dummy_d_9 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_6; +reg dummy_d_10; // synthesis translate_on always @(*) begin a7ddrphy_bitslip0_o <= 8'd0; @@ -2058,14 +2174,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[22:15]; + end endcase // synthesis translate_off - dummy_d_6 = dummy_s; + dummy_d_10 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_7; +reg dummy_d_11; // synthesis translate_on always @(*) begin a7ddrphy_bitslip1_o <= 8'd0; @@ -2094,14 +2234,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[22:15]; + end endcase // synthesis translate_off - dummy_d_7 = dummy_s; + dummy_d_11 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_8; +reg dummy_d_12; // synthesis translate_on always @(*) begin a7ddrphy_bitslip2_o <= 8'd0; @@ -2130,14 +2294,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[22:15]; + end endcase // synthesis translate_off - dummy_d_8 = dummy_s; + dummy_d_12 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_9; +reg dummy_d_13; // synthesis translate_on always @(*) begin a7ddrphy_bitslip3_o <= 8'd0; @@ -2166,14 +2354,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[22:15]; + end endcase // synthesis translate_off - dummy_d_9 = dummy_s; + dummy_d_13 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_10; +reg dummy_d_14; // synthesis translate_on always @(*) begin a7ddrphy_bitslip4_o <= 8'd0; @@ -2202,14 +2414,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[22:15]; + end endcase // synthesis translate_off - dummy_d_10 = dummy_s; + dummy_d_14 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_11; +reg dummy_d_15; // synthesis translate_on always @(*) begin a7ddrphy_bitslip5_o <= 8'd0; @@ -2238,14 +2474,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[22:15]; + end endcase // synthesis translate_off - dummy_d_11 = dummy_s; + dummy_d_15 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_12; +reg dummy_d_16; // synthesis translate_on always @(*) begin a7ddrphy_bitslip6_o <= 8'd0; @@ -2274,14 +2534,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[22:15]; + end endcase // synthesis translate_off - dummy_d_12 = dummy_s; + dummy_d_16 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_13; +reg dummy_d_17; // synthesis translate_on always @(*) begin a7ddrphy_bitslip7_o <= 8'd0; @@ -2310,14 +2594,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[22:15]; + end endcase // synthesis translate_off - dummy_d_13 = dummy_s; + dummy_d_17 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_14; +reg dummy_d_18; // synthesis translate_on always @(*) begin a7ddrphy_bitslip8_o <= 8'd0; @@ -2346,14 +2654,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[22:15]; + end endcase // synthesis translate_off - dummy_d_14 = dummy_s; + dummy_d_18 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_15; +reg dummy_d_19; // synthesis translate_on always @(*) begin a7ddrphy_bitslip9_o <= 8'd0; @@ -2382,14 +2714,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[22:15]; + end endcase // synthesis translate_off - dummy_d_15 = dummy_s; + dummy_d_19 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_16; +reg dummy_d_20; // synthesis translate_on always @(*) begin a7ddrphy_bitslip10_o <= 8'd0; @@ -2418,14 +2774,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[22:15]; + end endcase // synthesis translate_off - dummy_d_16 = dummy_s; + dummy_d_20 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_17; +reg dummy_d_21; // synthesis translate_on always @(*) begin a7ddrphy_bitslip11_o <= 8'd0; @@ -2454,14 +2834,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7]; end - endcase -// synthesis translate_off - dummy_d_17 = dummy_s; -// synthesis translate_on -end - + 4'd8: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[22:15]; + end + endcase // synthesis translate_off -reg dummy_d_18; + dummy_d_21 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_22; // synthesis translate_on always @(*) begin a7ddrphy_bitslip12_o <= 8'd0; @@ -2490,14 +2894,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[22:15]; + end endcase // synthesis translate_off - dummy_d_18 = dummy_s; + dummy_d_22 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_19; +reg dummy_d_23; // synthesis translate_on always @(*) begin a7ddrphy_bitslip13_o <= 8'd0; @@ -2526,14 +2954,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[22:15]; + end endcase // synthesis translate_off - dummy_d_19 = dummy_s; + dummy_d_23 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_20; +reg dummy_d_24; // synthesis translate_on always @(*) begin a7ddrphy_bitslip14_o <= 8'd0; @@ -2562,14 +3014,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[22:15]; + end endcase // synthesis translate_off - dummy_d_20 = dummy_s; + dummy_d_24 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_21; +reg dummy_d_25; // synthesis translate_on always @(*) begin a7ddrphy_bitslip15_o <= 8'd0; @@ -2598,9 +3074,33 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[22:15]; + end endcase // synthesis translate_off - dummy_d_21 = dummy_s; + dummy_d_25 = dummy_s; // synthesis translate_on end assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; @@ -2732,75 +3232,15 @@ assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; -// synthesis translate_off -reg dummy_d_22; -// synthesis translate_on -always @(*) begin - litedramcore_master_p3_cke <= 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; - end else begin - litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; - end -// synthesis translate_off - dummy_d_22 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_23; -// synthesis translate_on -always @(*) begin - litedramcore_master_p3_odt <= 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; - end else begin - litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; - end -// synthesis translate_off - dummy_d_23 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_24; -// synthesis translate_on -always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; - end else begin - litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; - end -// synthesis translate_off - dummy_d_24 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_25; -// synthesis translate_on -always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; - end else begin - litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; - end -// synthesis translate_off - dummy_d_25 = dummy_s; -// synthesis translate_on -end - // synthesis translate_off reg dummy_d_26; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; + litedramcore_master_p2_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; end else begin - litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; + litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_26 = dummy_s; @@ -2811,10 +3251,11 @@ end reg dummy_d_27; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata <= 32'd0; + litedramcore_master_p2_odt <= 1'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; end else begin - litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_27 = dummy_s; @@ -2825,11 +3266,11 @@ end reg dummy_d_28; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; + litedramcore_master_p2_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; + litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_28 = dummy_s; @@ -2840,10 +3281,11 @@ end reg dummy_d_29; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata_valid <= 1'd0; + litedramcore_master_p2_act_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; end else begin - litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_29 = dummy_s; @@ -2854,11 +3296,11 @@ end reg dummy_d_30; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; + litedramcore_master_p2_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; + litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_30 = dummy_s; @@ -2869,11 +3311,10 @@ end reg dummy_d_31; // synthesis translate_on always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; + litedramcore_inti_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; end else begin - litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; + litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_31 = dummy_s; @@ -2884,11 +3325,11 @@ end reg dummy_d_32; // synthesis translate_on always @(*) begin - litedramcore_master_p0_address <= 14'd0; + litedramcore_master_p2_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; end else begin - litedramcore_master_p0_address <= litedramcore_inti_p0_address; + litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_32 = dummy_s; @@ -2899,11 +3340,10 @@ end reg dummy_d_33; // synthesis translate_on always @(*) begin - litedramcore_master_p0_bank <= 3'd0; + litedramcore_inti_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; end else begin - litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; + litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_33 = dummy_s; @@ -2914,11 +3354,11 @@ end reg dummy_d_34; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; + litedramcore_master_p2_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; end else begin - litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; + litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_34 = dummy_s; @@ -2929,11 +3369,11 @@ end reg dummy_d_35; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; + litedramcore_master_p2_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; end else begin - litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; + litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_35 = dummy_s; @@ -2944,10 +3384,11 @@ end reg dummy_d_36; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; + litedramcore_master_p3_address <= 14'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_master_p3_address <= litedramcore_slave_p3_address; end else begin + litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_36 = dummy_s; @@ -2958,11 +3399,11 @@ end reg dummy_d_37; // synthesis translate_on always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; + litedramcore_master_p3_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; end else begin - litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; + litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_37 = dummy_s; @@ -2973,10 +3414,11 @@ end reg dummy_d_38; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; + litedramcore_master_p3_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; end else begin + litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_38 = dummy_s; @@ -2987,11 +3429,11 @@ end reg dummy_d_39; // synthesis translate_on always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; + litedramcore_master_p3_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; end else begin - litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; + litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_39 = dummy_s; @@ -3002,11 +3444,11 @@ end reg dummy_d_40; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cke <= 1'd0; + litedramcore_master_p3_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; end else begin - litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; + litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_40 = dummy_s; @@ -3017,11 +3459,10 @@ end reg dummy_d_41; // synthesis translate_on always @(*) begin - litedramcore_master_p0_odt <= 1'd0; + litedramcore_slave_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; end else begin - litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_41 = dummy_s; @@ -3032,11 +3473,11 @@ end reg dummy_d_42; // synthesis translate_on always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; + litedramcore_master_p3_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; end else begin - litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; + litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_42 = dummy_s; @@ -3047,11 +3488,10 @@ end reg dummy_d_43; // synthesis translate_on always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; + litedramcore_slave_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end else begin - litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_43 = dummy_s; @@ -3062,11 +3502,11 @@ end reg dummy_d_44; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; + litedramcore_master_p3_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; end else begin - litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; + litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; end // synthesis translate_off dummy_d_44 = dummy_s; @@ -3077,10 +3517,11 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata <= 32'd0; + litedramcore_master_p3_odt <= 1'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; end else begin - litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; + litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -3091,11 +3532,11 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; + litedramcore_master_p3_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; + litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -3106,10 +3547,11 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata_valid <= 1'd0; + litedramcore_master_p3_act_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; end else begin - litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -3120,11 +3562,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; + litedramcore_master_p3_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; + litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -3135,11 +3577,10 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; + litedramcore_inti_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; end else begin - litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; + litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -3150,11 +3591,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - litedramcore_master_p1_address <= 14'd0; + litedramcore_master_p3_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; end else begin - litedramcore_master_p1_address <= litedramcore_inti_p1_address; + litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -3165,11 +3606,10 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - litedramcore_master_p1_bank <= 3'd0; + litedramcore_inti_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; end else begin - litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; + litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -3180,11 +3620,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; + litedramcore_master_p3_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; end else begin - litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; + litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -3195,11 +3635,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; + litedramcore_master_p3_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; end else begin - litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; + litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -3210,11 +3650,11 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; + litedramcore_master_p0_address <= 14'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + litedramcore_master_p0_address <= litedramcore_slave_p0_address; end else begin - litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; + litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -3225,10 +3665,11 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; + litedramcore_master_p0_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; end else begin + litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -3239,11 +3680,11 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; + litedramcore_master_p0_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; end else begin - litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; + litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -3254,10 +3695,11 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; + litedramcore_master_p0_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; end else begin + litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_57 = dummy_s; @@ -3268,11 +3710,10 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cke <= 1'd0; + litedramcore_slave_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; end else begin - litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -3283,11 +3724,11 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - litedramcore_master_p1_odt <= 1'd0; + litedramcore_master_p0_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; end else begin - litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; + litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; end // synthesis translate_off dummy_d_59 = dummy_s; @@ -3298,11 +3739,10 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; + litedramcore_slave_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end else begin - litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -3313,11 +3753,11 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; + litedramcore_master_p0_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; end else begin - litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; + litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off dummy_d_61 = dummy_s; @@ -3328,11 +3768,11 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; + litedramcore_master_p0_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; end else begin - litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; + litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -3343,10 +3783,11 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata <= 32'd0; + litedramcore_master_p0_odt <= 1'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; end else begin - litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; + litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -3357,11 +3798,11 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; + litedramcore_master_p0_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; + litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -3372,10 +3813,11 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata_valid <= 1'd0; + litedramcore_master_p0_act_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; end else begin - litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -3386,11 +3828,11 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; + litedramcore_master_p0_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; + litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -3401,11 +3843,10 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; + litedramcore_inti_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; end else begin - litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; + litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -3416,10 +3857,11 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; + litedramcore_master_p0_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -3430,11 +3872,10 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - litedramcore_master_p2_address <= 14'd0; + litedramcore_inti_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; end else begin - litedramcore_master_p2_address <= litedramcore_inti_p2_address; + litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -3445,11 +3886,11 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - litedramcore_master_p2_bank <= 3'd0; + litedramcore_master_p0_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; end else begin - litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; + litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -3460,11 +3901,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; + litedramcore_master_p0_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; end else begin - litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; + litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -3475,11 +3916,11 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; + litedramcore_master_p1_address <= 14'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + litedramcore_master_p1_address <= litedramcore_slave_p1_address; end else begin - litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; + litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -3490,10 +3931,11 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; + litedramcore_master_p1_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; end else begin + litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -3504,11 +3946,11 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; + litedramcore_master_p1_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; end else begin - litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; + litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -3533,11 +3975,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; + litedramcore_master_p1_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; end else begin - litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; + litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -3548,10 +3990,11 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; + litedramcore_master_p1_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; end else begin + litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_77 = dummy_s; @@ -3562,11 +4005,10 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cke <= 1'd0; + litedramcore_slave_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end else begin - litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -3577,11 +4019,11 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - litedramcore_master_p2_odt <= 1'd0; + litedramcore_master_p1_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; end else begin - litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; + litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_79 = dummy_s; @@ -3592,11 +4034,10 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; + litedramcore_slave_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end else begin - litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -3607,11 +4048,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; + litedramcore_master_p1_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; end else begin - litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; + litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -3622,11 +4063,11 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; + litedramcore_master_p1_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; end else begin - litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; + litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -3637,10 +4078,10 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata <= 32'd0; + litedramcore_slave_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end else begin - litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -3651,11 +4092,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; + litedramcore_master_p1_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; + litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -3666,10 +4107,11 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata_valid <= 1'd0; + litedramcore_master_p1_act_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; end else begin - litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -3680,11 +4122,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; + litedramcore_master_p1_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; + litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -3695,11 +4137,10 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; + litedramcore_inti_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; end else begin - litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; + litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -3710,11 +4151,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - litedramcore_master_p3_address <= 14'd0; + litedramcore_master_p1_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; end else begin - litedramcore_master_p3_address <= litedramcore_inti_p3_address; + litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -3725,11 +4166,10 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - litedramcore_master_p3_bank <= 3'd0; + litedramcore_inti_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; end else begin - litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; + litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -3740,11 +4180,11 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; + litedramcore_master_p1_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; end else begin - litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; + litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -3755,11 +4195,11 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; + litedramcore_master_p1_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; end else begin - litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; + litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -3770,11 +4210,11 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; + litedramcore_master_p2_address <= 14'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + litedramcore_master_p2_address <= litedramcore_slave_p2_address; end else begin - litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; + litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -3785,16 +4225,76 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; + litedramcore_master_p2_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; end else begin - litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; + litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_93 = dummy_s; // synthesis translate_on end + +// synthesis translate_off +reg dummy_d_94; +// synthesis translate_on +always @(*) begin + litedramcore_master_p2_cas_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + end else begin + litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; + end +// synthesis translate_off + dummy_d_94 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_95; +// synthesis translate_on +always @(*) begin + litedramcore_master_p2_cs_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + end else begin + litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; + end +// synthesis translate_off + dummy_d_95 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_96; +// synthesis translate_on +always @(*) begin + litedramcore_master_p2_ras_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + end else begin + litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; + end +// synthesis translate_off + dummy_d_96 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_97; +// synthesis translate_on +always @(*) begin + litedramcore_master_p2_we_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + end else begin + litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; + end +// synthesis translate_off + dummy_d_97 = dummy_s; +// synthesis translate_on +end assign litedramcore_inti_p0_cke = litedramcore_storage[1]; assign litedramcore_inti_p1_cke = litedramcore_storage[1]; assign litedramcore_inti_p2_cke = litedramcore_storage[1]; @@ -3809,7 +4309,7 @@ assign litedramcore_inti_p2_reset_n = litedramcore_storage[3]; assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; // synthesis translate_off -reg dummy_d_94; +reg dummy_d_98; // synthesis translate_on always @(*) begin litedramcore_inti_p0_cas_n <= 1'd1; @@ -3819,12 +4319,12 @@ always @(*) begin litedramcore_inti_p0_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_94 = dummy_s; + dummy_d_98 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_95; +reg dummy_d_99; // synthesis translate_on always @(*) begin litedramcore_inti_p0_cs_n <= 1'd1; @@ -3834,12 +4334,12 @@ always @(*) begin litedramcore_inti_p0_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_95 = dummy_s; + dummy_d_99 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_96; +reg dummy_d_100; // synthesis translate_on always @(*) begin litedramcore_inti_p0_ras_n <= 1'd1; @@ -3849,12 +4349,12 @@ always @(*) begin litedramcore_inti_p0_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_96 = dummy_s; + dummy_d_100 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_97; +reg dummy_d_101; // synthesis translate_on always @(*) begin litedramcore_inti_p0_we_n <= 1'd1; @@ -3864,7 +4364,7 @@ always @(*) begin litedramcore_inti_p0_we_n <= 1'd1; end // synthesis translate_off - dummy_d_97 = dummy_s; + dummy_d_101 = dummy_s; // synthesis translate_on end assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; @@ -3875,7 +4375,7 @@ assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; assign litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_98; +reg dummy_d_102; // synthesis translate_on always @(*) begin litedramcore_inti_p1_cas_n <= 1'd1; @@ -3885,12 +4385,12 @@ always @(*) begin litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_98 = dummy_s; + dummy_d_102 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_99; +reg dummy_d_103; // synthesis translate_on always @(*) begin litedramcore_inti_p1_cs_n <= 1'd1; @@ -3900,12 +4400,12 @@ always @(*) begin litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_99 = dummy_s; + dummy_d_103 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_100; +reg dummy_d_104; // synthesis translate_on always @(*) begin litedramcore_inti_p1_ras_n <= 1'd1; @@ -3915,12 +4415,12 @@ always @(*) begin litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_100 = dummy_s; + dummy_d_104 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_101; +reg dummy_d_105; // synthesis translate_on always @(*) begin litedramcore_inti_p1_we_n <= 1'd1; @@ -3930,7 +4430,7 @@ always @(*) begin litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off - dummy_d_101 = dummy_s; + dummy_d_105 = dummy_s; // synthesis translate_on end assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; @@ -3941,7 +4441,7 @@ assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; assign litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_102; +reg dummy_d_106; // synthesis translate_on always @(*) begin litedramcore_inti_p2_cas_n <= 1'd1; @@ -3951,12 +4451,12 @@ always @(*) begin litedramcore_inti_p2_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_102 = dummy_s; + dummy_d_106 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_103; +reg dummy_d_107; // synthesis translate_on always @(*) begin litedramcore_inti_p2_cs_n <= 1'd1; @@ -3966,12 +4466,12 @@ always @(*) begin litedramcore_inti_p2_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_103 = dummy_s; + dummy_d_107 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_104; +reg dummy_d_108; // synthesis translate_on always @(*) begin litedramcore_inti_p2_ras_n <= 1'd1; @@ -3981,12 +4481,12 @@ always @(*) begin litedramcore_inti_p2_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_104 = dummy_s; + dummy_d_108 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_105; +reg dummy_d_109; // synthesis translate_on always @(*) begin litedramcore_inti_p2_we_n <= 1'd1; @@ -3996,7 +4496,7 @@ always @(*) begin litedramcore_inti_p2_we_n <= 1'd1; end // synthesis translate_off - dummy_d_105 = dummy_s; + dummy_d_109 = dummy_s; // synthesis translate_on end assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage; @@ -4007,7 +4507,7 @@ assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; assign litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_106; +reg dummy_d_110; // synthesis translate_on always @(*) begin litedramcore_inti_p3_cas_n <= 1'd1; @@ -4017,12 +4517,12 @@ always @(*) begin litedramcore_inti_p3_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_106 = dummy_s; + dummy_d_110 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_107; +reg dummy_d_111; // synthesis translate_on always @(*) begin litedramcore_inti_p3_cs_n <= 1'd1; @@ -4032,12 +4532,12 @@ always @(*) begin litedramcore_inti_p3_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_107 = dummy_s; + dummy_d_111 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_108; +reg dummy_d_112; // synthesis translate_on always @(*) begin litedramcore_inti_p3_ras_n <= 1'd1; @@ -4047,12 +4547,12 @@ always @(*) begin litedramcore_inti_p3_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_108 = dummy_s; + dummy_d_112 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_109; +reg dummy_d_113; // synthesis translate_on always @(*) begin litedramcore_inti_p3_we_n <= 1'd1; @@ -4062,7 +4562,7 @@ always @(*) begin litedramcore_inti_p3_we_n <= 1'd1; end // synthesis translate_off - dummy_d_109 = dummy_s; + dummy_d_113 = dummy_s; // synthesis translate_on end assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage; @@ -4142,7 +4642,7 @@ assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; // synthesis translate_off -reg dummy_d_110; +reg dummy_d_114; // synthesis translate_on always @(*) begin refresher_next_state <= 2'd0; @@ -4176,12 +4676,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_110 = dummy_s; + dummy_d_114 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_111; +reg dummy_d_115; // synthesis translate_on always @(*) begin litedramcore_cmd_valid <= 1'd0; @@ -4208,12 +4708,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_111 = dummy_s; + dummy_d_115 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_112; +reg dummy_d_116; // synthesis translate_on always @(*) begin litedramcore_zqcs_executer_start <= 1'd0; @@ -4234,12 +4734,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_112 = dummy_s; + dummy_d_116 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_113; +reg dummy_d_117; // synthesis translate_on always @(*) begin litedramcore_cmd_last <= 1'd0; @@ -4263,12 +4763,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_113 = dummy_s; + dummy_d_117 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_114; +reg dummy_d_118; // synthesis translate_on always @(*) begin litedramcore_sequencer_start0 <= 1'd0; @@ -4286,7 +4786,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_114 = dummy_s; + dummy_d_118 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; @@ -4305,7 +4805,7 @@ assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == lit assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off -reg dummy_d_115; +reg dummy_d_119; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_a <= 14'd0; @@ -4315,7 +4815,7 @@ always @(*) begin litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_115 = dummy_s; + dummy_d_119 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); @@ -4323,7 +4823,7 @@ assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_ assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); // synthesis translate_off -reg dummy_d_116; +reg dummy_d_120; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_auto_precharge <= 1'd0; @@ -4333,7 +4833,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_116 = dummy_s; + dummy_d_120 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -4355,7 +4855,7 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_117; +reg dummy_d_121; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -4365,7 +4865,7 @@ always @(*) begin litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_117 = dummy_s; + dummy_d_121 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; @@ -4378,7 +4878,7 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (lite assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_118; +reg dummy_d_122; // synthesis translate_on always @(*) begin bankmachine0_next_state <= 4'd0; @@ -4441,12 +4941,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_118 = dummy_s; + dummy_d_122 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_119; +reg dummy_d_123; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_req_rdata_valid <= 1'd0; @@ -4486,12 +4986,45 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_119 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_120; +reg dummy_d_124; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_124 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_125; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_refresh_gnt <= 1'd0; @@ -4519,12 +5052,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_120 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_121; +reg dummy_d_126; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_valid <= 1'd0; @@ -4567,12 +5100,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_121 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_122; +reg dummy_d_127; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_open <= 1'd0; @@ -4600,12 +5133,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_122 = dummy_s; + dummy_d_127 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_123; +reg dummy_d_128; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_close <= 1'd0; @@ -4633,12 +5166,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_123 = dummy_s; + dummy_d_128 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_124; +reg dummy_d_129; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; @@ -4675,12 +5208,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_124 = dummy_s; + dummy_d_129 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_125; +reg dummy_d_130; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; @@ -4711,12 +5244,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_130 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_131; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_we <= 1'd0; @@ -4759,45 +5292,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_127 = dummy_s; + dummy_d_131 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_128; +reg dummy_d_132; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; @@ -4829,12 +5329,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_128 = dummy_s; + dummy_d_132 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_129; +reg dummy_d_133; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; @@ -4874,12 +5374,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_129 = dummy_s; + dummy_d_133 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_130; +reg dummy_d_134; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; @@ -4919,12 +5419,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_130 = dummy_s; + dummy_d_134 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_131; +reg dummy_d_135; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_req_wdata_ready <= 1'd0; @@ -4964,7 +5464,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_131 = dummy_s; + dummy_d_135 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; @@ -4983,7 +5483,7 @@ assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == lit assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off -reg dummy_d_132; +reg dummy_d_136; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_a <= 14'd0; @@ -4993,7 +5493,7 @@ always @(*) begin litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_132 = dummy_s; + dummy_d_136 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); @@ -5001,7 +5501,7 @@ assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_ assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); // synthesis translate_off -reg dummy_d_133; +reg dummy_d_137; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_auto_precharge <= 1'd0; @@ -5011,7 +5511,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_133 = dummy_s; + dummy_d_137 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -5033,7 +5533,7 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_134; +reg dummy_d_138; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -5043,7 +5543,7 @@ always @(*) begin litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_134 = dummy_s; + dummy_d_138 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; @@ -5056,7 +5556,7 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (lite assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_135; +reg dummy_d_139; // synthesis translate_on always @(*) begin bankmachine1_next_state <= 4'd0; @@ -5119,12 +5619,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_135 = dummy_s; + dummy_d_139 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_136; +reg dummy_d_140; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_req_rdata_valid <= 1'd0; @@ -5164,26 +5664,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_136 = dummy_s; + dummy_d_140 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_137; +reg dummy_d_141; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5197,26 +5697,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_137 = dummy_s; + dummy_d_141 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_138; +reg dummy_d_142; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; + litedramcore_bankmachine1_cmd_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5227,29 +5730,38 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_138 = dummy_s; + dummy_d_142 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_139; +reg dummy_d_143; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5263,27 +5775,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_139 = dummy_s; + dummy_d_143 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_140; +reg dummy_d_144; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_open <= 1'd0; @@ -5311,12 +5811,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_140 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_141; +reg dummy_d_145; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_close <= 1'd0; @@ -5344,12 +5844,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_141 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_142; +reg dummy_d_146; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; @@ -5386,12 +5886,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_142 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_143; +reg dummy_d_147; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; @@ -5422,12 +5922,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_144; +reg dummy_d_148; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_we <= 1'd0; @@ -5470,12 +5970,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_144 = dummy_s; + dummy_d_148 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_145; +reg dummy_d_149; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; @@ -5507,12 +6007,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_145 = dummy_s; + dummy_d_149 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_146; +reg dummy_d_150; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; @@ -5552,12 +6052,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_146 = dummy_s; + dummy_d_150 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_147; +reg dummy_d_151; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; @@ -5597,12 +6097,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_147 = dummy_s; + dummy_d_151 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_148; +reg dummy_d_152; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_req_wdata_ready <= 1'd0; @@ -5642,7 +6142,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_148 = dummy_s; + dummy_d_152 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; @@ -5661,7 +6161,7 @@ assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == lit assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; // synthesis translate_off -reg dummy_d_149; +reg dummy_d_153; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_a <= 14'd0; @@ -5671,7 +6171,7 @@ always @(*) begin litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_149 = dummy_s; + dummy_d_153 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); @@ -5679,7 +6179,7 @@ assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_ assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); // synthesis translate_off -reg dummy_d_150; +reg dummy_d_154; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_auto_precharge <= 1'd0; @@ -5689,7 +6189,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_150 = dummy_s; + dummy_d_154 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -5711,7 +6211,7 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_151; +reg dummy_d_155; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -5721,7 +6221,7 @@ always @(*) begin litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_151 = dummy_s; + dummy_d_155 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; @@ -5734,7 +6234,7 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (lite assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_152; +reg dummy_d_156; // synthesis translate_on always @(*) begin bankmachine2_next_state <= 4'd0; @@ -5797,12 +6297,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_152 = dummy_s; + dummy_d_156 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_153; +reg dummy_d_157; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_req_rdata_valid <= 1'd0; @@ -5842,12 +6342,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_153 = dummy_s; + dummy_d_157 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_154; +reg dummy_d_158; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_refresh_gnt <= 1'd0; @@ -5875,12 +6375,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_154 = dummy_s; + dummy_d_158 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_155; +reg dummy_d_159; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_valid <= 1'd0; @@ -5923,15 +6423,15 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_155 = dummy_s; + dummy_d_159 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_156; +reg dummy_d_160; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine2_row_open <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -5939,7 +6439,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -5956,26 +6456,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_156 = dummy_s; + dummy_d_160 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_157; +reg dummy_d_161; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; + litedramcore_bankmachine2_row_close <= 1'd0; case (bankmachine2_state) 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end end 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -5989,26 +6489,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_157 = dummy_s; + dummy_d_161 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_158; +reg dummy_d_162; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6019,24 +6516,39 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_158 = dummy_s; + dummy_d_162 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_159; +reg dummy_d_163; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6049,27 +6561,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_159 = dummy_s; + dummy_d_163 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_160; +reg dummy_d_164; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; @@ -6100,12 +6600,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_160 = dummy_s; + dummy_d_164 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_161; +reg dummy_d_165; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_we <= 1'd0; @@ -6148,12 +6648,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_161 = dummy_s; + dummy_d_165 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_162; +reg dummy_d_166; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; @@ -6185,12 +6685,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_162 = dummy_s; + dummy_d_166 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_163; +reg dummy_d_167; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; @@ -6230,12 +6730,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_163 = dummy_s; + dummy_d_167 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_164; +reg dummy_d_168; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; @@ -6275,12 +6775,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_164 = dummy_s; + dummy_d_168 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_165; +reg dummy_d_169; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_req_wdata_ready <= 1'd0; @@ -6320,7 +6820,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_165 = dummy_s; + dummy_d_169 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; @@ -6339,7 +6839,7 @@ assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == lit assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; // synthesis translate_off -reg dummy_d_166; +reg dummy_d_170; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_a <= 14'd0; @@ -6349,7 +6849,7 @@ always @(*) begin litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_166 = dummy_s; + dummy_d_170 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); @@ -6357,7 +6857,7 @@ assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_ assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); // synthesis translate_off -reg dummy_d_167; +reg dummy_d_171; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_auto_precharge <= 1'd0; @@ -6367,7 +6867,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_167 = dummy_s; + dummy_d_171 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -6389,7 +6889,7 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_168; +reg dummy_d_172; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -6399,7 +6899,7 @@ always @(*) begin litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_168 = dummy_s; + dummy_d_172 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; @@ -6412,7 +6912,7 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (lite assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_169; +reg dummy_d_173; // synthesis translate_on always @(*) begin bankmachine3_next_state <= 4'd0; @@ -6475,12 +6975,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_169 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_170; +reg dummy_d_174; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_req_rdata_valid <= 1'd0; @@ -6520,12 +7020,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_170 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_171; +reg dummy_d_175; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_refresh_gnt <= 1'd0; @@ -6553,12 +7053,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_171 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_172; +reg dummy_d_176; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_valid <= 1'd0; @@ -6601,12 +7101,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_173; +reg dummy_d_177; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_open <= 1'd0; @@ -6634,12 +7134,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_177 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_178; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_close <= 1'd0; @@ -6667,12 +7167,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_178 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_179; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; @@ -6709,45 +7209,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_175 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_176; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_176 = dummy_s; + dummy_d_179 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_177; +reg dummy_d_180; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; @@ -6778,12 +7245,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_177 = dummy_s; + dummy_d_180 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_178; +reg dummy_d_181; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_we <= 1'd0; @@ -6826,12 +7293,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_178 = dummy_s; + dummy_d_181 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_179; +reg dummy_d_182; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; @@ -6863,12 +7330,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_179 = dummy_s; + dummy_d_182 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_180; +reg dummy_d_183; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; @@ -6908,12 +7375,45 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_180 = dummy_s; + dummy_d_183 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_181; +reg dummy_d_184; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_184 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_185; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; @@ -6953,12 +7453,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_181 = dummy_s; + dummy_d_185 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_182; +reg dummy_d_186; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_req_wdata_ready <= 1'd0; @@ -6998,7 +7498,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_182 = dummy_s; + dummy_d_186 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; @@ -7017,7 +7517,7 @@ assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == lit assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; // synthesis translate_off -reg dummy_d_183; +reg dummy_d_187; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_a <= 14'd0; @@ -7027,7 +7527,7 @@ always @(*) begin litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_183 = dummy_s; + dummy_d_187 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); @@ -7035,7 +7535,7 @@ assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_ assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); // synthesis translate_off -reg dummy_d_184; +reg dummy_d_188; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_auto_precharge <= 1'd0; @@ -7045,7 +7545,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_184 = dummy_s; + dummy_d_188 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -7067,7 +7567,7 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_185; +reg dummy_d_189; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -7077,7 +7577,7 @@ always @(*) begin litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_185 = dummy_s; + dummy_d_189 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; @@ -7090,7 +7590,7 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (lite assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_186; +reg dummy_d_190; // synthesis translate_on always @(*) begin bankmachine4_next_state <= 4'd0; @@ -7153,12 +7653,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_186 = dummy_s; + dummy_d_190 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_187; +reg dummy_d_191; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_req_rdata_valid <= 1'd0; @@ -7198,26 +7698,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_187 = dummy_s; + dummy_d_191 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_188; +reg dummy_d_192; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7231,12 +7731,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_188 = dummy_s; + dummy_d_192 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_189; +reg dummy_d_193; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_valid <= 1'd0; @@ -7279,12 +7779,45 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_189 = dummy_s; + dummy_d_193 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_190; +reg dummy_d_194; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_194 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_195; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_row_open <= 1'd0; @@ -7312,12 +7845,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_190 = dummy_s; + dummy_d_195 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_191; +reg dummy_d_196; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_row_close <= 1'd0; @@ -7345,12 +7878,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_191 = dummy_s; + dummy_d_196 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_192; +reg dummy_d_197; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; @@ -7387,12 +7920,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_192 = dummy_s; + dummy_d_197 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_193; +reg dummy_d_198; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; @@ -7423,12 +7956,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_193 = dummy_s; + dummy_d_198 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_194; +reg dummy_d_199; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_we <= 1'd0; @@ -7471,12 +8004,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_194 = dummy_s; + dummy_d_199 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_195; +reg dummy_d_200; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; @@ -7508,12 +8041,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_195 = dummy_s; + dummy_d_200 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_196; +reg dummy_d_201; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; @@ -7553,45 +8086,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_196 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_197; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_197 = dummy_s; + dummy_d_201 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_198; +reg dummy_d_202; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; @@ -7631,12 +8131,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_198 = dummy_s; + dummy_d_202 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_199; +reg dummy_d_203; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_req_wdata_ready <= 1'd0; @@ -7676,7 +8176,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_199 = dummy_s; + dummy_d_203 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; @@ -7695,7 +8195,7 @@ assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == lit assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; // synthesis translate_off -reg dummy_d_200; +reg dummy_d_204; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_a <= 14'd0; @@ -7705,7 +8205,7 @@ always @(*) begin litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_200 = dummy_s; + dummy_d_204 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); @@ -7713,7 +8213,7 @@ assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_ assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); // synthesis translate_off -reg dummy_d_201; +reg dummy_d_205; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_auto_precharge <= 1'd0; @@ -7723,7 +8223,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_201 = dummy_s; + dummy_d_205 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -7745,7 +8245,7 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_202; +reg dummy_d_206; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -7755,7 +8255,7 @@ always @(*) begin litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_202 = dummy_s; + dummy_d_206 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; @@ -7768,7 +8268,7 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (lite assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_203; +reg dummy_d_207; // synthesis translate_on always @(*) begin bankmachine5_next_state <= 4'd0; @@ -7831,12 +8331,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_203 = dummy_s; + dummy_d_207 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_204; +reg dummy_d_208; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_req_rdata_valid <= 1'd0; @@ -7876,26 +8376,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_204 = dummy_s; + dummy_d_208 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_205; +reg dummy_d_209; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7909,26 +8409,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_205 = dummy_s; + dummy_d_209 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_206; +reg dummy_d_210; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; + litedramcore_bankmachine5_cmd_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7939,29 +8442,38 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_206 = dummy_s; + dummy_d_210 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_207; +reg dummy_d_211; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7975,27 +8487,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_207 = dummy_s; + dummy_d_211 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_208; +reg dummy_d_212; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_row_open <= 1'd0; @@ -8023,12 +8523,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_208 = dummy_s; + dummy_d_212 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_209; +reg dummy_d_213; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_row_close <= 1'd0; @@ -8056,12 +8556,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_209 = dummy_s; + dummy_d_213 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_210; +reg dummy_d_214; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; @@ -8098,12 +8598,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_210 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_211; +reg dummy_d_215; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; @@ -8134,12 +8634,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_211 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_212; +reg dummy_d_216; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_we <= 1'd0; @@ -8182,12 +8682,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_212 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_213; +reg dummy_d_217; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; @@ -8219,12 +8719,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_214; +reg dummy_d_218; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; @@ -8264,12 +8764,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_218 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_215; +reg dummy_d_219; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; @@ -8309,12 +8809,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_219 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_216; +reg dummy_d_220; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_req_wdata_ready <= 1'd0; @@ -8354,7 +8854,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_220 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; @@ -8373,7 +8873,7 @@ assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == lit assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; // synthesis translate_off -reg dummy_d_217; +reg dummy_d_221; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_a <= 14'd0; @@ -8383,7 +8883,7 @@ always @(*) begin litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_217 = dummy_s; + dummy_d_221 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); @@ -8391,7 +8891,7 @@ assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_ assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); // synthesis translate_off -reg dummy_d_218; +reg dummy_d_222; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_auto_precharge <= 1'd0; @@ -8401,7 +8901,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_218 = dummy_s; + dummy_d_222 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -8423,7 +8923,7 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_219; +reg dummy_d_223; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -8433,7 +8933,7 @@ always @(*) begin litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_219 = dummy_s; + dummy_d_223 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; @@ -8446,7 +8946,7 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (lite assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_220; +reg dummy_d_224; // synthesis translate_on always @(*) begin bankmachine6_next_state <= 4'd0; @@ -8509,12 +9009,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_220 = dummy_s; + dummy_d_224 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_221; +reg dummy_d_225; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_req_rdata_valid <= 1'd0; @@ -8554,12 +9054,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_221 = dummy_s; + dummy_d_225 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_222; +reg dummy_d_226; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_refresh_gnt <= 1'd0; @@ -8587,12 +9087,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_222 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_223; +reg dummy_d_227; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_valid <= 1'd0; @@ -8635,45 +9135,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_223 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_224; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_224 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_225; +reg dummy_d_228; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_open <= 1'd0; @@ -8701,12 +9168,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_225 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_226; +reg dummy_d_229; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_close <= 1'd0; @@ -8734,12 +9201,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_226 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_227; +reg dummy_d_230; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; @@ -8776,12 +9243,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_230 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_231; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; @@ -8812,12 +9279,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_231 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_232; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_we <= 1'd0; @@ -8860,12 +9327,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_232 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_230; +reg dummy_d_233; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; @@ -8897,12 +9364,45 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_233 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_231; +reg dummy_d_234; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_234 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_235; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; @@ -8942,12 +9442,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_231 = dummy_s; + dummy_d_235 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_232; +reg dummy_d_236; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; @@ -8987,12 +9487,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_232 = dummy_s; + dummy_d_236 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_233; +reg dummy_d_237; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_req_wdata_ready <= 1'd0; @@ -9032,7 +9532,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_233 = dummy_s; + dummy_d_237 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; @@ -9051,7 +9551,7 @@ assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == lit assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; // synthesis translate_off -reg dummy_d_234; +reg dummy_d_238; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_a <= 14'd0; @@ -9061,7 +9561,7 @@ always @(*) begin litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_234 = dummy_s; + dummy_d_238 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); @@ -9069,7 +9569,7 @@ assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_ assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); // synthesis translate_off -reg dummy_d_235; +reg dummy_d_239; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_auto_precharge <= 1'd0; @@ -9079,7 +9579,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_235 = dummy_s; + dummy_d_239 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -9101,7 +9601,7 @@ assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_236; +reg dummy_d_240; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -9111,7 +9611,7 @@ always @(*) begin litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_236 = dummy_s; + dummy_d_240 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; @@ -9124,7 +9624,7 @@ assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (lite assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_237; +reg dummy_d_241; // synthesis translate_on always @(*) begin bankmachine7_next_state <= 4'd0; @@ -9187,12 +9687,45 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_237 = dummy_s; + dummy_d_241 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_238; +reg dummy_d_242; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_242 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_243; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_req_rdata_valid <= 1'd0; @@ -9232,12 +9765,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_238 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_239; +reg dummy_d_244; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_refresh_gnt <= 1'd0; @@ -9265,12 +9798,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_239 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_240; +reg dummy_d_245; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_valid <= 1'd0; @@ -9313,12 +9846,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_240 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_241; +reg dummy_d_246; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_open <= 1'd0; @@ -9346,12 +9879,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_246 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_247; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_close <= 1'd0; @@ -9379,12 +9912,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_247 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_248; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; @@ -9421,12 +9954,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_248 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_249; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; @@ -9457,12 +9990,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_249 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_250; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_we <= 1'd0; @@ -9490,78 +10023,45 @@ always @(*) begin if (litedramcore_bankmachine7_refresh_req) begin end else begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_245 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_246; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_246 = dummy_s; + dummy_d_250 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_247; +reg dummy_d_251; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9575,12 +10075,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_247 = dummy_s; + dummy_d_251 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_248; +reg dummy_d_252; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; @@ -9620,12 +10120,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_248 = dummy_s; + dummy_d_252 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_249; +reg dummy_d_253; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; @@ -9665,12 +10165,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_249 = dummy_s; + dummy_d_253 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_250; +reg dummy_d_254; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_req_wdata_ready <= 1'd0; @@ -9710,7 +10210,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_250 = dummy_s; + dummy_d_254 = dummy_s; // synthesis translate_on end assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); @@ -9743,7 +10243,7 @@ assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedr assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); // synthesis translate_off -reg dummy_d_251; +reg dummy_d_255; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_valids <= 8'd0; @@ -9756,7 +10256,7 @@ always @(*) begin litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); // synthesis translate_off - dummy_d_251 = dummy_s; + dummy_d_255 = dummy_s; // synthesis translate_on end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; @@ -9768,7 +10268,7 @@ assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; // synthesis translate_off -reg dummy_d_252; +reg dummy_d_256; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; @@ -9776,12 +10276,12 @@ always @(*) begin litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; end // synthesis translate_off - dummy_d_252 = dummy_s; + dummy_d_256 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_253; +reg dummy_d_257; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; @@ -9789,12 +10289,12 @@ always @(*) begin litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; end // synthesis translate_off - dummy_d_253 = dummy_s; + dummy_d_257 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_254; +reg dummy_d_258; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_cmd_payload_we <= 1'd0; @@ -9802,12 +10302,12 @@ always @(*) begin litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; end // synthesis translate_off - dummy_d_254 = dummy_s; + dummy_d_258 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_255; +reg dummy_d_259; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_ready <= 1'd0; @@ -9818,12 +10318,12 @@ always @(*) begin litedramcore_bankmachine0_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_255 = dummy_s; + dummy_d_259 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_256; +reg dummy_d_260; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_ready <= 1'd0; @@ -9834,12 +10334,12 @@ always @(*) begin litedramcore_bankmachine1_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_256 = dummy_s; + dummy_d_260 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_257; +reg dummy_d_261; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_ready <= 1'd0; @@ -9850,12 +10350,12 @@ always @(*) begin litedramcore_bankmachine2_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_257 = dummy_s; + dummy_d_261 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_258; +reg dummy_d_262; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_ready <= 1'd0; @@ -9866,12 +10366,12 @@ always @(*) begin litedramcore_bankmachine3_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_258 = dummy_s; + dummy_d_262 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_259; +reg dummy_d_263; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_ready <= 1'd0; @@ -9882,12 +10382,12 @@ always @(*) begin litedramcore_bankmachine4_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_259 = dummy_s; + dummy_d_263 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_260; +reg dummy_d_264; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_ready <= 1'd0; @@ -9898,12 +10398,12 @@ always @(*) begin litedramcore_bankmachine5_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_260 = dummy_s; + dummy_d_264 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_261; +reg dummy_d_265; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_ready <= 1'd0; @@ -9914,12 +10414,12 @@ always @(*) begin litedramcore_bankmachine6_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_261 = dummy_s; + dummy_d_265 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_262; +reg dummy_d_266; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_ready <= 1'd0; @@ -9930,13 +10430,13 @@ always @(*) begin litedramcore_bankmachine7_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_262 = dummy_s; + dummy_d_266 = dummy_s; // synthesis translate_on end assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); // synthesis translate_off -reg dummy_d_263; +reg dummy_d_267; // synthesis translate_on always @(*) begin litedramcore_choose_req_valids <= 8'd0; @@ -9949,7 +10449,7 @@ always @(*) begin litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); // synthesis translate_off - dummy_d_263 = dummy_s; + dummy_d_267 = dummy_s; // synthesis translate_on end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; @@ -9961,7 +10461,7 @@ assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; // synthesis translate_off -reg dummy_d_264; +reg dummy_d_268; // synthesis translate_on always @(*) begin litedramcore_choose_req_cmd_payload_cas <= 1'd0; @@ -9969,12 +10469,12 @@ always @(*) begin litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; end // synthesis translate_off - dummy_d_264 = dummy_s; + dummy_d_268 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_265; +reg dummy_d_269; // synthesis translate_on always @(*) begin litedramcore_choose_req_cmd_payload_ras <= 1'd0; @@ -9982,12 +10482,12 @@ always @(*) begin litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; end // synthesis translate_off - dummy_d_265 = dummy_s; + dummy_d_269 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_266; +reg dummy_d_270; // synthesis translate_on always @(*) begin litedramcore_choose_req_cmd_payload_we <= 1'd0; @@ -9995,7 +10495,7 @@ always @(*) begin litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; end // synthesis translate_off - dummy_d_266 = dummy_s; + dummy_d_270 = dummy_s; // synthesis translate_on end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); @@ -10014,7 +10514,7 @@ assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); // synthesis translate_off -reg dummy_d_267; +reg dummy_d_271; // synthesis translate_on always @(*) begin multiplexer_next_state <= 4'd0; @@ -10073,17 +10573,18 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_267 = dummy_s; + dummy_d_271 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_268; +reg dummy_d_272; // synthesis translate_on always @(*) begin - litedramcore_en0 <= 1'd0; + litedramcore_steerer_sel3 <= 2'd0; case (multiplexer_state) 1'd1: begin + litedramcore_steerer_sel3 <= 2'd2; end 2'd2: begin end @@ -10104,24 +10605,23 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off - dummy_d_268 = dummy_s; + dummy_d_272 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_269; +reg dummy_d_273; // synthesis translate_on always @(*) begin - litedramcore_cmd_ready <= 1'd0; + litedramcore_en0 <= 1'd0; case (multiplexer_state) 1'd1: begin end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10140,26 +10640,24 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off - dummy_d_269 = dummy_s; + dummy_d_273 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_270; +reg dummy_d_274; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; + litedramcore_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end end 2'd2: begin + litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10178,24 +10676,24 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end end endcase // synthesis translate_off - dummy_d_270 = dummy_s; + dummy_d_274 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_271; +reg dummy_d_275; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; + litedramcore_choose_cmd_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end 2'd2: begin end @@ -10216,22 +10714,24 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end endcase // synthesis translate_off - dummy_d_271 = dummy_s; + dummy_d_275 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_272; +reg dummy_d_276; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; + litedramcore_choose_req_want_reads <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10252,25 +10752,22 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off - dummy_d_272 = dummy_s; + dummy_d_276 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_273; +reg dummy_d_277; // synthesis translate_on always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; + litedramcore_choose_req_want_writes <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10291,26 +10788,25 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end end endcase // synthesis translate_off - dummy_d_273 = dummy_s; + dummy_d_277 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_274; +reg dummy_d_278; // synthesis translate_on always @(*) begin - litedramcore_en1 <= 1'd0; + litedramcore_choose_req_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end 2'd2: begin end @@ -10331,21 +10827,26 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end endcase // synthesis translate_off - dummy_d_274 = dummy_s; + dummy_d_278 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_275; +reg dummy_d_279; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; + litedramcore_en1 <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 2'd2; + litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10366,16 +10867,15 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off - dummy_d_275 = dummy_s; + dummy_d_279 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_276; +reg dummy_d_280; // synthesis translate_on always @(*) begin litedramcore_steerer_sel0 <= 2'd0; @@ -10407,12 +10907,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_276 = dummy_s; + dummy_d_280 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_277; +reg dummy_d_281; // synthesis translate_on always @(*) begin litedramcore_steerer_sel1 <= 2'd0; @@ -10443,12 +10943,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_277 = dummy_s; + dummy_d_281 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_278; +reg dummy_d_282; // synthesis translate_on always @(*) begin litedramcore_steerer_sel2 <= 2'd0; @@ -10479,12 +10979,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_278 = dummy_s; + dummy_d_282 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_279; +reg dummy_d_283; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_want_activates <= 1'd0; @@ -10521,7 +11021,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_279 = dummy_s; + dummy_d_283 = dummy_s; // synthesis translate_on end assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; @@ -10569,7 +11069,7 @@ assign user_port_wdata_ready = new_master_wdata_ready2; assign user_port_rdata_valid = new_master_rdata_valid8; // synthesis translate_off -reg dummy_d_280; +reg dummy_d_284; // synthesis translate_on always @(*) begin litedramcore_interface_wdata_we <= 16'd0; @@ -10582,12 +11082,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_280 = dummy_s; + dummy_d_284 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_281; +reg dummy_d_285; // synthesis translate_on always @(*) begin litedramcore_interface_wdata <= 128'd0; @@ -10600,7 +11100,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_281 = dummy_s; + dummy_d_285 = dummy_s; // synthesis translate_on end assign user_port_rdata_payload_data = litedramcore_interface_rdata; @@ -10612,9 +11112,20 @@ assign roundrobin4_grant = 1'd0; assign roundrobin5_grant = 1'd0; assign roundrobin6_grant = 1'd0; assign roundrobin7_grant = 1'd0; +assign litedramcore_wishbone_adr = wb_bus_adr; +assign litedramcore_wishbone_dat_w = wb_bus_dat_w; +assign wb_bus_dat_r = litedramcore_wishbone_dat_r; +assign litedramcore_wishbone_sel = wb_bus_sel; +assign litedramcore_wishbone_cyc = wb_bus_cyc; +assign litedramcore_wishbone_stb = wb_bus_stb; +assign wb_bus_ack = litedramcore_wishbone_ack; +assign litedramcore_wishbone_we = wb_bus_we; +assign litedramcore_wishbone_cti = wb_bus_cti; +assign litedramcore_wishbone_bte = wb_bus_bte; +assign wb_bus_err = litedramcore_wishbone_err; // synthesis translate_off -reg dummy_d_282; +reg dummy_d_286; // synthesis translate_on always @(*) begin csrbank0_sel <= 1'd0; @@ -10623,7 +11134,7 @@ always @(*) begin csrbank0_sel <= 1'd0; end // synthesis translate_off - dummy_d_282 = dummy_s; + dummy_d_286 = dummy_s; // synthesis translate_on end assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; @@ -10636,7 +11147,7 @@ assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; // synthesis translate_off -reg dummy_d_283; +reg dummy_d_287; // synthesis translate_on always @(*) begin csrbank1_sel <= 1'd0; @@ -10645,7 +11156,7 @@ always @(*) begin csrbank1_sel <= 1'd0; end // synthesis translate_off - dummy_d_283 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; @@ -10683,7 +11194,7 @@ assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; // synthesis translate_off -reg dummy_d_284; +reg dummy_d_288; // synthesis translate_on always @(*) begin csrbank2_sel <= 1'd0; @@ -10692,7 +11203,7 @@ always @(*) begin csrbank2_sel <= 1'd0; end // synthesis translate_off - dummy_d_284 = dummy_s; + dummy_d_288 = dummy_s; // synthesis translate_on end assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; @@ -10795,10 +11306,10 @@ assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_stor assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we; -assign adr = csr_port_adr; -assign we = csr_port_we; -assign dat_w = csr_port_dat_w; -assign csr_port_dat_r = dat_r; +assign adr = litedramcore_adr; +assign we = litedramcore_we; +assign dat_w = litedramcore_dat_w; +assign litedramcore_dat_r = dat_r; assign interface0_bank_bus_adr = adr; assign interface1_bank_bus_adr = adr; assign interface2_bank_bus_adr = adr; @@ -10811,7 +11322,7 @@ assign interface2_bank_bus_dat_w = dat_w; assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); // synthesis translate_off -reg dummy_d_285; +reg dummy_d_289; // synthesis translate_on always @(*) begin rhs_array_muxed0 <= 1'd0; @@ -10842,12 +11353,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_285 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_286; +reg dummy_d_290; // synthesis translate_on always @(*) begin rhs_array_muxed1 <= 14'd0; @@ -10878,12 +11389,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_286 = dummy_s; + dummy_d_290 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_287; +reg dummy_d_291; // synthesis translate_on always @(*) begin rhs_array_muxed2 <= 3'd0; @@ -10914,12 +11425,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_287 = dummy_s; + dummy_d_291 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_288; +reg dummy_d_292; // synthesis translate_on always @(*) begin rhs_array_muxed3 <= 1'd0; @@ -10950,12 +11461,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_288 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_289; +reg dummy_d_293; // synthesis translate_on always @(*) begin rhs_array_muxed4 <= 1'd0; @@ -10986,12 +11497,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_289 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_290; +reg dummy_d_294; // synthesis translate_on always @(*) begin rhs_array_muxed5 <= 1'd0; @@ -11022,12 +11533,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_290 = dummy_s; + dummy_d_294 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_291; +reg dummy_d_295; // synthesis translate_on always @(*) begin t_array_muxed0 <= 1'd0; @@ -11058,12 +11569,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_291 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_292; +reg dummy_d_296; // synthesis translate_on always @(*) begin t_array_muxed1 <= 1'd0; @@ -11094,12 +11605,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_292 = dummy_s; + dummy_d_296 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_293; +reg dummy_d_297; // synthesis translate_on always @(*) begin t_array_muxed2 <= 1'd0; @@ -11130,12 +11641,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_293 = dummy_s; + dummy_d_297 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_294; +reg dummy_d_298; // synthesis translate_on always @(*) begin rhs_array_muxed6 <= 1'd0; @@ -11166,12 +11677,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_294 = dummy_s; + dummy_d_298 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_295; +reg dummy_d_299; // synthesis translate_on always @(*) begin rhs_array_muxed7 <= 14'd0; @@ -11202,12 +11713,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_295 = dummy_s; + dummy_d_299 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_296; +reg dummy_d_300; // synthesis translate_on always @(*) begin rhs_array_muxed8 <= 3'd0; @@ -11238,12 +11749,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_296 = dummy_s; + dummy_d_300 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_297; +reg dummy_d_301; // synthesis translate_on always @(*) begin rhs_array_muxed9 <= 1'd0; @@ -11274,12 +11785,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_297 = dummy_s; + dummy_d_301 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_298; +reg dummy_d_302; // synthesis translate_on always @(*) begin rhs_array_muxed10 <= 1'd0; @@ -11310,12 +11821,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_298 = dummy_s; + dummy_d_302 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_299; +reg dummy_d_303; // synthesis translate_on always @(*) begin rhs_array_muxed11 <= 1'd0; @@ -11346,12 +11857,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_299 = dummy_s; + dummy_d_303 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_300; +reg dummy_d_304; // synthesis translate_on always @(*) begin t_array_muxed3 <= 1'd0; @@ -11382,12 +11893,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_300 = dummy_s; + dummy_d_304 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_301; +reg dummy_d_305; // synthesis translate_on always @(*) begin t_array_muxed4 <= 1'd0; @@ -11418,12 +11929,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_301 = dummy_s; + dummy_d_305 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_302; +reg dummy_d_306; // synthesis translate_on always @(*) begin t_array_muxed5 <= 1'd0; @@ -11454,12 +11965,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_302 = dummy_s; + dummy_d_306 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_303; +reg dummy_d_307; // synthesis translate_on always @(*) begin rhs_array_muxed12 <= 21'd0; @@ -11469,12 +11980,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_303 = dummy_s; + dummy_d_307 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_304; +reg dummy_d_308; // synthesis translate_on always @(*) begin rhs_array_muxed13 <= 1'd0; @@ -11484,12 +11995,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_304 = dummy_s; + dummy_d_308 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_305; +reg dummy_d_309; // synthesis translate_on always @(*) begin rhs_array_muxed14 <= 1'd0; @@ -11499,12 +12010,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_305 = dummy_s; + dummy_d_309 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_306; +reg dummy_d_310; // synthesis translate_on always @(*) begin rhs_array_muxed15 <= 21'd0; @@ -11514,12 +12025,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_306 = dummy_s; + dummy_d_310 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_307; +reg dummy_d_311; // synthesis translate_on always @(*) begin rhs_array_muxed16 <= 1'd0; @@ -11529,12 +12040,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_307 = dummy_s; + dummy_d_311 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_308; +reg dummy_d_312; // synthesis translate_on always @(*) begin rhs_array_muxed17 <= 1'd0; @@ -11544,12 +12055,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_308 = dummy_s; + dummy_d_312 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_309; +reg dummy_d_313; // synthesis translate_on always @(*) begin rhs_array_muxed18 <= 21'd0; @@ -11559,12 +12070,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_309 = dummy_s; + dummy_d_313 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_310; +reg dummy_d_314; // synthesis translate_on always @(*) begin rhs_array_muxed19 <= 1'd0; @@ -11574,12 +12085,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_310 = dummy_s; + dummy_d_314 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_311; +reg dummy_d_315; // synthesis translate_on always @(*) begin rhs_array_muxed20 <= 1'd0; @@ -11589,12 +12100,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_311 = dummy_s; + dummy_d_315 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_312; +reg dummy_d_316; // synthesis translate_on always @(*) begin rhs_array_muxed21 <= 21'd0; @@ -11604,12 +12115,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_312 = dummy_s; + dummy_d_316 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_313; +reg dummy_d_317; // synthesis translate_on always @(*) begin rhs_array_muxed22 <= 1'd0; @@ -11619,12 +12130,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_313 = dummy_s; + dummy_d_317 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_314; +reg dummy_d_318; // synthesis translate_on always @(*) begin rhs_array_muxed23 <= 1'd0; @@ -11634,12 +12145,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_314 = dummy_s; + dummy_d_318 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_315; +reg dummy_d_319; // synthesis translate_on always @(*) begin rhs_array_muxed24 <= 21'd0; @@ -11649,12 +12160,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_315 = dummy_s; + dummy_d_319 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_316; +reg dummy_d_320; // synthesis translate_on always @(*) begin rhs_array_muxed25 <= 1'd0; @@ -11664,12 +12175,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_316 = dummy_s; + dummy_d_320 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_317; +reg dummy_d_321; // synthesis translate_on always @(*) begin rhs_array_muxed26 <= 1'd0; @@ -11679,12 +12190,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_317 = dummy_s; + dummy_d_321 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_318; +reg dummy_d_322; // synthesis translate_on always @(*) begin rhs_array_muxed27 <= 21'd0; @@ -11694,12 +12205,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_318 = dummy_s; + dummy_d_322 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_319; +reg dummy_d_323; // synthesis translate_on always @(*) begin rhs_array_muxed28 <= 1'd0; @@ -11709,12 +12220,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_319 = dummy_s; + dummy_d_323 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_320; +reg dummy_d_324; // synthesis translate_on always @(*) begin rhs_array_muxed29 <= 1'd0; @@ -11724,12 +12235,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_320 = dummy_s; + dummy_d_324 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_321; +reg dummy_d_325; // synthesis translate_on always @(*) begin rhs_array_muxed30 <= 21'd0; @@ -11739,12 +12250,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_321 = dummy_s; + dummy_d_325 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_322; +reg dummy_d_326; // synthesis translate_on always @(*) begin rhs_array_muxed31 <= 1'd0; @@ -11754,12 +12265,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_322 = dummy_s; + dummy_d_326 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_323; +reg dummy_d_327; // synthesis translate_on always @(*) begin rhs_array_muxed32 <= 1'd0; @@ -11769,12 +12280,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_323 = dummy_s; + dummy_d_327 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_324; +reg dummy_d_328; // synthesis translate_on always @(*) begin rhs_array_muxed33 <= 21'd0; @@ -11784,12 +12295,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_324 = dummy_s; + dummy_d_328 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_325; +reg dummy_d_329; // synthesis translate_on always @(*) begin rhs_array_muxed34 <= 1'd0; @@ -11799,12 +12310,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_325 = dummy_s; + dummy_d_329 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_326; +reg dummy_d_330; // synthesis translate_on always @(*) begin rhs_array_muxed35 <= 1'd0; @@ -11814,12 +12325,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_326 = dummy_s; + dummy_d_330 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_327; +reg dummy_d_331; // synthesis translate_on always @(*) begin array_muxed0 <= 3'd0; @@ -11838,12 +12349,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_327 = dummy_s; + dummy_d_331 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_328; +reg dummy_d_332; // synthesis translate_on always @(*) begin array_muxed1 <= 14'd0; @@ -11862,12 +12373,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_328 = dummy_s; + dummy_d_332 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_329; +reg dummy_d_333; // synthesis translate_on always @(*) begin array_muxed2 <= 1'd0; @@ -11886,12 +12397,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_329 = dummy_s; + dummy_d_333 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_330; +reg dummy_d_334; // synthesis translate_on always @(*) begin array_muxed3 <= 1'd0; @@ -11910,12 +12421,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_330 = dummy_s; + dummy_d_334 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_331; +reg dummy_d_335; // synthesis translate_on always @(*) begin array_muxed4 <= 1'd0; @@ -11934,12 +12445,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_331 = dummy_s; + dummy_d_335 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_332; +reg dummy_d_336; // synthesis translate_on always @(*) begin array_muxed5 <= 1'd0; @@ -11958,12 +12469,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_332 = dummy_s; + dummy_d_336 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_333; +reg dummy_d_337; // synthesis translate_on always @(*) begin array_muxed6 <= 1'd0; @@ -11982,12 +12493,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_333 = dummy_s; + dummy_d_337 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_334; +reg dummy_d_338; // synthesis translate_on always @(*) begin array_muxed7 <= 3'd0; @@ -12006,12 +12517,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_334 = dummy_s; + dummy_d_338 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_335; +reg dummy_d_339; // synthesis translate_on always @(*) begin array_muxed8 <= 14'd0; @@ -12030,12 +12541,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_335 = dummy_s; + dummy_d_339 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_336; +reg dummy_d_340; // synthesis translate_on always @(*) begin array_muxed9 <= 1'd0; @@ -12054,12 +12565,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_336 = dummy_s; + dummy_d_340 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_337; +reg dummy_d_341; // synthesis translate_on always @(*) begin array_muxed10 <= 1'd0; @@ -12078,12 +12589,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_341 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_338; +reg dummy_d_342; // synthesis translate_on always @(*) begin array_muxed11 <= 1'd0; @@ -12102,12 +12613,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_342 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_343; // synthesis translate_on always @(*) begin array_muxed12 <= 1'd0; @@ -12126,12 +12637,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_343 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_344; // synthesis translate_on always @(*) begin array_muxed13 <= 1'd0; @@ -12150,12 +12661,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_344 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_345; // synthesis translate_on always @(*) begin array_muxed14 <= 3'd0; @@ -12174,12 +12685,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_345 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_346; // synthesis translate_on always @(*) begin array_muxed15 <= 14'd0; @@ -12198,12 +12709,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_346 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_347; // synthesis translate_on always @(*) begin array_muxed16 <= 1'd0; @@ -12222,12 +12733,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_347 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_344; +reg dummy_d_348; // synthesis translate_on always @(*) begin array_muxed17 <= 1'd0; @@ -12246,12 +12757,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_348 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_345; +reg dummy_d_349; // synthesis translate_on always @(*) begin array_muxed18 <= 1'd0; @@ -12270,12 +12781,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_349 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_350; // synthesis translate_on always @(*) begin array_muxed19 <= 1'd0; @@ -12294,12 +12805,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_350 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_351; // synthesis translate_on always @(*) begin array_muxed20 <= 1'd0; @@ -12318,12 +12829,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_351 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_352; // synthesis translate_on always @(*) begin array_muxed21 <= 3'd0; @@ -12342,12 +12853,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_352 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_353; // synthesis translate_on always @(*) begin array_muxed22 <= 14'd0; @@ -12366,12 +12877,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_353 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_354; // synthesis translate_on always @(*) begin array_muxed23 <= 1'd0; @@ -12390,12 +12901,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_354 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_355; // synthesis translate_on always @(*) begin array_muxed24 <= 1'd0; @@ -12414,12 +12925,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_355 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_356; // synthesis translate_on always @(*) begin array_muxed25 <= 1'd0; @@ -12438,12 +12949,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_356 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_357; // synthesis translate_on always @(*) begin array_muxed26 <= 1'd0; @@ -12462,12 +12973,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_357 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_358; // synthesis translate_on always @(*) begin array_muxed27 <= 1'd0; @@ -12486,7 +12997,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_358 = dummy_s; // synthesis translate_on end assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset); @@ -12507,6 +13018,7 @@ always @(posedge iodelay_clk) begin end always @(posedge sys_clk) begin + state <= next_state; a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1); a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1); a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en; @@ -12522,112 +13034,112 @@ always @(posedge sys_clk) begin if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip0_value <= 1'd0; end - a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[15:8]}; + a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip1_value <= 1'd0; end - a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[15:8]}; + a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip2_value <= 1'd0; end - a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[15:8]}; + a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip3_value <= 1'd0; end - a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[15:8]}; + a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip4_value <= 1'd0; end - a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[15:8]}; + a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip5_value <= 1'd0; end - a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[15:8]}; + a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip6_value <= 1'd0; end - a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[15:8]}; + a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip7_value <= 1'd0; end - a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[15:8]}; + a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip8_value <= 1'd0; end - a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[15:8]}; + a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip9_value <= 1'd0; end - a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[15:8]}; + a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip10_value <= 1'd0; end - a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[15:8]}; + a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip11_value <= 1'd0; end - a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[15:8]}; + a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip12_value <= 1'd0; end - a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[15:8]}; + a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip13_value <= 1'd0; end - a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[15:8]}; + a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip14_value <= 1'd0; end - a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[15:8]}; + a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip15_value <= 1'd0; end - a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[15:8]}; + a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[23:8]}; if (litedramcore_inti_p0_rddata_valid) begin litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata; end @@ -14161,22 +14673,22 @@ always @(posedge sys_clk) begin a7ddrphy_dqs_oe_delayed <= 1'd0; a7ddrphy_dqspattern_o1 <= 8'd0; a7ddrphy_dq_oe_delayed <= 1'd0; - a7ddrphy_bitslip0_value <= 3'd0; - a7ddrphy_bitslip1_value <= 3'd0; - a7ddrphy_bitslip2_value <= 3'd0; - a7ddrphy_bitslip3_value <= 3'd0; - a7ddrphy_bitslip4_value <= 3'd0; - a7ddrphy_bitslip5_value <= 3'd0; - a7ddrphy_bitslip6_value <= 3'd0; - a7ddrphy_bitslip7_value <= 3'd0; - a7ddrphy_bitslip8_value <= 3'd0; - a7ddrphy_bitslip9_value <= 3'd0; - a7ddrphy_bitslip10_value <= 3'd0; - a7ddrphy_bitslip11_value <= 3'd0; - a7ddrphy_bitslip12_value <= 3'd0; - a7ddrphy_bitslip13_value <= 3'd0; - a7ddrphy_bitslip14_value <= 3'd0; - a7ddrphy_bitslip15_value <= 3'd0; + a7ddrphy_bitslip0_value <= 4'd0; + a7ddrphy_bitslip1_value <= 4'd0; + a7ddrphy_bitslip2_value <= 4'd0; + a7ddrphy_bitslip3_value <= 4'd0; + a7ddrphy_bitslip4_value <= 4'd0; + a7ddrphy_bitslip5_value <= 4'd0; + a7ddrphy_bitslip6_value <= 4'd0; + a7ddrphy_bitslip7_value <= 4'd0; + a7ddrphy_bitslip8_value <= 4'd0; + a7ddrphy_bitslip9_value <= 4'd0; + a7ddrphy_bitslip10_value <= 4'd0; + a7ddrphy_bitslip11_value <= 4'd0; + a7ddrphy_bitslip12_value <= 4'd0; + a7ddrphy_bitslip13_value <= 4'd0; + a7ddrphy_bitslip14_value <= 4'd0; + a7ddrphy_bitslip15_value <= 4'd0; a7ddrphy_rddata_en_last <= 8'd0; a7ddrphy_wrdata_en_last <= 4'd0; litedramcore_storage <= 4'd0; @@ -14358,6 +14870,7 @@ always @(posedge sys_clk) begin init_done_re <= 1'd0; init_error_storage <= 1'd0; init_error_re <= 1'd0; + state <= 1'd0; refresher_state <= 2'd0; bankmachine0_state <= 4'd0; bankmachine1_state <= 4'd0; diff --git a/litedram/generated/nexys-video/litedram-wrapper.vhdl b/litedram/generated/nexys-video/litedram-wrapper.vhdl index 46ae4b1..fd9f3bd 100644 --- a/litedram/generated/nexys-video/litedram-wrapper.vhdl +++ b/litedram/generated/nexys-video/litedram-wrapper.vhdl @@ -25,7 +25,7 @@ entity litedram_wrapper is -- Wishbone ports: wb_in : in wishbone_master_out; wb_out : out wishbone_slave_out; - wb_is_csr : in std_ulogic; + wb_is_ctrl : in std_ulogic; wb_is_init : in std_ulogic; -- Init core serial debug @@ -58,32 +58,39 @@ end entity litedram_wrapper; architecture behaviour of litedram_wrapper is component litedram_core port ( - clk : in std_ulogic; - rst : in std_ulogic; - pll_locked : out std_ulogic; - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic; - init_done : out std_ulogic; - init_error : out std_ulogic; - user_clk : out std_ulogic; - user_rst : out std_ulogic; - csr_port0_adr : in std_ulogic_vector(13 downto 0); - csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(31 downto 0); - csr_port0_dat_r : out std_ulogic_vector(31 downto 0); + clk : in std_ulogic; + rst : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -112,20 +119,19 @@ architecture behaviour of litedram_wrapper is signal ad3 : std_ulogic; - signal dram_user_reset : std_ulogic; - - signal csr_port0_adr : std_ulogic_vector(13 downto 0); - signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); - signal csr_port_read_comb : std_ulogic_vector(63 downto 0); - signal csr_valid : std_ulogic; - signal csr_write_valid : std_ulogic; + signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); + signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); + signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0); + signal wb_ctrl_sel : std_ulogic_vector(3 downto 0); + signal wb_ctrl_cyc : std_ulogic; + signal wb_ctrl_stb : std_ulogic; + signal wb_ctrl_ack : std_ulogic; + signal wb_ctrl_we : std_ulogic; signal wb_init_in : wishbone_master_out; signal wb_init_out : wishbone_slave_out; - type state_t is (CMD, MWRITE, MREAD, CSR); + type state_t is (CMD, MWRITE, MREAD); signal state : state_t; constant INIT_RAM_SIZE : integer := 16384; @@ -192,7 +198,7 @@ begin ad3 <= wb_in.adr(3); -- DRAM data interface signals - user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) + user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_ctrl and not wb_is_init) when state = CMD else '0'; user_port0_cmd_we <= wb_in.we when state = CMD else '0'; user_port0_wdata_valid <= '1' when state = MWRITE else '0'; @@ -202,31 +208,28 @@ begin user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else "00000000" & wb_in.sel; - -- DRAM CSR interface signals. We only support access to the bottom byte - csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; - csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(31 downto 0); - csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; + -- DRAM ctrl interface signals + wb_ctrl_adr <= x"0000" & wb_in.adr(15 downto 2); + wb_ctrl_dat_w <= wb_in.dat(31 downto 0); + wb_ctrl_sel <= wb_in.sel(3 downto 0); + wb_ctrl_cyc <= wb_in.cyc and wb_is_ctrl; + wb_ctrl_stb <= wb_in.stb and wb_is_ctrl; + wb_ctrl_we <= wb_in.we; -- Wishbone out signals - wb_out.ack <= '1' when state = CSR else + wb_out.ack <= wb_ctrl_ack when wb_is_ctrl ='1' else wb_init_out.ack when wb_is_init = '1' else user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000" & csr_port0_dat_r; - wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else + wb_out.dat <= (x"00000000" & wb_ctrl_dat_r) when wb_is_ctrl = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(63 downto 0); -- We don't do pipelining yet. wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - -- Reset ignored, the reset controller use the pll lock signal, - -- and alternate core reset address set when DRAM is not initialized. - -- - system_reset <= '0'; + -- Use alternate core reset address set when DRAM is not initialized. core_alt_reset <= not init_done; -- State machine @@ -234,14 +237,12 @@ begin begin if rising_edge(system_clk) then - if dram_user_reset = '1' then + if system_reset = '1' then state <= CMD; else case state is when CMD => - if csr_valid = '1' then - state <= CSR; - elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then + if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then state <= MWRITE when wb_in.we = '1' else MREAD; end if; when MWRITE => @@ -252,8 +253,6 @@ begin if user_port0_rdata_valid = '1' then state <= CMD; end if; - when CSR => - state <= CMD; end case; end if; end if; @@ -282,11 +281,18 @@ begin init_done => init_done, init_error => init_error, user_clk => system_clk, - user_rst => dram_user_reset, - csr_port0_adr => csr_port0_adr, - csr_port0_we => csr_port0_we, - csr_port0_dat_w => csr_port0_dat_w, - csr_port0_dat_r => csr_port0_dat_r, + user_rst => system_reset, + wb_ctrl_adr => wb_ctrl_adr, + wb_ctrl_dat_w => wb_ctrl_dat_w, + wb_ctrl_dat_r => wb_ctrl_dat_r, + wb_ctrl_sel => wb_ctrl_sel, + wb_ctrl_cyc => wb_ctrl_cyc, + wb_ctrl_stb => wb_ctrl_stb, + wb_ctrl_ack => wb_ctrl_ack, + wb_ctrl_we => wb_ctrl_we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, user_port_native_0_cmd_valid => user_port0_cmd_valid, user_port_native_0_cmd_ready => user_port0_cmd_ready, user_port_native_0_cmd_we => user_port0_cmd_we, diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index 7708f27..508f707 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ffff782107c6 3d80000060213f00 798c07c6618c0000 -618c1168658cffff +618c108c658cffff 4e8004217d8903a6 0000000048000002 0000000000000000 @@ -510,120 +510,113 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -38429d003c4c0001 -600000003d20c000 -7929002061292000 -3d40c000f9228000 -614a201839200035 -7c0004ac794a0020 -4e8000207d2057aa -0000000000000000 -3c4c000100000000 -6000000038429cbc -39290010e9228000 -7d204eaa7c0004ac -4082ffe871290008 -e922800060000000 -7c604faa7c0004ac -000000004e800020 -0000000000000000 -38429c783c4c0001 +38429f003c4c0001 fbc1fff07c0802a6 -7fc32214fbe1fff8 -f80100107c7f1b78 -7fbff040f821ffd1 -38210030409e000c -893f000048001908 -409e000c2f89000a -4bffff813860000d -3bff0001887f0000 -4bffffd04bffff75 +f8010010fbe1fff8 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+4e8000207d2057ea +0000000000000000 +3c4c000100000000 +7c0802a638428cec +fbe1fff8fbc1fff0 +f80100103bc3ffff +8ffe0001f821ffd1 +409e00102fbf0000 +3860000038210030 +2b9f000a48000a20 +3860000d409e000c +7fe3fb784bffff81 +4bffffd04bffff79 0100000000000000 -2c24000000000980 +2c24000000000280 3881fff040820008 f86400002b850024 4d9d002038600000 @@ -1064,7 +1149,7 @@ e8e400007c691a14 7c6307b43863ffe0 000000004e800020 0000000000000000 -38428bb03c4c0001 +38428b083c4c0001 3d2037367c0802a6 612935347d908026 65293332792907c6 @@ -1098,7 +1183,7 @@ fbfd00007fe9fa14 4bfffff07d29f392 0300000000000000 3c4c000100000580 -7c0802a638428aa4 +7c0802a6384289fc f821ffb1480006e9 7c7f1b78eb630000 7cbd2b787c9c2378 @@ -1114,7 +1199,7 @@ f821ffb1480006e9 4bffffb8f93f0000 0100000000000000 3c4c000100000580 -7c0802a638428a24 +7c0802a63842897c f821ffa148000661 7c9b23787c7d1b78 388000007ca32b78 @@ -1145,16 +1230,16 @@ e95d00009b270000 f95d0000394a0001 000000004bffffa8 0000078001000000 -384289283c4c0001 +384288803c4c0001 480005397c0802a6 7c741b79f821fed1 38600000f8610060 2fa4000041820068 39210040419e0060 -3ac4ffff3e42ffff +3ac4ffff60000000 f92100703b410020 -3ae000003d22ffff -3a527fb039297ff8 +3ae0000060000000 +3a428060392280a8 f92100783ba10060 ebc1006089250000 419e00102fa90000 @@ -1362,9 +1447,9 @@ e8010010ebc1fff0 203a4b4c43202020 7a484d20646c6c25 000000000000000a -6564346264343964 +6138393331393333 0000000000000000 -0036656663396364 +0033306536316430 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1402,10 +1487,10 @@ e8010010ebc1fff0 000000000000002d 30252d2b64323025 0000000000006432 -0000000000000830 -0000000000000860 -0000000000000890 -00000000000008c0 +00000000c0100830 +00000000c0100860 +00000000c0100890 +00000000c01008c0 6f6e204d41524453 207265646e752077 6572617764726168 @@ -1416,12 +1501,13 @@ e8010010ebc1fff0 00000a2e2e2e4d41 76656c2064616552 000a3a676e696c65 -642562202c64256d -00000000007c203a +302562202c64256d +0000007c203a6432 0000000000006425 000000000000207c 256d203a74736562 -0020642562202c64 +6432302562202c64 +0000000000000020 0000000078323025 6f6e204d41524453 207265646e752077 diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index 854f4c6..57ecfd7 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:13 +// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 09:40:28 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -22,10 +22,17 @@ module litedram_core( output wire ddram_reset_n, output wire init_done, output wire init_error, - input wire [13:0] csr_port0_adr, - input wire csr_port0_we, - input wire [31:0] csr_port0_dat_w, - output wire [31:0] csr_port0_dat_r, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, @@ -41,6 +48,21 @@ module litedram_core( output wire [127:0] user_port_native_0_rdata_data ); +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +wire [31:0] litedramcore_dat_w; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +wire [31:0] litedramcore_wishbone_dat_r; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; @@ -185,8 +207,8 @@ wire a7ddrphy_dq_t0; wire [7:0] a7ddrphy_dq_i_data0; wire [7:0] a7ddrphy_bitslip0_i; reg [7:0] a7ddrphy_bitslip0_o = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value = 3'd0; -reg [15:0] a7ddrphy_bitslip0_r = 16'd0; +reg [3:0] a7ddrphy_bitslip0_value = 4'd0; +reg [23:0] a7ddrphy_bitslip0_r = 24'd0; wire a7ddrphy_dq_o_nodelay1; wire a7ddrphy_dq_i_nodelay1; wire a7ddrphy_dq_i_delayed1; @@ -194,8 +216,8 @@ wire a7ddrphy_dq_t1; wire [7:0] a7ddrphy_dq_i_data1; wire [7:0] a7ddrphy_bitslip1_i; reg [7:0] a7ddrphy_bitslip1_o = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value = 3'd0; -reg [15:0] a7ddrphy_bitslip1_r = 16'd0; +reg [3:0] a7ddrphy_bitslip1_value = 4'd0; +reg [23:0] a7ddrphy_bitslip1_r = 24'd0; wire a7ddrphy_dq_o_nodelay2; wire a7ddrphy_dq_i_nodelay2; wire a7ddrphy_dq_i_delayed2; @@ -203,8 +225,8 @@ wire a7ddrphy_dq_t2; wire [7:0] a7ddrphy_dq_i_data2; wire [7:0] a7ddrphy_bitslip2_i; reg [7:0] a7ddrphy_bitslip2_o = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value = 3'd0; -reg [15:0] a7ddrphy_bitslip2_r = 16'd0; +reg [3:0] a7ddrphy_bitslip2_value = 4'd0; +reg [23:0] a7ddrphy_bitslip2_r = 24'd0; wire a7ddrphy_dq_o_nodelay3; wire a7ddrphy_dq_i_nodelay3; wire a7ddrphy_dq_i_delayed3; @@ -212,8 +234,8 @@ wire a7ddrphy_dq_t3; wire [7:0] a7ddrphy_dq_i_data3; wire [7:0] a7ddrphy_bitslip3_i; reg [7:0] a7ddrphy_bitslip3_o = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value = 3'd0; -reg [15:0] a7ddrphy_bitslip3_r = 16'd0; +reg [3:0] a7ddrphy_bitslip3_value = 4'd0; +reg [23:0] a7ddrphy_bitslip3_r = 24'd0; wire a7ddrphy_dq_o_nodelay4; wire a7ddrphy_dq_i_nodelay4; wire a7ddrphy_dq_i_delayed4; @@ -221,8 +243,8 @@ wire a7ddrphy_dq_t4; wire [7:0] a7ddrphy_dq_i_data4; wire [7:0] a7ddrphy_bitslip4_i; reg [7:0] a7ddrphy_bitslip4_o = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value = 3'd0; -reg [15:0] a7ddrphy_bitslip4_r = 16'd0; +reg [3:0] a7ddrphy_bitslip4_value = 4'd0; +reg [23:0] a7ddrphy_bitslip4_r = 24'd0; wire a7ddrphy_dq_o_nodelay5; wire a7ddrphy_dq_i_nodelay5; wire a7ddrphy_dq_i_delayed5; @@ -230,8 +252,8 @@ wire a7ddrphy_dq_t5; wire [7:0] a7ddrphy_dq_i_data5; wire [7:0] a7ddrphy_bitslip5_i; reg [7:0] a7ddrphy_bitslip5_o = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value = 3'd0; -reg [15:0] a7ddrphy_bitslip5_r = 16'd0; +reg [3:0] a7ddrphy_bitslip5_value = 4'd0; +reg [23:0] a7ddrphy_bitslip5_r = 24'd0; wire a7ddrphy_dq_o_nodelay6; wire a7ddrphy_dq_i_nodelay6; wire a7ddrphy_dq_i_delayed6; @@ -239,8 +261,8 @@ wire a7ddrphy_dq_t6; wire [7:0] a7ddrphy_dq_i_data6; wire [7:0] a7ddrphy_bitslip6_i; reg [7:0] a7ddrphy_bitslip6_o = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value = 3'd0; -reg [15:0] a7ddrphy_bitslip6_r = 16'd0; +reg [3:0] a7ddrphy_bitslip6_value = 4'd0; +reg [23:0] a7ddrphy_bitslip6_r = 24'd0; wire a7ddrphy_dq_o_nodelay7; wire a7ddrphy_dq_i_nodelay7; wire a7ddrphy_dq_i_delayed7; @@ -248,8 +270,8 @@ wire a7ddrphy_dq_t7; wire [7:0] a7ddrphy_dq_i_data7; wire [7:0] a7ddrphy_bitslip7_i; reg [7:0] a7ddrphy_bitslip7_o = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value = 3'd0; -reg [15:0] a7ddrphy_bitslip7_r = 16'd0; +reg [3:0] a7ddrphy_bitslip7_value = 4'd0; +reg [23:0] a7ddrphy_bitslip7_r = 24'd0; wire a7ddrphy_dq_o_nodelay8; wire a7ddrphy_dq_i_nodelay8; wire a7ddrphy_dq_i_delayed8; @@ -257,8 +279,8 @@ wire a7ddrphy_dq_t8; wire [7:0] a7ddrphy_dq_i_data8; wire [7:0] a7ddrphy_bitslip8_i; reg [7:0] a7ddrphy_bitslip8_o = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value = 3'd0; -reg [15:0] a7ddrphy_bitslip8_r = 16'd0; +reg [3:0] a7ddrphy_bitslip8_value = 4'd0; +reg [23:0] a7ddrphy_bitslip8_r = 24'd0; wire a7ddrphy_dq_o_nodelay9; wire a7ddrphy_dq_i_nodelay9; wire a7ddrphy_dq_i_delayed9; @@ -266,8 +288,8 @@ wire a7ddrphy_dq_t9; wire [7:0] a7ddrphy_dq_i_data9; wire [7:0] a7ddrphy_bitslip9_i; reg [7:0] a7ddrphy_bitslip9_o = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value = 3'd0; -reg [15:0] a7ddrphy_bitslip9_r = 16'd0; +reg [3:0] a7ddrphy_bitslip9_value = 4'd0; +reg [23:0] a7ddrphy_bitslip9_r = 24'd0; wire a7ddrphy_dq_o_nodelay10; wire a7ddrphy_dq_i_nodelay10; wire a7ddrphy_dq_i_delayed10; @@ -275,8 +297,8 @@ wire a7ddrphy_dq_t10; wire [7:0] a7ddrphy_dq_i_data10; wire [7:0] a7ddrphy_bitslip10_i; reg [7:0] a7ddrphy_bitslip10_o = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value = 3'd0; -reg [15:0] a7ddrphy_bitslip10_r = 16'd0; +reg [3:0] a7ddrphy_bitslip10_value = 4'd0; +reg [23:0] a7ddrphy_bitslip10_r = 24'd0; wire a7ddrphy_dq_o_nodelay11; wire a7ddrphy_dq_i_nodelay11; wire a7ddrphy_dq_i_delayed11; @@ -284,8 +306,8 @@ wire a7ddrphy_dq_t11; wire [7:0] a7ddrphy_dq_i_data11; wire [7:0] a7ddrphy_bitslip11_i; reg [7:0] a7ddrphy_bitslip11_o = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value = 3'd0; -reg [15:0] a7ddrphy_bitslip11_r = 16'd0; +reg [3:0] a7ddrphy_bitslip11_value = 4'd0; +reg [23:0] a7ddrphy_bitslip11_r = 24'd0; wire a7ddrphy_dq_o_nodelay12; wire a7ddrphy_dq_i_nodelay12; wire a7ddrphy_dq_i_delayed12; @@ -293,8 +315,8 @@ wire a7ddrphy_dq_t12; wire [7:0] a7ddrphy_dq_i_data12; wire [7:0] a7ddrphy_bitslip12_i; reg [7:0] a7ddrphy_bitslip12_o = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value = 3'd0; -reg [15:0] a7ddrphy_bitslip12_r = 16'd0; +reg [3:0] a7ddrphy_bitslip12_value = 4'd0; +reg [23:0] a7ddrphy_bitslip12_r = 24'd0; wire a7ddrphy_dq_o_nodelay13; wire a7ddrphy_dq_i_nodelay13; wire a7ddrphy_dq_i_delayed13; @@ -302,8 +324,8 @@ wire a7ddrphy_dq_t13; wire [7:0] a7ddrphy_dq_i_data13; wire [7:0] a7ddrphy_bitslip13_i; reg [7:0] a7ddrphy_bitslip13_o = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value = 3'd0; -reg [15:0] a7ddrphy_bitslip13_r = 16'd0; +reg [3:0] a7ddrphy_bitslip13_value = 4'd0; +reg [23:0] a7ddrphy_bitslip13_r = 24'd0; wire a7ddrphy_dq_o_nodelay14; wire a7ddrphy_dq_i_nodelay14; wire a7ddrphy_dq_i_delayed14; @@ -311,8 +333,8 @@ wire a7ddrphy_dq_t14; wire [7:0] a7ddrphy_dq_i_data14; wire [7:0] a7ddrphy_bitslip14_i; reg [7:0] a7ddrphy_bitslip14_o = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value = 3'd0; -reg [15:0] a7ddrphy_bitslip14_r = 16'd0; +reg [3:0] a7ddrphy_bitslip14_value = 4'd0; +reg [23:0] a7ddrphy_bitslip14_r = 24'd0; wire a7ddrphy_dq_o_nodelay15; wire a7ddrphy_dq_i_nodelay15; wire a7ddrphy_dq_i_delayed15; @@ -320,8 +342,8 @@ wire a7ddrphy_dq_t15; wire [7:0] a7ddrphy_dq_i_data15; wire [7:0] a7ddrphy_bitslip15_i; reg [7:0] a7ddrphy_bitslip15_o = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value = 3'd0; -reg [15:0] a7ddrphy_bitslip15_r = 16'd0; +reg [3:0] a7ddrphy_bitslip15_value = 4'd0; +reg [23:0] a7ddrphy_bitslip15_r = 24'd0; wire [7:0] a7ddrphy_rddata_en; reg [7:0] a7ddrphy_rddata_en_last = 8'd0; wire [3:0] a7ddrphy_wrdata_en; @@ -1483,10 +1505,17 @@ reg init_done_storage = 1'd0; reg init_done_re = 1'd0; reg init_error_storage = 1'd0; reg init_error_re = 1'd0; -wire [13:0] csr_port_adr; -wire csr_port_we; -wire [31:0] csr_port_dat_w; -wire [31:0] csr_port_dat_r; +wire [29:0] wb_bus_adr; +wire [31:0] wb_bus_dat_w; +wire [31:0] wb_bus_dat_r; +wire [3:0] wb_bus_sel; +wire wb_bus_cyc; +wire wb_bus_stb; +wire wb_bus_ack; +wire wb_bus_we; +wire [2:0] wb_bus_cti; +wire [1:0] wb_bus_bte; +wire wb_bus_err; wire user_port_cmd_valid; wire user_port_cmd_ready; wire user_port_cmd_payload_we; @@ -1498,6 +1527,8 @@ wire [15:0] user_port_wdata_payload_we; wire user_port_rdata_valid; wire user_port_rdata_ready; wire [127:0] user_port_rdata_payload_data; +reg state = 1'd0; +reg next_state = 1'd0; wire pll_fb0; wire pll_fb1; reg [1:0] refresher_state = 2'd0; @@ -1774,10 +1805,17 @@ initial dummy_s <= 1'd0; // synthesis translate_on assign init_done = init_done_storage; assign init_error = init_error_storage; -assign csr_port_adr = csr_port0_adr; -assign csr_port_we = csr_port0_we; -assign csr_port_dat_w = csr_port0_dat_w; -assign csr_port0_dat_r = csr_port_dat_r; +assign wb_bus_adr = wb_ctrl_adr; +assign wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_bus_dat_r; +assign wb_bus_sel = wb_ctrl_sel; +assign wb_bus_cyc = wb_ctrl_cyc; +assign wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = wb_bus_ack; +assign wb_bus_we = wb_ctrl_we; +assign wb_bus_cti = wb_ctrl_cti; +assign wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; assign user_port_cmd_valid = user_port_native_0_cmd_valid; @@ -1791,6 +1829,84 @@ assign user_port_wdata_payload_data = user_port_native_0_wdata_data; assign user_port_native_0_rdata_valid = user_port_rdata_valid; assign user_port_rdata_ready = user_port_native_0_rdata_ready; assign user_port_native_0_rdata_data = user_port_rdata_payload_data; +assign litedramcore_dat_w = litedramcore_wishbone_dat_w; +assign litedramcore_wishbone_dat_r = litedramcore_dat_r; + +// synthesis translate_off +reg dummy_d; +// synthesis translate_on +always @(*) begin + next_state <= 1'd0; + next_state <= state; + case (state) + 1'd1: begin + next_state <= 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + next_state <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_1; +// synthesis translate_on +always @(*) begin + litedramcore_adr <= 14'd0; + case (state) + 1'd1: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr <= litedramcore_wishbone_adr; + end + end + endcase +// synthesis translate_off + dummy_d_1 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_2; +// synthesis translate_on +always @(*) begin + litedramcore_we <= 1'd0; + case (state) + 1'd1: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we <= litedramcore_wishbone_we; + end + end + endcase +// synthesis translate_off + dummy_d_2 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_3; +// synthesis translate_on +always @(*) begin + litedramcore_wishbone_ack <= 1'd0; + case (state) + 1'd1: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_3 = dummy_s; +// synthesis translate_on +end assign sys_pll_reset = rst; assign pll_locked = sys_pll_locked; assign iodelay_pll_reset = rst; @@ -1803,7 +1919,7 @@ assign iodelay_clk = s7pll1_clkout_buf; assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0; // synthesis translate_off -reg dummy_d; +reg dummy_d_4; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p0_rddata <= 32'd0; @@ -1840,12 +1956,12 @@ always @(*) begin a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0]; a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1]; // synthesis translate_off - dummy_d = dummy_s; + dummy_d_4 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_1; +reg dummy_d_5; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p1_rddata <= 32'd0; @@ -1882,12 +1998,12 @@ always @(*) begin a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2]; a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3]; // synthesis translate_off - dummy_d_1 = dummy_s; + dummy_d_5 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_2; +reg dummy_d_6; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p2_rddata <= 32'd0; @@ -1924,12 +2040,12 @@ always @(*) begin a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4]; a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5]; // synthesis translate_off - dummy_d_2 = dummy_s; + dummy_d_6 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_3; +reg dummy_d_7; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p3_rddata <= 32'd0; @@ -1966,7 +2082,7 @@ always @(*) begin a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6]; a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7]; // synthesis translate_off - dummy_d_3 = dummy_s; + dummy_d_7 = dummy_s; // synthesis translate_on end assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1; @@ -1989,7 +2105,7 @@ assign a7ddrphy_wrdata_en = {a7ddrphy_wrdata_en_last, a7ddrphy_dfi_p3_wrdata_en} assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2]; // synthesis translate_off -reg dummy_d_4; +reg dummy_d_8; // synthesis translate_on always @(*) begin a7ddrphy_dqs_oe <= 1'd0; @@ -1999,14 +2115,14 @@ always @(*) begin a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; end // synthesis translate_off - dummy_d_4 = dummy_s; + dummy_d_8 = dummy_s; // synthesis translate_on end assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2])); assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2])); // synthesis translate_off -reg dummy_d_5; +reg dummy_d_9; // synthesis translate_on always @(*) begin a7ddrphy_dqspattern_o0 <= 8'd0; @@ -2024,12 +2140,12 @@ always @(*) begin end end // synthesis translate_off - dummy_d_5 = dummy_s; + dummy_d_9 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_6; +reg dummy_d_10; // synthesis translate_on always @(*) begin a7ddrphy_bitslip0_o <= 8'd0; @@ -2058,14 +2174,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[22:15]; + end endcase // synthesis translate_off - dummy_d_6 = dummy_s; + dummy_d_10 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_7; +reg dummy_d_11; // synthesis translate_on always @(*) begin a7ddrphy_bitslip1_o <= 8'd0; @@ -2094,14 +2234,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[22:15]; + end endcase // synthesis translate_off - dummy_d_7 = dummy_s; + dummy_d_11 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_8; +reg dummy_d_12; // synthesis translate_on always @(*) begin a7ddrphy_bitslip2_o <= 8'd0; @@ -2130,14 +2294,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[22:15]; + end endcase // synthesis translate_off - dummy_d_8 = dummy_s; + dummy_d_12 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_9; +reg dummy_d_13; // synthesis translate_on always @(*) begin a7ddrphy_bitslip3_o <= 8'd0; @@ -2166,14 +2354,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[22:15]; + end endcase // synthesis translate_off - dummy_d_9 = dummy_s; + dummy_d_13 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_10; +reg dummy_d_14; // synthesis translate_on always @(*) begin a7ddrphy_bitslip4_o <= 8'd0; @@ -2202,14 +2414,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[22:15]; + end endcase // synthesis translate_off - dummy_d_10 = dummy_s; + dummy_d_14 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_11; +reg dummy_d_15; // synthesis translate_on always @(*) begin a7ddrphy_bitslip5_o <= 8'd0; @@ -2238,14 +2474,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[22:15]; + end endcase // synthesis translate_off - dummy_d_11 = dummy_s; + dummy_d_15 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_12; +reg dummy_d_16; // synthesis translate_on always @(*) begin a7ddrphy_bitslip6_o <= 8'd0; @@ -2274,14 +2534,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[22:15]; + end endcase // synthesis translate_off - dummy_d_12 = dummy_s; + dummy_d_16 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_13; +reg dummy_d_17; // synthesis translate_on always @(*) begin a7ddrphy_bitslip7_o <= 8'd0; @@ -2310,14 +2594,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[22:15]; + end endcase // synthesis translate_off - dummy_d_13 = dummy_s; + dummy_d_17 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_14; +reg dummy_d_18; // synthesis translate_on always @(*) begin a7ddrphy_bitslip8_o <= 8'd0; @@ -2346,14 +2654,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[22:15]; + end endcase // synthesis translate_off - dummy_d_14 = dummy_s; + dummy_d_18 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_15; +reg dummy_d_19; // synthesis translate_on always @(*) begin a7ddrphy_bitslip9_o <= 8'd0; @@ -2382,14 +2714,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[22:15]; + end endcase // synthesis translate_off - dummy_d_15 = dummy_s; + dummy_d_19 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_16; +reg dummy_d_20; // synthesis translate_on always @(*) begin a7ddrphy_bitslip10_o <= 8'd0; @@ -2418,14 +2774,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[22:15]; + end endcase // synthesis translate_off - dummy_d_16 = dummy_s; + dummy_d_20 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_17; +reg dummy_d_21; // synthesis translate_on always @(*) begin a7ddrphy_bitslip11_o <= 8'd0; @@ -2454,14 +2834,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7]; end - endcase -// synthesis translate_off - dummy_d_17 = dummy_s; -// synthesis translate_on -end - + 4'd8: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[22:15]; + end + endcase // synthesis translate_off -reg dummy_d_18; + dummy_d_21 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_22; // synthesis translate_on always @(*) begin a7ddrphy_bitslip12_o <= 8'd0; @@ -2490,14 +2894,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[22:15]; + end endcase // synthesis translate_off - dummy_d_18 = dummy_s; + dummy_d_22 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_19; +reg dummy_d_23; // synthesis translate_on always @(*) begin a7ddrphy_bitslip13_o <= 8'd0; @@ -2526,14 +2954,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[22:15]; + end endcase // synthesis translate_off - dummy_d_19 = dummy_s; + dummy_d_23 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_20; +reg dummy_d_24; // synthesis translate_on always @(*) begin a7ddrphy_bitslip14_o <= 8'd0; @@ -2562,14 +3014,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[22:15]; + end endcase // synthesis translate_off - dummy_d_20 = dummy_s; + dummy_d_24 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_21; +reg dummy_d_25; // synthesis translate_on always @(*) begin a7ddrphy_bitslip15_o <= 8'd0; @@ -2598,9 +3074,33 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[22:15]; + end endcase // synthesis translate_off - dummy_d_21 = dummy_s; + dummy_d_25 = dummy_s; // synthesis translate_on end assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; @@ -2732,73 +3232,15 @@ assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; -// synthesis translate_off -reg dummy_d_22; -// synthesis translate_on -always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; - end else begin - litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; - end -// synthesis translate_off - dummy_d_22 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_23; -// synthesis translate_on -always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; - if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; - end else begin - end -// synthesis translate_off - dummy_d_23 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_24; -// synthesis translate_on -always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; - end else begin - litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; - end -// synthesis translate_off - dummy_d_24 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_25; -// synthesis translate_on -always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end else begin - end -// synthesis translate_off - dummy_d_25 = dummy_s; -// synthesis translate_on -end - // synthesis translate_off reg dummy_d_26; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cke <= 1'd0; + litedramcore_master_p1_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; end else begin - litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; + litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_26 = dummy_s; @@ -2809,11 +3251,10 @@ end reg dummy_d_27; // synthesis translate_on always @(*) begin - litedramcore_master_p1_odt <= 1'd0; + litedramcore_inti_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; end else begin - litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; + litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_27 = dummy_s; @@ -2824,11 +3265,11 @@ end reg dummy_d_28; // synthesis translate_on always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; + litedramcore_master_p1_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; end else begin - litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; + litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_28 = dummy_s; @@ -2839,11 +3280,11 @@ end reg dummy_d_29; // synthesis translate_on always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; + litedramcore_master_p1_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; end else begin - litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; + litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_29 = dummy_s; @@ -2854,11 +3295,11 @@ end reg dummy_d_30; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; + litedramcore_master_p2_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + litedramcore_master_p2_address <= litedramcore_slave_p2_address; end else begin - litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; + litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_30 = dummy_s; @@ -2869,10 +3310,11 @@ end reg dummy_d_31; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata <= 32'd0; + litedramcore_master_p2_bank <= 3'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; end else begin - litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; + litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_31 = dummy_s; @@ -2883,11 +3325,11 @@ end reg dummy_d_32; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; + litedramcore_master_p2_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; + litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_32 = dummy_s; @@ -2898,10 +3340,11 @@ end reg dummy_d_33; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata_valid <= 1'd0; + litedramcore_master_p2_cs_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; end else begin - litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_33 = dummy_s; @@ -2912,11 +3355,11 @@ end reg dummy_d_34; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; + litedramcore_master_p2_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; + litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; end // synthesis translate_off dummy_d_34 = dummy_s; @@ -2927,11 +3370,10 @@ end reg dummy_d_35; // synthesis translate_on always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; + litedramcore_slave_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; end else begin - litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_35 = dummy_s; @@ -2942,11 +3384,11 @@ end reg dummy_d_36; // synthesis translate_on always @(*) begin - litedramcore_master_p2_address <= 15'd0; + litedramcore_master_p2_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; end else begin - litedramcore_master_p2_address <= litedramcore_inti_p2_address; + litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; end // synthesis translate_off dummy_d_36 = dummy_s; @@ -2957,11 +3399,10 @@ end reg dummy_d_37; // synthesis translate_on always @(*) begin - litedramcore_master_p2_bank <= 3'd0; + litedramcore_slave_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end else begin - litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_37 = dummy_s; @@ -2972,11 +3413,11 @@ end reg dummy_d_38; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; + litedramcore_master_p2_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; end else begin - litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; + litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_38 = dummy_s; @@ -2987,11 +3428,10 @@ end reg dummy_d_39; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; + litedramcore_inti_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; end else begin - litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; + litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_39 = dummy_s; @@ -3002,11 +3442,11 @@ end reg dummy_d_40; // synthesis translate_on always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; + litedramcore_master_p2_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; end else begin - litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; + litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_40 = dummy_s; @@ -3017,10 +3457,11 @@ end reg dummy_d_41; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; + litedramcore_master_p2_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; end else begin + litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_41 = dummy_s; @@ -3031,11 +3472,11 @@ end reg dummy_d_42; // synthesis translate_on always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; + litedramcore_master_p2_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; end else begin - litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; + litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_42 = dummy_s; @@ -3046,10 +3487,11 @@ end reg dummy_d_43; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; + litedramcore_master_p2_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; end else begin + litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_43 = dummy_s; @@ -3060,11 +3502,10 @@ end reg dummy_d_44; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cke <= 1'd0; + litedramcore_inti_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; end else begin - litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; + litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_44 = dummy_s; @@ -3075,11 +3516,11 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - litedramcore_master_p2_odt <= 1'd0; + litedramcore_master_p2_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; end else begin - litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; + litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -3090,11 +3531,10 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; + litedramcore_inti_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; end else begin - litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; + litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -3105,11 +3545,11 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; + litedramcore_master_p2_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; end else begin - litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; + litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -3120,11 +3560,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; + litedramcore_master_p2_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; end else begin - litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; + litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -3135,10 +3575,11 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata <= 32'd0; + litedramcore_master_p3_address <= 15'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p3_address <= litedramcore_slave_p3_address; end else begin - litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; + litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -3149,11 +3590,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; + litedramcore_master_p3_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; + litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -3164,10 +3605,11 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata_valid <= 1'd0; + litedramcore_master_p3_cas_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; end else begin - litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -3178,11 +3620,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; + litedramcore_master_p3_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; + litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -3193,11 +3635,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; + litedramcore_master_p3_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; end else begin - litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; + litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -3208,11 +3650,10 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - litedramcore_master_p3_address <= 15'd0; + litedramcore_slave_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; end else begin - litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -3223,11 +3664,11 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - litedramcore_master_p3_bank <= 3'd0; + litedramcore_master_p3_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; end else begin - litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; + litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -3238,11 +3679,10 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; + litedramcore_slave_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end else begin - litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -3253,11 +3693,11 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; + litedramcore_master_p3_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; end else begin - litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; + litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; end // synthesis translate_off dummy_d_57 = dummy_s; @@ -3268,11 +3708,11 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; + litedramcore_master_p3_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; end else begin - litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; + litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -3283,10 +3723,11 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; + litedramcore_master_p3_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; end else begin + litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_59 = dummy_s; @@ -3297,11 +3738,11 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; + litedramcore_master_p3_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; end else begin - litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; + litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -3312,10 +3753,11 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; + litedramcore_master_p3_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; end else begin + litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_61 = dummy_s; @@ -3326,11 +3768,10 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cke <= 1'd0; + litedramcore_inti_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; end else begin - litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; + litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -3341,11 +3782,11 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - litedramcore_master_p3_odt <= 1'd0; + litedramcore_master_p3_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; end else begin - litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; + litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -3356,11 +3797,10 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; + litedramcore_inti_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; end else begin - litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; + litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -3371,11 +3811,11 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; + litedramcore_master_p3_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; end else begin - litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; + litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -3386,11 +3826,11 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; + litedramcore_master_p3_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; end else begin - litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; + litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -3401,10 +3841,11 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata <= 32'd0; + litedramcore_master_p0_address <= 15'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p0_address <= litedramcore_slave_p0_address; end else begin - litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -3415,11 +3856,11 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; + litedramcore_master_p0_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; + litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -3430,10 +3871,11 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata_valid <= 1'd0; + litedramcore_master_p0_cas_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; end else begin - litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -3444,11 +3886,11 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; + litedramcore_master_p0_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; + litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -3459,11 +3901,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; + litedramcore_master_p0_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; end else begin - litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; + litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -3474,11 +3916,10 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - litedramcore_master_p0_address <= 15'd0; + litedramcore_slave_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; end else begin - litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -3489,11 +3930,11 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - litedramcore_master_p0_bank <= 3'd0; + litedramcore_master_p0_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; end else begin - litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; + litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -3504,11 +3945,10 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; + litedramcore_slave_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end else begin - litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -3519,11 +3959,11 @@ end reg dummy_d_75; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; + litedramcore_master_p0_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; end else begin - litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; + litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; end // synthesis translate_off dummy_d_75 = dummy_s; @@ -3534,11 +3974,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; + litedramcore_master_p0_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; end else begin - litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; + litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -3549,10 +3989,11 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; + litedramcore_master_p0_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; end else begin + litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; end // synthesis translate_off dummy_d_77 = dummy_s; @@ -3563,11 +4004,11 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; + litedramcore_master_p0_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; end else begin - litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; + litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -3578,10 +4019,11 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; + litedramcore_master_p0_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; end else begin + litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; end // synthesis translate_off dummy_d_79 = dummy_s; @@ -3592,11 +4034,10 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cke <= 1'd0; + litedramcore_inti_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; end else begin - litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; + litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -3607,11 +4048,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - litedramcore_master_p0_odt <= 1'd0; + litedramcore_master_p0_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; end else begin - litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; + litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -3622,11 +4063,10 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; + litedramcore_inti_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; end else begin - litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; + litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -3637,11 +4077,11 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; + litedramcore_master_p0_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; end else begin - litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; + litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -3652,11 +4092,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; + litedramcore_master_p0_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; end else begin - litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; + litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -3667,10 +4107,11 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata <= 32'd0; + litedramcore_master_p1_address <= 15'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p1_address <= litedramcore_slave_p1_address; end else begin - litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; + litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -3681,11 +4122,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; + litedramcore_master_p1_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; + litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -3696,10 +4137,11 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata_valid <= 1'd0; + litedramcore_master_p1_cas_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; end else begin - litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -3710,11 +4152,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; + litedramcore_master_p1_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; + litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -3725,11 +4167,11 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; + litedramcore_master_p1_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; end else begin - litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; + litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -3740,11 +4182,10 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - litedramcore_master_p1_address <= 15'd0; + litedramcore_slave_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end else begin - litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -3755,11 +4196,11 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - litedramcore_master_p1_bank <= 3'd0; + litedramcore_master_p1_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; end else begin - litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; + litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -3770,11 +4211,10 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; + litedramcore_slave_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end else begin - litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -3785,16 +4225,76 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; + litedramcore_master_p1_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; end else begin - litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; + litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_93 = dummy_s; // synthesis translate_on end + +// synthesis translate_off +reg dummy_d_94; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_odt <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + end else begin + litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; + end +// synthesis translate_off + dummy_d_94 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_95; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_reset_n <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + end else begin + litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; + end +// synthesis translate_off + dummy_d_95 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_96; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_act_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + end else begin + litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; + end +// synthesis translate_off + dummy_d_96 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_97; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_wrdata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + end else begin + litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; + end +// synthesis translate_off + dummy_d_97 = dummy_s; +// synthesis translate_on +end assign litedramcore_inti_p0_cke = litedramcore_storage[1]; assign litedramcore_inti_p1_cke = litedramcore_storage[1]; assign litedramcore_inti_p2_cke = litedramcore_storage[1]; @@ -3809,7 +4309,22 @@ assign litedramcore_inti_p2_reset_n = litedramcore_storage[3]; assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; // synthesis translate_off -reg dummy_d_94; +reg dummy_d_98; +// synthesis translate_on +always @(*) begin + litedramcore_inti_p0_cs_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; + end else begin + litedramcore_inti_p0_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_98 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_99; // synthesis translate_on always @(*) begin litedramcore_inti_p0_ras_n <= 1'd1; @@ -3819,12 +4334,12 @@ always @(*) begin litedramcore_inti_p0_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_94 = dummy_s; + dummy_d_99 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_95; +reg dummy_d_100; // synthesis translate_on always @(*) begin litedramcore_inti_p0_we_n <= 1'd1; @@ -3834,12 +4349,12 @@ always @(*) begin litedramcore_inti_p0_we_n <= 1'd1; end // synthesis translate_off - dummy_d_95 = dummy_s; + dummy_d_100 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_96; +reg dummy_d_101; // synthesis translate_on always @(*) begin litedramcore_inti_p0_cas_n <= 1'd1; @@ -3849,33 +4364,33 @@ always @(*) begin litedramcore_inti_p0_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_96 = dummy_s; + dummy_d_101 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; +assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage; +assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]); +assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]); +assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; +assign litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_97; +reg dummy_d_102; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; + litedramcore_inti_p1_cs_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; end else begin - litedramcore_inti_p0_cs_n <= {1{1'd1}}; + litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_97 = dummy_s; + dummy_d_102 = dummy_s; // synthesis translate_on end -assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; -assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage; -assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]); -assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]); -assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; -assign litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_98; +reg dummy_d_103; // synthesis translate_on always @(*) begin litedramcore_inti_p1_ras_n <= 1'd1; @@ -3885,12 +4400,12 @@ always @(*) begin litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_98 = dummy_s; + dummy_d_103 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_99; +reg dummy_d_104; // synthesis translate_on always @(*) begin litedramcore_inti_p1_we_n <= 1'd1; @@ -3900,12 +4415,12 @@ always @(*) begin litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off - dummy_d_99 = dummy_s; + dummy_d_104 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_100; +reg dummy_d_105; // synthesis translate_on always @(*) begin litedramcore_inti_p1_cas_n <= 1'd1; @@ -3915,33 +4430,33 @@ always @(*) begin litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_100 = dummy_s; + dummy_d_105 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; +assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage; +assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]); +assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]); +assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; +assign litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_101; +reg dummy_d_106; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; + litedramcore_inti_p2_cs_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; end else begin - litedramcore_inti_p1_cs_n <= {1{1'd1}}; + litedramcore_inti_p2_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_101 = dummy_s; + dummy_d_106 = dummy_s; // synthesis translate_on end -assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; -assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage; -assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]); -assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]); -assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; -assign litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_102; +reg dummy_d_107; // synthesis translate_on always @(*) begin litedramcore_inti_p2_ras_n <= 1'd1; @@ -3951,12 +4466,12 @@ always @(*) begin litedramcore_inti_p2_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_102 = dummy_s; + dummy_d_107 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_103; +reg dummy_d_108; // synthesis translate_on always @(*) begin litedramcore_inti_p2_we_n <= 1'd1; @@ -3966,12 +4481,12 @@ always @(*) begin litedramcore_inti_p2_we_n <= 1'd1; end // synthesis translate_off - dummy_d_103 = dummy_s; + dummy_d_108 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_104; +reg dummy_d_109; // synthesis translate_on always @(*) begin litedramcore_inti_p2_cas_n <= 1'd1; @@ -3981,33 +4496,33 @@ always @(*) begin litedramcore_inti_p2_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_104 = dummy_s; + dummy_d_109 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage; +assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage; +assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]); +assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]); +assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; +assign litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_105; +reg dummy_d_110; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_cs_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; + litedramcore_inti_p3_cs_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; end else begin - litedramcore_inti_p2_cs_n <= {1{1'd1}}; + litedramcore_inti_p3_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_105 = dummy_s; + dummy_d_110 = dummy_s; // synthesis translate_on end -assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage; -assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage; -assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]); -assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]); -assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; -assign litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_106; +reg dummy_d_111; // synthesis translate_on always @(*) begin litedramcore_inti_p3_ras_n <= 1'd1; @@ -4017,12 +4532,12 @@ always @(*) begin litedramcore_inti_p3_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_106 = dummy_s; + dummy_d_111 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_107; +reg dummy_d_112; // synthesis translate_on always @(*) begin litedramcore_inti_p3_we_n <= 1'd1; @@ -4032,12 +4547,12 @@ always @(*) begin litedramcore_inti_p3_we_n <= 1'd1; end // synthesis translate_off - dummy_d_107 = dummy_s; + dummy_d_112 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_108; +reg dummy_d_113; // synthesis translate_on always @(*) begin litedramcore_inti_p3_cas_n <= 1'd1; @@ -4047,22 +4562,7 @@ always @(*) begin litedramcore_inti_p3_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_108 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_109; -// synthesis translate_on -always @(*) begin - litedramcore_inti_p3_cs_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; - end else begin - litedramcore_inti_p3_cs_n <= {1{1'd1}}; - end -// synthesis translate_off - dummy_d_109 = dummy_s; + dummy_d_113 = dummy_s; // synthesis translate_on end assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage; @@ -4142,7 +4642,7 @@ assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; // synthesis translate_off -reg dummy_d_110; +reg dummy_d_114; // synthesis translate_on always @(*) begin refresher_next_state <= 2'd0; @@ -4176,12 +4676,35 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_110 = dummy_s; + dummy_d_114 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_111; +reg dummy_d_115; +// synthesis translate_on +always @(*) begin + litedramcore_sequencer_start0 <= 1'd0; + case (refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_115 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_116; // synthesis translate_on always @(*) begin litedramcore_cmd_valid <= 1'd0; @@ -4208,12 +4731,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_111 = dummy_s; + dummy_d_116 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_112; +reg dummy_d_117; // synthesis translate_on always @(*) begin litedramcore_zqcs_executer_start <= 1'd0; @@ -4234,12 +4757,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_112 = dummy_s; + dummy_d_117 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_113; +reg dummy_d_118; // synthesis translate_on always @(*) begin litedramcore_cmd_last <= 1'd0; @@ -4263,30 +4786,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_113 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_114; -// synthesis translate_on -always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_114 = dummy_s; + dummy_d_118 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; @@ -4305,7 +4805,7 @@ assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == lit assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off -reg dummy_d_115; +reg dummy_d_119; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_a <= 15'd0; @@ -4315,7 +4815,7 @@ always @(*) begin litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_115 = dummy_s; + dummy_d_119 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); @@ -4323,7 +4823,7 @@ assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_ assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); // synthesis translate_off -reg dummy_d_116; +reg dummy_d_120; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_auto_precharge <= 1'd0; @@ -4333,7 +4833,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_116 = dummy_s; + dummy_d_120 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -4355,7 +4855,7 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_117; +reg dummy_d_121; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -4365,7 +4865,7 @@ always @(*) begin litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_117 = dummy_s; + dummy_d_121 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; @@ -4378,7 +4878,7 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (lite assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_118; +reg dummy_d_122; // synthesis translate_on always @(*) begin bankmachine0_next_state <= 4'd0; @@ -4441,21 +4941,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_118 = dummy_s; + dummy_d_122 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_119; +reg dummy_d_123; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine0_row_open <= 1'd0; case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end end 3'd4: begin end @@ -4468,41 +4971,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_119 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_120; +reg dummy_d_124; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + litedramcore_bankmachine0_row_close <= 1'd0; case (bankmachine0_state) 1'd1: begin + litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -4513,33 +5004,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_120 = dummy_s; + dummy_d_124 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_121; +reg dummy_d_125; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -4563,10 +5039,7 @@ always @(*) begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; - end + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -4576,23 +5049,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_121 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_122; +reg dummy_d_126; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -4609,26 +5085,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_122 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_123; +reg dummy_d_127; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -4639,29 +5115,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_123 = dummy_s; + dummy_d_127 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_124; +reg dummy_d_128; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -4675,41 +5163,33 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_124 = dummy_s; + dummy_d_128 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_125; +reg dummy_d_129; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -4723,26 +5203,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_129 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_130; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (bankmachine0_state) 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -4753,18 +5230,33 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_126 = dummy_s; + dummy_d_130 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_127; +reg dummy_d_131; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -4788,7 +5280,10 @@ always @(*) begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -4798,56 +5293,62 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_127 = dummy_s; + dummy_d_131 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_128; +reg dummy_d_132; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end end end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end endcase // synthesis translate_off - dummy_d_128 = dummy_s; + dummy_d_132 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_129; +reg dummy_d_133; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -4870,8 +5371,8 @@ always @(*) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -4882,30 +5383,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_129 = dummy_s; + dummy_d_133 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_130; +reg dummy_d_134; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -4919,21 +5416,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_130 = dummy_s; + dummy_d_134 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_131; +reg dummy_d_135; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine0_cmd_valid <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -4951,10 +5454,7 @@ always @(*) begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine0_cmd_valid <= 1'd1; end else begin end end else begin @@ -4964,7 +5464,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_131 = dummy_s; + dummy_d_135 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; @@ -4983,7 +5483,7 @@ assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == lit assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off -reg dummy_d_132; +reg dummy_d_136; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_a <= 15'd0; @@ -4993,7 +5493,7 @@ always @(*) begin litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_132 = dummy_s; + dummy_d_136 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); @@ -5001,7 +5501,7 @@ assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_ assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); // synthesis translate_off -reg dummy_d_133; +reg dummy_d_137; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_auto_precharge <= 1'd0; @@ -5011,7 +5511,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_133 = dummy_s; + dummy_d_137 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -5033,7 +5533,7 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_134; +reg dummy_d_138; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -5043,7 +5543,7 @@ always @(*) begin litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_134 = dummy_s; + dummy_d_138 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; @@ -5056,7 +5556,7 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (lite assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_135; +reg dummy_d_139; // synthesis translate_on always @(*) begin bankmachine1_next_state <= 4'd0; @@ -5119,21 +5619,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_135 = dummy_s; + dummy_d_139 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_136; +reg dummy_d_140; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine1_row_open <= 1'd0; case (bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end end 3'd4: begin end @@ -5146,41 +5649,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_136 = dummy_s; + dummy_d_140 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_137; +reg dummy_d_141; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + litedramcore_bankmachine1_row_close <= 1'd0; case (bankmachine1_state) 1'd1: begin + litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5191,33 +5682,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_137 = dummy_s; + dummy_d_141 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_138; +reg dummy_d_142; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5241,10 +5717,7 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5254,26 +5727,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_138 = dummy_s; + dummy_d_142 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_139; +reg dummy_d_143; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5287,27 +5763,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_139 = dummy_s; + dummy_d_143 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_140; +reg dummy_d_144; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (bankmachine1_state) 1'd1: begin if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -5325,7 +5798,10 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -5335,12 +5811,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_140 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_141; +reg dummy_d_145; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; @@ -5368,26 +5844,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_141 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_142; +reg dummy_d_146; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5401,26 +5881,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_142 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_143; +reg dummy_d_147; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; case (bankmachine1_state) 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5431,18 +5908,33 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_144; +reg dummy_d_148; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5466,7 +5958,10 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -5476,27 +5971,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_144 = dummy_s; + dummy_d_148 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_145; +reg dummy_d_149; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -5509,23 +5998,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_145 = dummy_s; + dummy_d_149 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_146; +reg dummy_d_150; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -5548,8 +6049,8 @@ always @(*) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; end end else begin end @@ -5560,30 +6061,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_146 = dummy_s; + dummy_d_150 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_147; +reg dummy_d_151; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5597,21 +6094,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_147 = dummy_s; + dummy_d_151 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_148; +reg dummy_d_152; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine1_cmd_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -5629,10 +6132,7 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin @@ -5642,7 +6142,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_148 = dummy_s; + dummy_d_152 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; @@ -5661,7 +6161,7 @@ assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == lit assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; // synthesis translate_off -reg dummy_d_149; +reg dummy_d_153; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_a <= 15'd0; @@ -5671,7 +6171,7 @@ always @(*) begin litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_149 = dummy_s; + dummy_d_153 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); @@ -5679,7 +6179,7 @@ assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_ assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); // synthesis translate_off -reg dummy_d_150; +reg dummy_d_154; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_auto_precharge <= 1'd0; @@ -5689,7 +6189,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_150 = dummy_s; + dummy_d_154 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -5711,7 +6211,7 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_151; +reg dummy_d_155; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -5721,7 +6221,7 @@ always @(*) begin litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_151 = dummy_s; + dummy_d_155 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; @@ -5734,7 +6234,7 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (lite assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_152; +reg dummy_d_156; // synthesis translate_on always @(*) begin bankmachine2_next_state <= 4'd0; @@ -5797,21 +6297,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_152 = dummy_s; + dummy_d_156 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_153; +reg dummy_d_157; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine2_row_open <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end end 3'd4: begin end @@ -5824,41 +6327,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_153 = dummy_s; + dummy_d_157 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_154; +reg dummy_d_158; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + litedramcore_bankmachine2_row_close <= 1'd0; case (bankmachine2_state) 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -5869,33 +6360,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_154 = dummy_s; + dummy_d_158 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_155; +reg dummy_d_159; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -5919,10 +6395,7 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; - end + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5932,26 +6405,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_155 = dummy_s; + dummy_d_159 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_156; +reg dummy_d_160; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5965,27 +6441,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_156 = dummy_s; + dummy_d_160 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_157; +reg dummy_d_161; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -6003,7 +6476,10 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -6013,15 +6489,15 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_157 = dummy_s; + dummy_d_161 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_158; +reg dummy_d_162; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6029,7 +6505,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6046,26 +6522,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_158 = dummy_s; + dummy_d_162 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_159; +reg dummy_d_163; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6079,15 +6559,15 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_159 = dummy_s; + dummy_d_163 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_160; +reg dummy_d_164; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6111,7 +6591,10 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -6121,24 +6604,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_160 = dummy_s; + dummy_d_164 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_161; +reg dummy_d_165; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -6151,30 +6631,39 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_161 = dummy_s; + dummy_d_165 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_162; +reg dummy_d_166; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -6187,23 +6676,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_162 = dummy_s; + dummy_d_166 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_163; +reg dummy_d_167; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6226,8 +6727,8 @@ always @(*) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6238,30 +6739,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_163 = dummy_s; + dummy_d_167 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_164; +reg dummy_d_168; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6275,21 +6772,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_164 = dummy_s; + dummy_d_168 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_165; +reg dummy_d_169; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine2_cmd_valid <= 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6307,10 +6810,7 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6320,7 +6820,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_165 = dummy_s; + dummy_d_169 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; @@ -6339,7 +6839,7 @@ assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == lit assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; // synthesis translate_off -reg dummy_d_166; +reg dummy_d_170; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_a <= 15'd0; @@ -6349,7 +6849,7 @@ always @(*) begin litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_166 = dummy_s; + dummy_d_170 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); @@ -6357,7 +6857,7 @@ assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_ assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); // synthesis translate_off -reg dummy_d_167; +reg dummy_d_171; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_auto_precharge <= 1'd0; @@ -6367,7 +6867,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_167 = dummy_s; + dummy_d_171 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -6389,7 +6889,7 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_168; +reg dummy_d_172; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -6399,7 +6899,7 @@ always @(*) begin litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_168 = dummy_s; + dummy_d_172 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; @@ -6412,7 +6912,7 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (lite assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_169; +reg dummy_d_173; // synthesis translate_on always @(*) begin bankmachine3_next_state <= 4'd0; @@ -6475,21 +6975,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_169 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_170; +reg dummy_d_174; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine3_row_open <= 1'd0; case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end end 3'd4: begin end @@ -6502,41 +7005,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_170 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_171; +reg dummy_d_175; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + litedramcore_bankmachine3_row_close <= 1'd0; case (bankmachine3_state) 1'd1: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -6547,42 +7038,24 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_171 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_172; +reg dummy_d_176; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -6595,24 +7068,42 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_173; +reg dummy_d_177; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -6625,44 +7116,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_177 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_178; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -6673,29 +7149,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_178 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_179; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6709,41 +7197,33 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_179 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_180; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6757,26 +7237,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_176 = dummy_s; + dummy_d_180 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_177; +reg dummy_d_181; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; case (bankmachine3_state) 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -6787,18 +7264,33 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_177 = dummy_s; + dummy_d_181 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_178; +reg dummy_d_182; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6822,7 +7314,10 @@ always @(*) begin if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -6832,27 +7327,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_178 = dummy_s; + dummy_d_182 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_179; +reg dummy_d_183; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -6865,23 +7354,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_179 = dummy_s; + dummy_d_183 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_180; +reg dummy_d_184; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6904,8 +7405,8 @@ always @(*) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -6916,30 +7417,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_180 = dummy_s; + dummy_d_184 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_181; +reg dummy_d_185; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine3_refresh_gnt <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6953,21 +7450,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_181 = dummy_s; + dummy_d_185 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_182; +reg dummy_d_186; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine3_cmd_valid <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6985,10 +7488,7 @@ always @(*) begin if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -6998,7 +7498,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_182 = dummy_s; + dummy_d_186 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; @@ -7017,7 +7517,7 @@ assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == lit assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; // synthesis translate_off -reg dummy_d_183; +reg dummy_d_187; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_a <= 15'd0; @@ -7027,7 +7527,7 @@ always @(*) begin litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_183 = dummy_s; + dummy_d_187 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); @@ -7035,7 +7535,7 @@ assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_ assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); // synthesis translate_off -reg dummy_d_184; +reg dummy_d_188; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_auto_precharge <= 1'd0; @@ -7045,7 +7545,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_184 = dummy_s; + dummy_d_188 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -7067,7 +7567,7 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_185; +reg dummy_d_189; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -7077,7 +7577,7 @@ always @(*) begin litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_185 = dummy_s; + dummy_d_189 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; @@ -7090,7 +7590,7 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (lite assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_186; +reg dummy_d_190; // synthesis translate_on always @(*) begin bankmachine4_next_state <= 4'd0; @@ -7153,21 +7653,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_186 = dummy_s; + dummy_d_190 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_187; +reg dummy_d_191; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine4_row_open <= 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin end @@ -7180,41 +7683,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_187 = dummy_s; + dummy_d_191 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_188; +reg dummy_d_192; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + litedramcore_bankmachine4_row_close <= 1'd0; case (bankmachine4_state) 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7225,33 +7716,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_188 = dummy_s; + dummy_d_192 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_189; +reg dummy_d_193; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7275,10 +7751,7 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; - end + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7288,26 +7761,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_189 = dummy_s; + dummy_d_193 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_190; +reg dummy_d_194; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7321,24 +7797,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_190 = dummy_s; + dummy_d_194 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_191; +reg dummy_d_195; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -7351,29 +7827,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_191 = dummy_s; + dummy_d_195 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_192; +reg dummy_d_196; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7387,41 +7875,33 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_192 = dummy_s; + dummy_d_196 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_193; +reg dummy_d_197; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7435,26 +7915,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_193 = dummy_s; + dummy_d_197 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_194; +reg dummy_d_198; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (bankmachine4_state) 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7465,18 +7942,33 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_194 = dummy_s; + dummy_d_198 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_195; +reg dummy_d_199; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7500,7 +7992,10 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -7510,56 +8005,62 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_195 = dummy_s; + dummy_d_199 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_196; +reg dummy_d_200; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end end end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end endcase // synthesis translate_off - dummy_d_196 = dummy_s; + dummy_d_200 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_197; +reg dummy_d_201; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -7582,8 +8083,8 @@ always @(*) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -7594,30 +8095,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_197 = dummy_s; + dummy_d_201 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_198; +reg dummy_d_202; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine4_refresh_gnt <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7631,21 +8128,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_198 = dummy_s; + dummy_d_202 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_199; +reg dummy_d_203; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine4_cmd_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -7663,10 +8166,7 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin @@ -7676,7 +8176,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_199 = dummy_s; + dummy_d_203 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; @@ -7695,7 +8195,7 @@ assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == lit assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; // synthesis translate_off -reg dummy_d_200; +reg dummy_d_204; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_a <= 15'd0; @@ -7705,7 +8205,7 @@ always @(*) begin litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_200 = dummy_s; + dummy_d_204 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); @@ -7713,7 +8213,7 @@ assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_ assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); // synthesis translate_off -reg dummy_d_201; +reg dummy_d_205; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_auto_precharge <= 1'd0; @@ -7723,7 +8223,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_201 = dummy_s; + dummy_d_205 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -7745,7 +8245,7 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_202; +reg dummy_d_206; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -7755,7 +8255,7 @@ always @(*) begin litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_202 = dummy_s; + dummy_d_206 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; @@ -7768,7 +8268,7 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (lite assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_203; +reg dummy_d_207; // synthesis translate_on always @(*) begin bankmachine5_next_state <= 4'd0; @@ -7831,21 +8331,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_203 = dummy_s; + dummy_d_207 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_204; +reg dummy_d_208; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine5_row_open <= 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end end 3'd4: begin end @@ -7858,41 +8361,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_204 = dummy_s; + dummy_d_208 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_205; +reg dummy_d_209; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + litedramcore_bankmachine5_row_close <= 1'd0; case (bankmachine5_state) 1'd1: begin + litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -7903,33 +8394,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_205 = dummy_s; + dummy_d_209 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_206; +reg dummy_d_210; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7953,10 +8429,7 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; - end + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7966,26 +8439,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_206 = dummy_s; + dummy_d_210 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_207; +reg dummy_d_211; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7999,27 +8475,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_207 = dummy_s; + dummy_d_211 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_208; +reg dummy_d_212; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; case (bankmachine5_state) 1'd1: begin if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8037,7 +8510,10 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -8047,15 +8523,15 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_208 = dummy_s; + dummy_d_212 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_209; +reg dummy_d_213; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8063,7 +8539,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8080,26 +8556,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_209 = dummy_s; + dummy_d_213 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_210; +reg dummy_d_214; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8113,26 +8593,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_210 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_211; +reg dummy_d_215; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; case (bankmachine5_state) 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -8143,18 +8620,33 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_211 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_212; +reg dummy_d_216; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8178,7 +8670,10 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -8188,27 +8683,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_212 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_213; +reg dummy_d_217; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -8221,23 +8710,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_214; +reg dummy_d_218; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -8260,8 +8761,8 @@ always @(*) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -8272,30 +8773,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_218 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_215; +reg dummy_d_219; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8309,21 +8806,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_219 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_216; +reg dummy_d_220; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine5_cmd_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -8341,10 +8844,7 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -8354,7 +8854,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_220 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; @@ -8373,7 +8873,7 @@ assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == lit assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; // synthesis translate_off -reg dummy_d_217; +reg dummy_d_221; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_a <= 15'd0; @@ -8383,7 +8883,7 @@ always @(*) begin litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_217 = dummy_s; + dummy_d_221 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); @@ -8391,7 +8891,7 @@ assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_ assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); // synthesis translate_off -reg dummy_d_218; +reg dummy_d_222; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_auto_precharge <= 1'd0; @@ -8401,7 +8901,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_218 = dummy_s; + dummy_d_222 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -8423,7 +8923,7 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_219; +reg dummy_d_223; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -8433,7 +8933,7 @@ always @(*) begin litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_219 = dummy_s; + dummy_d_223 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; @@ -8446,7 +8946,7 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (lite assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_220; +reg dummy_d_224; // synthesis translate_on always @(*) begin bankmachine6_next_state <= 4'd0; @@ -8509,21 +9009,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_220 = dummy_s; + dummy_d_224 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_221; +reg dummy_d_225; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine6_row_open <= 1'd0; case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin end @@ -8536,41 +9039,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_221 = dummy_s; + dummy_d_225 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_222; +reg dummy_d_226; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + litedramcore_bankmachine6_row_close <= 1'd0; case (bankmachine6_state) 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -8581,33 +9072,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_222 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_223; +reg dummy_d_227; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8631,10 +9107,7 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; - end + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8644,26 +9117,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_223 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_224; +reg dummy_d_228; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8677,27 +9153,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_224 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_225; +reg dummy_d_229; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (bankmachine6_state) 1'd1: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8715,7 +9188,10 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -8725,15 +9201,15 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_225 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_226; +reg dummy_d_230; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8741,7 +9217,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8758,26 +9234,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_226 = dummy_s; + dummy_d_230 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_227; +reg dummy_d_231; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (bankmachine6_state) 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8791,15 +9271,15 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_231 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_232; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8823,7 +9303,10 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -8833,27 +9316,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_232 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_233; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -8866,23 +9343,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_233 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_230; +reg dummy_d_234; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -8905,7 +9394,7 @@ always @(*) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; end else begin end end else begin @@ -8917,24 +9406,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_234 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_231; +reg dummy_d_235; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -8947,33 +9433,44 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_231 = dummy_s; + dummy_d_235 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_232; +reg dummy_d_236; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine6_refresh_gnt <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8987,21 +9484,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_232 = dummy_s; + dummy_d_236 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_233; +reg dummy_d_237; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine6_cmd_valid <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9019,10 +9522,7 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin end end else begin @@ -9032,7 +9532,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_233 = dummy_s; + dummy_d_237 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; @@ -9051,7 +9551,7 @@ assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == lit assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; // synthesis translate_off -reg dummy_d_234; +reg dummy_d_238; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_a <= 15'd0; @@ -9061,7 +9561,7 @@ always @(*) begin litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_234 = dummy_s; + dummy_d_238 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); @@ -9069,7 +9569,7 @@ assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_ assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); // synthesis translate_off -reg dummy_d_235; +reg dummy_d_239; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_auto_precharge <= 1'd0; @@ -9079,7 +9579,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_235 = dummy_s; + dummy_d_239 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -9101,7 +9601,7 @@ assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_236; +reg dummy_d_240; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -9111,7 +9611,7 @@ always @(*) begin litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_236 = dummy_s; + dummy_d_240 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; @@ -9124,7 +9624,7 @@ assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (lite assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_237; +reg dummy_d_241; // synthesis translate_on always @(*) begin bankmachine7_next_state <= 4'd0; @@ -9187,21 +9687,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_237 = dummy_s; + dummy_d_241 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_238; +reg dummy_d_242; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine7_row_open <= 1'd0; case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end end 3'd4: begin end @@ -9214,41 +9717,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_238 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_239; +reg dummy_d_243; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + litedramcore_bankmachine7_row_close <= 1'd0; case (bankmachine7_state) 1'd1: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9259,33 +9750,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_239 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_240; +reg dummy_d_244; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -9309,10 +9785,7 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; - end + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9322,23 +9795,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_240 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_241; +reg dummy_d_245; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9355,26 +9831,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_246; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9385,29 +9861,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_246 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_247; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -9421,41 +9909,33 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_247 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_248; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9469,26 +9949,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_248 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_249; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (bankmachine7_state) 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9499,18 +9976,33 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_245 = dummy_s; + dummy_d_249 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_246; +reg dummy_d_250; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -9534,7 +10026,10 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -9544,27 +10039,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_246 = dummy_s; + dummy_d_250 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_247; +reg dummy_d_251; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -9577,23 +10066,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_247 = dummy_s; + dummy_d_251 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_248; +reg dummy_d_252; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -9616,8 +10117,8 @@ always @(*) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -9628,30 +10129,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_248 = dummy_s; + dummy_d_252 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_249; +reg dummy_d_253; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9665,21 +10162,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_249 = dummy_s; + dummy_d_253 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_250; +reg dummy_d_254; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine7_cmd_valid <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9697,10 +10200,7 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -9710,7 +10210,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_250 = dummy_s; + dummy_d_254 = dummy_s; // synthesis translate_on end assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); @@ -9743,7 +10243,7 @@ assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedr assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); // synthesis translate_off -reg dummy_d_251; +reg dummy_d_255; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_valids <= 8'd0; @@ -9756,7 +10256,7 @@ always @(*) begin litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); // synthesis translate_off - dummy_d_251 = dummy_s; + dummy_d_255 = dummy_s; // synthesis translate_on end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; @@ -9768,7 +10268,7 @@ assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; // synthesis translate_off -reg dummy_d_252; +reg dummy_d_256; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; @@ -9776,12 +10276,12 @@ always @(*) begin litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; end // synthesis translate_off - dummy_d_252 = dummy_s; + dummy_d_256 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_253; +reg dummy_d_257; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; @@ -9789,12 +10289,12 @@ always @(*) begin litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; end // synthesis translate_off - dummy_d_253 = dummy_s; + dummy_d_257 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_254; +reg dummy_d_258; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_cmd_payload_we <= 1'd0; @@ -9802,12 +10302,12 @@ always @(*) begin litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; end // synthesis translate_off - dummy_d_254 = dummy_s; + dummy_d_258 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_255; +reg dummy_d_259; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_ready <= 1'd0; @@ -9818,12 +10318,12 @@ always @(*) begin litedramcore_bankmachine0_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_255 = dummy_s; + dummy_d_259 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_256; +reg dummy_d_260; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_ready <= 1'd0; @@ -9834,12 +10334,12 @@ always @(*) begin litedramcore_bankmachine1_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_256 = dummy_s; + dummy_d_260 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_257; +reg dummy_d_261; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_ready <= 1'd0; @@ -9850,12 +10350,12 @@ always @(*) begin litedramcore_bankmachine2_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_257 = dummy_s; + dummy_d_261 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_258; +reg dummy_d_262; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_ready <= 1'd0; @@ -9866,12 +10366,12 @@ always @(*) begin litedramcore_bankmachine3_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_258 = dummy_s; + dummy_d_262 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_259; +reg dummy_d_263; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_ready <= 1'd0; @@ -9882,12 +10382,12 @@ always @(*) begin litedramcore_bankmachine4_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_259 = dummy_s; + dummy_d_263 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_260; +reg dummy_d_264; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_ready <= 1'd0; @@ -9898,12 +10398,12 @@ always @(*) begin litedramcore_bankmachine5_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_260 = dummy_s; + dummy_d_264 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_261; +reg dummy_d_265; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_ready <= 1'd0; @@ -9914,12 +10414,12 @@ always @(*) begin litedramcore_bankmachine6_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_261 = dummy_s; + dummy_d_265 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_262; +reg dummy_d_266; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_ready <= 1'd0; @@ -9930,13 +10430,13 @@ always @(*) begin litedramcore_bankmachine7_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_262 = dummy_s; + dummy_d_266 = dummy_s; // synthesis translate_on end assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); // synthesis translate_off -reg dummy_d_263; +reg dummy_d_267; // synthesis translate_on always @(*) begin litedramcore_choose_req_valids <= 8'd0; @@ -9949,7 +10449,7 @@ always @(*) begin litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); // synthesis translate_off - dummy_d_263 = dummy_s; + dummy_d_267 = dummy_s; // synthesis translate_on end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; @@ -9961,7 +10461,7 @@ assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; // synthesis translate_off -reg dummy_d_264; +reg dummy_d_268; // synthesis translate_on always @(*) begin litedramcore_choose_req_cmd_payload_cas <= 1'd0; @@ -9969,12 +10469,12 @@ always @(*) begin litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; end // synthesis translate_off - dummy_d_264 = dummy_s; + dummy_d_268 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_265; +reg dummy_d_269; // synthesis translate_on always @(*) begin litedramcore_choose_req_cmd_payload_ras <= 1'd0; @@ -9982,12 +10482,12 @@ always @(*) begin litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; end // synthesis translate_off - dummy_d_265 = dummy_s; + dummy_d_269 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_266; +reg dummy_d_270; // synthesis translate_on always @(*) begin litedramcore_choose_req_cmd_payload_we <= 1'd0; @@ -9995,7 +10495,7 @@ always @(*) begin litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; end // synthesis translate_off - dummy_d_266 = dummy_s; + dummy_d_270 = dummy_s; // synthesis translate_on end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); @@ -10014,7 +10514,7 @@ assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); // synthesis translate_off -reg dummy_d_267; +reg dummy_d_271; // synthesis translate_on always @(*) begin multiplexer_next_state <= 4'd0; @@ -10073,18 +10573,22 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_267 = dummy_s; + dummy_d_271 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_268; +reg dummy_d_272; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; + litedramcore_choose_req_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel2 <= 1'd1; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end 2'd2: begin end @@ -10105,25 +10609,26 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel2 <= 2'd2; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end endcase // synthesis translate_off - dummy_d_268 = dummy_s; + dummy_d_272 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_269; +reg dummy_d_273; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; + litedramcore_en1 <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end + litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10144,27 +10649,24 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end end endcase // synthesis translate_off - dummy_d_269 = dummy_s; + dummy_d_273 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_270; +reg dummy_d_274; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; + litedramcore_steerer_sel0 <= 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 2'd2; + litedramcore_steerer_sel0 <= 1'd0; end 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10183,21 +10685,22 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; + litedramcore_steerer_sel0 <= 1'd0; end endcase // synthesis translate_off - dummy_d_270 = dummy_s; + dummy_d_274 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_271; +reg dummy_d_275; // synthesis translate_on always @(*) begin - litedramcore_en0 <= 1'd0; + litedramcore_steerer_sel1 <= 2'd0; case (multiplexer_state) 1'd1: begin + litedramcore_steerer_sel1 <= 1'd0; end 2'd2: begin end @@ -10218,24 +10721,24 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off - dummy_d_271 = dummy_s; + dummy_d_275 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_272; +reg dummy_d_276; // synthesis translate_on always @(*) begin - litedramcore_cmd_ready <= 1'd0; + litedramcore_steerer_sel2 <= 2'd0; case (multiplexer_state) 1'd1: begin + litedramcore_steerer_sel2 <= 1'd1; end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10254,23 +10757,24 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_steerer_sel2 <= 2'd2; end endcase // synthesis translate_off - dummy_d_272 = dummy_s; + dummy_d_276 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_273; +reg dummy_d_277; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; + litedramcore_choose_cmd_want_activates <= 1'd0; case (multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end 2'd2: begin @@ -10294,22 +10798,23 @@ always @(*) begin default: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end endcase // synthesis translate_off - dummy_d_273 = dummy_s; + dummy_d_277 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_274; +reg dummy_d_278; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; + litedramcore_steerer_sel3 <= 2'd0; case (multiplexer_state) 1'd1: begin + litedramcore_steerer_sel3 <= 2'd2; end 2'd2: begin end @@ -10330,22 +10835,21 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; + litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off - dummy_d_274 = dummy_s; + dummy_d_278 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_275; +reg dummy_d_279; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; + litedramcore_en0 <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10366,27 +10870,24 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off - dummy_d_275 = dummy_s; + dummy_d_279 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_276; +reg dummy_d_280; // synthesis translate_on always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; + litedramcore_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end end 2'd2: begin + litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10405,26 +10906,24 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end end endcase // synthesis translate_off - dummy_d_276 = dummy_s; + dummy_d_280 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_277; +reg dummy_d_281; // synthesis translate_on always @(*) begin - litedramcore_en1 <= 1'd0; + litedramcore_choose_cmd_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end 2'd2: begin end @@ -10445,24 +10944,26 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end endcase // synthesis translate_off - dummy_d_277 = dummy_s; + dummy_d_281 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_278; +reg dummy_d_282; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; + litedramcore_choose_req_want_reads <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; end 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10481,22 +10982,22 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel0 <= 1'd0; + litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off - dummy_d_278 = dummy_s; + dummy_d_282 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_279; +reg dummy_d_283; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; + litedramcore_choose_req_want_writes <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10517,11 +11018,10 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off - dummy_d_279 = dummy_s; + dummy_d_283 = dummy_s; // synthesis translate_on end assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; @@ -10569,7 +11069,7 @@ assign user_port_wdata_ready = new_master_wdata_ready2; assign user_port_rdata_valid = new_master_rdata_valid8; // synthesis translate_off -reg dummy_d_280; +reg dummy_d_284; // synthesis translate_on always @(*) begin litedramcore_interface_wdata <= 128'd0; @@ -10582,12 +11082,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_280 = dummy_s; + dummy_d_284 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_281; +reg dummy_d_285; // synthesis translate_on always @(*) begin litedramcore_interface_wdata_we <= 16'd0; @@ -10600,7 +11100,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_281 = dummy_s; + dummy_d_285 = dummy_s; // synthesis translate_on end assign user_port_rdata_payload_data = litedramcore_interface_rdata; @@ -10612,9 +11112,20 @@ assign roundrobin4_grant = 1'd0; assign roundrobin5_grant = 1'd0; assign roundrobin6_grant = 1'd0; assign roundrobin7_grant = 1'd0; +assign litedramcore_wishbone_adr = wb_bus_adr; +assign litedramcore_wishbone_dat_w = wb_bus_dat_w; +assign wb_bus_dat_r = litedramcore_wishbone_dat_r; +assign litedramcore_wishbone_sel = wb_bus_sel; +assign litedramcore_wishbone_cyc = wb_bus_cyc; +assign litedramcore_wishbone_stb = wb_bus_stb; +assign wb_bus_ack = litedramcore_wishbone_ack; +assign litedramcore_wishbone_we = wb_bus_we; +assign litedramcore_wishbone_cti = wb_bus_cti; +assign litedramcore_wishbone_bte = wb_bus_bte; +assign wb_bus_err = litedramcore_wishbone_err; // synthesis translate_off -reg dummy_d_282; +reg dummy_d_286; // synthesis translate_on always @(*) begin csrbank0_sel <= 1'd0; @@ -10623,7 +11134,7 @@ always @(*) begin csrbank0_sel <= 1'd0; end // synthesis translate_off - dummy_d_282 = dummy_s; + dummy_d_286 = dummy_s; // synthesis translate_on end assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; @@ -10636,7 +11147,7 @@ assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; // synthesis translate_off -reg dummy_d_283; +reg dummy_d_287; // synthesis translate_on always @(*) begin csrbank1_sel <= 1'd0; @@ -10645,7 +11156,7 @@ always @(*) begin csrbank1_sel <= 1'd0; end // synthesis translate_off - dummy_d_283 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; @@ -10683,7 +11194,7 @@ assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; // synthesis translate_off -reg dummy_d_284; +reg dummy_d_288; // synthesis translate_on always @(*) begin csrbank2_sel <= 1'd0; @@ -10692,7 +11203,7 @@ always @(*) begin csrbank2_sel <= 1'd0; end // synthesis translate_off - dummy_d_284 = dummy_s; + dummy_d_288 = dummy_s; // synthesis translate_on end assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; @@ -10795,10 +11306,10 @@ assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_stor assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we; -assign adr = csr_port_adr; -assign we = csr_port_we; -assign dat_w = csr_port_dat_w; -assign csr_port_dat_r = dat_r; +assign adr = litedramcore_adr; +assign we = litedramcore_we; +assign dat_w = litedramcore_dat_w; +assign litedramcore_dat_r = dat_r; assign interface0_bank_bus_adr = adr; assign interface1_bank_bus_adr = adr; assign interface2_bank_bus_adr = adr; @@ -10811,7 +11322,7 @@ assign interface2_bank_bus_dat_w = dat_w; assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); // synthesis translate_off -reg dummy_d_285; +reg dummy_d_289; // synthesis translate_on always @(*) begin rhs_array_muxed0 <= 1'd0; @@ -10842,12 +11353,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_285 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_286; +reg dummy_d_290; // synthesis translate_on always @(*) begin rhs_array_muxed1 <= 15'd0; @@ -10878,12 +11389,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_286 = dummy_s; + dummy_d_290 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_287; +reg dummy_d_291; // synthesis translate_on always @(*) begin rhs_array_muxed2 <= 3'd0; @@ -10914,12 +11425,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_287 = dummy_s; + dummy_d_291 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_288; +reg dummy_d_292; // synthesis translate_on always @(*) begin rhs_array_muxed3 <= 1'd0; @@ -10950,12 +11461,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_288 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_289; +reg dummy_d_293; // synthesis translate_on always @(*) begin rhs_array_muxed4 <= 1'd0; @@ -10986,12 +11497,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_289 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_290; +reg dummy_d_294; // synthesis translate_on always @(*) begin rhs_array_muxed5 <= 1'd0; @@ -11022,12 +11533,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_290 = dummy_s; + dummy_d_294 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_291; +reg dummy_d_295; // synthesis translate_on always @(*) begin t_array_muxed0 <= 1'd0; @@ -11058,12 +11569,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_291 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_292; +reg dummy_d_296; // synthesis translate_on always @(*) begin t_array_muxed1 <= 1'd0; @@ -11094,12 +11605,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_292 = dummy_s; + dummy_d_296 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_293; +reg dummy_d_297; // synthesis translate_on always @(*) begin t_array_muxed2 <= 1'd0; @@ -11130,12 +11641,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_293 = dummy_s; + dummy_d_297 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_294; +reg dummy_d_298; // synthesis translate_on always @(*) begin rhs_array_muxed6 <= 1'd0; @@ -11166,12 +11677,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_294 = dummy_s; + dummy_d_298 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_295; +reg dummy_d_299; // synthesis translate_on always @(*) begin rhs_array_muxed7 <= 15'd0; @@ -11202,12 +11713,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_295 = dummy_s; + dummy_d_299 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_296; +reg dummy_d_300; // synthesis translate_on always @(*) begin rhs_array_muxed8 <= 3'd0; @@ -11238,12 +11749,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_296 = dummy_s; + dummy_d_300 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_297; +reg dummy_d_301; // synthesis translate_on always @(*) begin rhs_array_muxed9 <= 1'd0; @@ -11274,12 +11785,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_297 = dummy_s; + dummy_d_301 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_298; +reg dummy_d_302; // synthesis translate_on always @(*) begin rhs_array_muxed10 <= 1'd0; @@ -11310,12 +11821,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_298 = dummy_s; + dummy_d_302 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_299; +reg dummy_d_303; // synthesis translate_on always @(*) begin rhs_array_muxed11 <= 1'd0; @@ -11346,12 +11857,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_299 = dummy_s; + dummy_d_303 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_300; +reg dummy_d_304; // synthesis translate_on always @(*) begin t_array_muxed3 <= 1'd0; @@ -11382,12 +11893,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_300 = dummy_s; + dummy_d_304 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_301; +reg dummy_d_305; // synthesis translate_on always @(*) begin t_array_muxed4 <= 1'd0; @@ -11418,12 +11929,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_301 = dummy_s; + dummy_d_305 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_302; +reg dummy_d_306; // synthesis translate_on always @(*) begin t_array_muxed5 <= 1'd0; @@ -11454,12 +11965,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_302 = dummy_s; + dummy_d_306 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_303; +reg dummy_d_307; // synthesis translate_on always @(*) begin rhs_array_muxed12 <= 22'd0; @@ -11469,12 +11980,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_303 = dummy_s; + dummy_d_307 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_304; +reg dummy_d_308; // synthesis translate_on always @(*) begin rhs_array_muxed13 <= 1'd0; @@ -11484,12 +11995,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_304 = dummy_s; + dummy_d_308 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_305; +reg dummy_d_309; // synthesis translate_on always @(*) begin rhs_array_muxed14 <= 1'd0; @@ -11499,12 +12010,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_305 = dummy_s; + dummy_d_309 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_306; +reg dummy_d_310; // synthesis translate_on always @(*) begin rhs_array_muxed15 <= 22'd0; @@ -11514,12 +12025,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_306 = dummy_s; + dummy_d_310 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_307; +reg dummy_d_311; // synthesis translate_on always @(*) begin rhs_array_muxed16 <= 1'd0; @@ -11529,12 +12040,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_307 = dummy_s; + dummy_d_311 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_308; +reg dummy_d_312; // synthesis translate_on always @(*) begin rhs_array_muxed17 <= 1'd0; @@ -11544,12 +12055,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_308 = dummy_s; + dummy_d_312 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_309; +reg dummy_d_313; // synthesis translate_on always @(*) begin rhs_array_muxed18 <= 22'd0; @@ -11559,12 +12070,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_309 = dummy_s; + dummy_d_313 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_310; +reg dummy_d_314; // synthesis translate_on always @(*) begin rhs_array_muxed19 <= 1'd0; @@ -11574,12 +12085,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_310 = dummy_s; + dummy_d_314 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_311; +reg dummy_d_315; // synthesis translate_on always @(*) begin rhs_array_muxed20 <= 1'd0; @@ -11589,12 +12100,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_311 = dummy_s; + dummy_d_315 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_312; +reg dummy_d_316; // synthesis translate_on always @(*) begin rhs_array_muxed21 <= 22'd0; @@ -11604,12 +12115,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_312 = dummy_s; + dummy_d_316 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_313; +reg dummy_d_317; // synthesis translate_on always @(*) begin rhs_array_muxed22 <= 1'd0; @@ -11619,12 +12130,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_313 = dummy_s; + dummy_d_317 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_314; +reg dummy_d_318; // synthesis translate_on always @(*) begin rhs_array_muxed23 <= 1'd0; @@ -11634,12 +12145,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_314 = dummy_s; + dummy_d_318 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_315; +reg dummy_d_319; // synthesis translate_on always @(*) begin rhs_array_muxed24 <= 22'd0; @@ -11649,12 +12160,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_315 = dummy_s; + dummy_d_319 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_316; +reg dummy_d_320; // synthesis translate_on always @(*) begin rhs_array_muxed25 <= 1'd0; @@ -11664,12 +12175,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_316 = dummy_s; + dummy_d_320 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_317; +reg dummy_d_321; // synthesis translate_on always @(*) begin rhs_array_muxed26 <= 1'd0; @@ -11679,12 +12190,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_317 = dummy_s; + dummy_d_321 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_318; +reg dummy_d_322; // synthesis translate_on always @(*) begin rhs_array_muxed27 <= 22'd0; @@ -11694,12 +12205,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_318 = dummy_s; + dummy_d_322 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_319; +reg dummy_d_323; // synthesis translate_on always @(*) begin rhs_array_muxed28 <= 1'd0; @@ -11709,12 +12220,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_319 = dummy_s; + dummy_d_323 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_320; +reg dummy_d_324; // synthesis translate_on always @(*) begin rhs_array_muxed29 <= 1'd0; @@ -11724,12 +12235,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_320 = dummy_s; + dummy_d_324 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_321; +reg dummy_d_325; // synthesis translate_on always @(*) begin rhs_array_muxed30 <= 22'd0; @@ -11739,12 +12250,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_321 = dummy_s; + dummy_d_325 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_322; +reg dummy_d_326; // synthesis translate_on always @(*) begin rhs_array_muxed31 <= 1'd0; @@ -11754,12 +12265,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_322 = dummy_s; + dummy_d_326 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_323; +reg dummy_d_327; // synthesis translate_on always @(*) begin rhs_array_muxed32 <= 1'd0; @@ -11769,12 +12280,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_323 = dummy_s; + dummy_d_327 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_324; +reg dummy_d_328; // synthesis translate_on always @(*) begin rhs_array_muxed33 <= 22'd0; @@ -11784,12 +12295,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_324 = dummy_s; + dummy_d_328 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_325; +reg dummy_d_329; // synthesis translate_on always @(*) begin rhs_array_muxed34 <= 1'd0; @@ -11799,12 +12310,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_325 = dummy_s; + dummy_d_329 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_326; +reg dummy_d_330; // synthesis translate_on always @(*) begin rhs_array_muxed35 <= 1'd0; @@ -11814,12 +12325,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_326 = dummy_s; + dummy_d_330 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_327; +reg dummy_d_331; // synthesis translate_on always @(*) begin array_muxed0 <= 3'd0; @@ -11838,12 +12349,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_327 = dummy_s; + dummy_d_331 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_328; +reg dummy_d_332; // synthesis translate_on always @(*) begin array_muxed1 <= 15'd0; @@ -11862,12 +12373,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_328 = dummy_s; + dummy_d_332 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_329; +reg dummy_d_333; // synthesis translate_on always @(*) begin array_muxed2 <= 1'd0; @@ -11886,12 +12397,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_329 = dummy_s; + dummy_d_333 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_330; +reg dummy_d_334; // synthesis translate_on always @(*) begin array_muxed3 <= 1'd0; @@ -11910,12 +12421,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_330 = dummy_s; + dummy_d_334 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_331; +reg dummy_d_335; // synthesis translate_on always @(*) begin array_muxed4 <= 1'd0; @@ -11934,12 +12445,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_331 = dummy_s; + dummy_d_335 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_332; +reg dummy_d_336; // synthesis translate_on always @(*) begin array_muxed5 <= 1'd0; @@ -11958,12 +12469,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_332 = dummy_s; + dummy_d_336 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_333; +reg dummy_d_337; // synthesis translate_on always @(*) begin array_muxed6 <= 1'd0; @@ -11982,12 +12493,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_333 = dummy_s; + dummy_d_337 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_334; +reg dummy_d_338; // synthesis translate_on always @(*) begin array_muxed7 <= 3'd0; @@ -12006,12 +12517,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_334 = dummy_s; + dummy_d_338 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_335; +reg dummy_d_339; // synthesis translate_on always @(*) begin array_muxed8 <= 15'd0; @@ -12030,12 +12541,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_335 = dummy_s; + dummy_d_339 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_336; +reg dummy_d_340; // synthesis translate_on always @(*) begin array_muxed9 <= 1'd0; @@ -12054,12 +12565,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_336 = dummy_s; + dummy_d_340 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_337; +reg dummy_d_341; // synthesis translate_on always @(*) begin array_muxed10 <= 1'd0; @@ -12078,12 +12589,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_341 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_338; +reg dummy_d_342; // synthesis translate_on always @(*) begin array_muxed11 <= 1'd0; @@ -12102,12 +12613,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_342 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_343; // synthesis translate_on always @(*) begin array_muxed12 <= 1'd0; @@ -12126,12 +12637,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_343 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_344; // synthesis translate_on always @(*) begin array_muxed13 <= 1'd0; @@ -12150,12 +12661,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_344 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_345; // synthesis translate_on always @(*) begin array_muxed14 <= 3'd0; @@ -12174,12 +12685,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_345 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_346; // synthesis translate_on always @(*) begin array_muxed15 <= 15'd0; @@ -12198,12 +12709,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_346 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_347; // synthesis translate_on always @(*) begin array_muxed16 <= 1'd0; @@ -12222,12 +12733,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_347 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_344; +reg dummy_d_348; // synthesis translate_on always @(*) begin array_muxed17 <= 1'd0; @@ -12246,12 +12757,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_348 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_345; +reg dummy_d_349; // synthesis translate_on always @(*) begin array_muxed18 <= 1'd0; @@ -12270,12 +12781,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_349 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_350; // synthesis translate_on always @(*) begin array_muxed19 <= 1'd0; @@ -12294,12 +12805,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_350 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_351; // synthesis translate_on always @(*) begin array_muxed20 <= 1'd0; @@ -12318,12 +12829,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_351 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_352; // synthesis translate_on always @(*) begin array_muxed21 <= 3'd0; @@ -12342,12 +12853,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_352 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_353; // synthesis translate_on always @(*) begin array_muxed22 <= 15'd0; @@ -12366,12 +12877,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_353 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_354; // synthesis translate_on always @(*) begin array_muxed23 <= 1'd0; @@ -12390,12 +12901,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_354 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_355; // synthesis translate_on always @(*) begin array_muxed24 <= 1'd0; @@ -12414,12 +12925,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_355 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_356; // synthesis translate_on always @(*) begin array_muxed25 <= 1'd0; @@ -12438,12 +12949,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_356 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_357; // synthesis translate_on always @(*) begin array_muxed26 <= 1'd0; @@ -12462,12 +12973,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_357 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_358; // synthesis translate_on always @(*) begin array_muxed27 <= 1'd0; @@ -12486,7 +12997,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_358 = dummy_s; // synthesis translate_on end assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset); @@ -12507,6 +13018,7 @@ always @(posedge iodelay_clk) begin end always @(posedge sys_clk) begin + state <= next_state; a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1); a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1); a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en; @@ -12522,112 +13034,112 @@ always @(posedge sys_clk) begin if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip0_value <= 1'd0; end - a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[15:8]}; + a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip1_value <= 1'd0; end - a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[15:8]}; + a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip2_value <= 1'd0; end - a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[15:8]}; + a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip3_value <= 1'd0; end - a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[15:8]}; + a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip4_value <= 1'd0; end - a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[15:8]}; + a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip5_value <= 1'd0; end - a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[15:8]}; + a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip6_value <= 1'd0; end - a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[15:8]}; + a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip7_value <= 1'd0; end - a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[15:8]}; + a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip8_value <= 1'd0; end - a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[15:8]}; + a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip9_value <= 1'd0; end - a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[15:8]}; + a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip10_value <= 1'd0; end - a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[15:8]}; + a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip11_value <= 1'd0; end - a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[15:8]}; + a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip12_value <= 1'd0; end - a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[15:8]}; + a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip13_value <= 1'd0; end - a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[15:8]}; + a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip14_value <= 1'd0; end - a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[15:8]}; + a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip15_value <= 1'd0; end - a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[15:8]}; + a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[23:8]}; if (litedramcore_inti_p0_rddata_valid) begin litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata; end @@ -14161,22 +14673,22 @@ always @(posedge sys_clk) begin a7ddrphy_dqs_oe_delayed <= 1'd0; a7ddrphy_dqspattern_o1 <= 8'd0; a7ddrphy_dq_oe_delayed <= 1'd0; - a7ddrphy_bitslip0_value <= 3'd0; - a7ddrphy_bitslip1_value <= 3'd0; - a7ddrphy_bitslip2_value <= 3'd0; - a7ddrphy_bitslip3_value <= 3'd0; - a7ddrphy_bitslip4_value <= 3'd0; - a7ddrphy_bitslip5_value <= 3'd0; - a7ddrphy_bitslip6_value <= 3'd0; - a7ddrphy_bitslip7_value <= 3'd0; - a7ddrphy_bitslip8_value <= 3'd0; - a7ddrphy_bitslip9_value <= 3'd0; - a7ddrphy_bitslip10_value <= 3'd0; - a7ddrphy_bitslip11_value <= 3'd0; - a7ddrphy_bitslip12_value <= 3'd0; - a7ddrphy_bitslip13_value <= 3'd0; - a7ddrphy_bitslip14_value <= 3'd0; - a7ddrphy_bitslip15_value <= 3'd0; + a7ddrphy_bitslip0_value <= 4'd0; + a7ddrphy_bitslip1_value <= 4'd0; + a7ddrphy_bitslip2_value <= 4'd0; + a7ddrphy_bitslip3_value <= 4'd0; + a7ddrphy_bitslip4_value <= 4'd0; + a7ddrphy_bitslip5_value <= 4'd0; + a7ddrphy_bitslip6_value <= 4'd0; + a7ddrphy_bitslip7_value <= 4'd0; + a7ddrphy_bitslip8_value <= 4'd0; + a7ddrphy_bitslip9_value <= 4'd0; + a7ddrphy_bitslip10_value <= 4'd0; + a7ddrphy_bitslip11_value <= 4'd0; + a7ddrphy_bitslip12_value <= 4'd0; + a7ddrphy_bitslip13_value <= 4'd0; + a7ddrphy_bitslip14_value <= 4'd0; + a7ddrphy_bitslip15_value <= 4'd0; a7ddrphy_rddata_en_last <= 8'd0; a7ddrphy_wrdata_en_last <= 4'd0; litedramcore_storage <= 4'd0; @@ -14358,6 +14870,7 @@ always @(posedge sys_clk) begin init_done_re <= 1'd0; init_error_storage <= 1'd0; init_error_re <= 1'd0; + state <= 1'd0; refresher_state <= 2'd0; bankmachine0_state <= 4'd0; bankmachine1_state <= 4'd0; diff --git a/soc.vhdl b/soc.vhdl index a8ae3c9..212314b 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -17,7 +17,7 @@ use work.wishbone_types.all; -- 0xc0000000: SYSCON -- 0xc0002000: UART0 -- 0xc0004000: XICS ICP --- 0xc0100000: DRAM CSRs +-- 0xc0100000: LiteDRAM control (CSRs) -- 0xf0000000: Block RAM (aliased & repeated) -- 0xffff0000: DRAM init code (if any) @@ -39,7 +39,7 @@ entity soc is -- DRAM controller signals wb_dram_in : out wishbone_master_out; wb_dram_out : in wishbone_slave_out; - wb_dram_csr : out std_ulogic; + wb_dram_ctrl : out std_ulogic; wb_dram_init : out std_ulogic; -- UART0 signals: @@ -162,7 +162,7 @@ begin SLAVE_BRAM, SLAVE_DRAM, SLAVE_DRAM_INIT, - SLAVE_DRAM_CSR, + SLAVE_DRAM_CTRL, SLAVE_ICP_0, SLAVE_NONE); variable slave : slave_type; @@ -185,7 +185,7 @@ begin elsif std_match(wb_master_out.adr, x"C0002---") then slave := SLAVE_UART; elsif std_match(wb_master_out.adr, x"C01-----") then - slave := SLAVE_DRAM_CSR; + slave := SLAVE_DRAM_CTRL; elsif std_match(wb_master_out.adr, x"C0004---") then slave := SLAVE_ICP_0; end if; @@ -204,7 +204,7 @@ begin wb_dram_in <= wb_master_out; wb_dram_in.cyc <= '0'; - wb_dram_csr <= '0'; + wb_dram_ctrl <= '0'; wb_dram_init <= '0'; wb_syscon_in <= wb_master_out; wb_syscon_in.cyc <= '0'; @@ -219,10 +219,10 @@ begin wb_dram_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_dram_out; wb_dram_init <= '1'; - when SLAVE_DRAM_CSR => + when SLAVE_DRAM_CTRL => wb_dram_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_dram_out; - wb_dram_csr <= '1'; + wb_dram_ctrl <= '1'; when SLAVE_SYSCON => wb_syscon_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_syscon_out; From c0f537b8455731cf1db23fb488afd0d9c5df19e6 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 15 May 2020 10:14:53 +1000 Subject: [PATCH 05/10] litedram: Remove init delays The clocks / resets are now stable Signed-off-by: Benjamin Herrenschmidt --- litedram/gen-src/sdram_init/main.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index b40c4df..fd43970 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -37,17 +37,10 @@ void flush_cpu_icache(void) void main(void) { unsigned long long ftr, val; - int i; /* Init the UART */ potato_uart_init(); - /* - * Let things settle ... not sure why but the UART is - * not happy otherwise. The PLL might need to settle ? - */ - for (i = 0; i < 10000; i++) - readb(UART_BASE + POTATO_CONSOLE_STATUS); printf("\n\nWelcome to Microwatt !\n\n"); /* TODO: Add core version information somewhere in syscon, possibly From 30fd9aa298056def2eb08d6fb66702cb05f2f421 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 15 May 2020 13:11:58 +1000 Subject: [PATCH 06/10] litedram: Forward system reset signal The wrapper wouldn't forward it. Make it do so Signed-off-by: Benjamin Herrenschmidt --- litedram/gen-src/wrapper-mw-init.vhdl | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/litedram/gen-src/wrapper-mw-init.vhdl b/litedram/gen-src/wrapper-mw-init.vhdl index f13edeb..c4d702e 100644 --- a/litedram/gen-src/wrapper-mw-init.vhdl +++ b/litedram/gen-src/wrapper-mw-init.vhdl @@ -119,8 +119,6 @@ architecture behaviour of litedram_wrapper is signal ad3 : std_ulogic; - signal dram_user_reset : std_ulogic; - signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0); @@ -234,7 +232,6 @@ begin -- Reset ignored, the reset controller use the pll lock signal, -- and alternate core reset address set when DRAM is not initialized. -- - system_reset <= '0'; core_alt_reset <= not init_done; -- State machine @@ -242,7 +239,7 @@ begin begin if rising_edge(system_clk) then - if dram_user_reset = '1' then + if system_reset = '1' then state <= CMD; else case state is @@ -286,7 +283,7 @@ begin init_done => init_done, init_error => init_error, user_clk => system_clk, - user_rst => dram_user_reset, + user_rst => system_reset, wb_ctrl_adr => wb_ctrl_adr, wb_ctrl_dat_w => wb_ctrl_dat_w, wb_ctrl_dat_r => wb_ctrl_dat_r, From 3b603402d2f454ad3084956e50d9430d7b373ed1 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 15 May 2020 13:15:48 +1000 Subject: [PATCH 07/10] soc_reset: Use counters, add synchronizers In some cases we need to keep the reset held for much longer, so use counters rather than shift registers. Additionally, some signals such as ext_rst and pll_locked or signals going from the ext_clk domain to the pll_clk domain need to be treated as async, and testing them without synchronizers is asking for trouble. Finally, make the external reset also reset the PLL. Signed-off-by: Benjamin Herrenschmidt --- fpga/soc_reset.vhdl | 45 +++++++++++++++++++++++------------ fpga/soc_reset_tb.vhdl | 54 ++++++++++++++++++++++++++++++------------ 2 files changed, 69 insertions(+), 30 deletions(-) diff --git a/fpga/soc_reset.vhdl b/fpga/soc_reset.vhdl index 2685dab..e1db2fb 100644 --- a/fpga/soc_reset.vhdl +++ b/fpga/soc_reset.vhdl @@ -1,10 +1,11 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.numeric_std.all; entity soc_reset is generic ( - PLL_RESET_CLOCKS : integer := 32; - SOC_RESET_CLOCKS : integer := 32; + PLL_RESET_BITS : integer := 5; + SOC_RESET_BITS : integer := 5; RESET_LOW : boolean := true ); port ( @@ -20,26 +21,38 @@ entity soc_reset is end soc_reset; architecture rtl of soc_reset is - signal ext_rst_n : std_ulogic; - signal rst_n : std_ulogic; - signal pll_rst_reg : std_ulogic_vector(PLL_RESET_CLOCKS downto 0) := (others => '1'); - signal soc_rst_reg : std_ulogic_vector(SOC_RESET_CLOCKS downto 0) := (others => '1'); + signal ext_rst0_n : std_ulogic; + signal ext_rst1_n : std_ulogic := '0'; + signal ext_rst2_n : std_ulogic := '0'; + signal rst0_n : std_ulogic; + signal rst1_n : std_ulogic := '0'; + signal rst2_n : std_ulogic := '0'; + signal pll_rst_cnt : std_ulogic_vector(PLL_RESET_BITS downto 0) := (others => '0'); + signal soc_rst_cnt : std_ulogic_vector(SOC_RESET_BITS downto 0) := (others => '0'); begin - ext_rst_n <= ext_rst_in when RESET_LOW else not ext_rst_in; - rst_n <= ext_rst_n and pll_locked_in; + ext_rst0_n <= ext_rst_in when RESET_LOW else not ext_rst_in; + rst0_n <= ext_rst0_n and pll_locked_in and not pll_rst_out; -- PLL reset is active high - pll_rst_out <= pll_rst_reg(0); + pll_rst_out <= not pll_rst_cnt(pll_rst_cnt'left); -- Pass active high reset around - rst_out <= soc_rst_reg(0); + rst_out <= not soc_rst_cnt(soc_rst_cnt'left); -- Wait for external clock to become stable before starting the PLL -- By the time the FPGA has been loaded the clock should be well and -- truly stable, but lets give it a few cycles to be sure. + -- + -- [BenH] Some designs seem to require a lot more.. pll_reset_0 : process(ext_clk) begin if (rising_edge(ext_clk)) then - pll_rst_reg <= '0' & pll_rst_reg(pll_rst_reg'length-1 downto 1); + ext_rst1_n <= ext_rst0_n; + ext_rst2_n <= ext_rst1_n; + if (ext_rst2_n = '0') then + pll_rst_cnt <= (others => '0'); + elsif (pll_rst_cnt(pll_rst_cnt'left) = '0') then + pll_rst_cnt <= std_ulogic_vector(unsigned(pll_rst_cnt) + 1); + end if; end if; end process; @@ -49,10 +62,12 @@ begin soc_reset_0 : process(pll_clk) begin if (rising_edge(pll_clk)) then - if (rst_n = '0') then - soc_rst_reg <= (others => '1'); - else - soc_rst_reg <= '0' & soc_rst_reg(soc_rst_reg'length-1 downto 1); + rst1_n <= rst0_n; + rst2_n <= rst1_n; + if (rst2_n = '0') then + soc_rst_cnt <= (others => '0'); + elsif (soc_rst_cnt(soc_rst_cnt'left) = '0') then + soc_rst_cnt <= std_ulogic_vector(unsigned(soc_rst_cnt) + 1); end if; end if; end process; diff --git a/fpga/soc_reset_tb.vhdl b/fpga/soc_reset_tb.vhdl index ee8fc17..26c6b1e 100644 --- a/fpga/soc_reset_tb.vhdl +++ b/fpga/soc_reset_tb.vhdl @@ -12,16 +12,14 @@ architecture behave of soc_reset_tb is signal ext_rst_in : std_ulogic; signal pll_rst_out : std_ulogic; - signal pll_rst_out_expected : std_ulogic; signal rst_out : std_ulogic; - signal rst_out_expected : std_ulogic; constant clk_period : time := 10 ns; type test_vector is record pll_locked_in : std_ulogic; ext_rst_in : std_ulogic; - pll_rst_out : std_ulogic; + pll_rst_out : std_ulogic; rst_out : std_ulogic; end record; @@ -32,6 +30,8 @@ architecture behave of soc_reset_tb is ('0', '1', '1', '1'), ('0', '1', '1', '1'), ('0', '1', '1', '1'), + ('0', '1', '1', '1'), + ('0', '1', '1', '1'), -- Reset is removed from the PLL ('0', '1', '0', '1'), ('0', '1', '0', '1'), @@ -41,15 +41,27 @@ architecture behave of soc_reset_tb is ('1', '1', '0', '1'), ('1', '1', '0', '1'), ('1', '1', '0', '1'), + ('1', '1', '0', '1'), + ('1', '1', '0', '1'), -- Finally SOC comes out of reset ('1', '1', '0', '0'), ('1', '1', '0', '0'), -- PLL locked, reset button pressed - ('1', '0', '0', '1'), - ('1', '0', '0', '1'), - ('1', '0', '0', '1'), + ('1', '0', '0', '0'), + ('1', '0', '0', '0'), + ('1', '0', '0', '0'), + ('1', '0', '1', '1'), -- PLL locked, reset button released + ('1', '1', '1', '1'), + ('1', '1', '1', '1'), + ('1', '1', '1', '1'), + ('1', '1', '1', '1'), + ('1', '1', '1', '1'), + ('1', '1', '1', '1'), + ('1', '1', '0', '1'), + ('1', '1', '0', '1'), + ('1', '1', '0', '1'), ('1', '1', '0', '1'), ('1', '1', '0', '1'), ('1', '1', '0', '1'), @@ -59,8 +71,8 @@ architecture behave of soc_reset_tb is begin soc_reset_0: entity work.soc_reset generic map ( - PLL_RESET_CLOCKS => 4, - SOC_RESET_CLOCKS => 4, + PLL_RESET_BITS => 2, + SOC_RESET_BITS => 2, RESET_LOW => true ) port map ( @@ -83,17 +95,29 @@ begin end process clock; stim: process + variable tv : test_vector; begin + -- skew us a bit + wait for clk_period/4; + for i in test_vectors'range loop - (pll_locked_in, ext_rst_in, pll_rst_out_expected, rst_out_expected) <= test_vectors(i); + tv := test_vectors(i); + + pll_locked_in <= tv.pll_locked_in; + ext_rst_in <= tv.ext_rst_in; - --report "pll_locked_in " & std_ulogic'image(pll_locked_in); - --report "ext_rst_in " & std_ulogic'image(ext_rst_in); - --report "pll_rst_out " & std_ulogic'image(pll_rst_out); - --report "rst_out" & std_ulogic'image(rst_out); + report " ** STEP " & integer'image(i); + report "pll_locked_in " & std_ulogic'image(pll_locked_in); + report "ext_rst_in " & std_ulogic'image(ext_rst_in); + report "pll_rst_out " & std_ulogic'image(pll_rst_out); + report "rst_out" & std_ulogic'image(rst_out); - assert pll_rst_out_expected = pll_rst_out report "pll_rst_out bad"; - assert rst_out_expected = rst_out report "rst_out bad"; + assert tv.pll_rst_out = pll_rst_out report + "pll_rst_out bad exp=" & std_ulogic'image(tv.pll_rst_out) & + " got=" & std_ulogic'image(pll_rst_out); + assert tv.rst_out = rst_out report + "rst_out bad exp=" & std_ulogic'image(tv.rst_out) & + " got=" & std_ulogic'image(rst_out); wait for clk_period; end loop; From 7560e8f2ff38ddca5b8da96a6c13c788927be46c Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 15 May 2020 13:20:27 +1000 Subject: [PATCH 08/10] arty/nexys: Rework reset with litedram When using litedram, request a much longer PLL reset. This seems to help get rid of all the grabled output after config. Also use the clean system_rst out of litedram as our source of reset for the rest of the SoC (it is synchronized with system_clk and takes pll_locked into account already) --- fpga/top-arty.vhdl | 14 +++++++------- fpga/top-nexys-video.vhdl | 14 +++++++------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index 9150f82..f2da6c2 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -158,8 +158,7 @@ begin has_dram: if USE_LITEDRAM generate signal dram_init_done : std_ulogic; signal dram_init_error : std_ulogic; - signal soc_rst_0 : std_ulogic; - signal soc_rst_1 : std_ulogic; + signal dram_sys_rst : std_ulogic; begin -- Eventually dig out the frequency from the generator @@ -168,15 +167,17 @@ begin reset_controller: entity work.soc_reset generic map( - RESET_LOW => RESET_LOW + RESET_LOW => RESET_LOW, + PLL_RESET_BITS => 18, + SOC_RESET_BITS => 1 ) port map( ext_clk => ext_clk, pll_clk => system_clk, - pll_locked_in => system_clk_locked, + pll_locked_in => '1', ext_rst_in => ext_rst, pll_rst_out => pll_rst, - rst_out => soc_rst_0 + rst_out => open ); dram: entity work.litedram_wrapper @@ -188,7 +189,7 @@ begin clk_in => ext_clk, rst => pll_rst, system_clk => system_clk, - system_reset => soc_rst_1, + system_reset => soc_rst, core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, @@ -223,7 +224,6 @@ begin led0_b_pwm <= not dram_init_done; led0_r_pwm <= dram_init_error; led0_g_pwm <= dram_init_done and not dram_init_error; - soc_rst <= soc_rst_0 or soc_rst_1; end generate; diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index 7cabfa6..0e4b097 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -140,8 +140,7 @@ begin has_dram: if USE_LITEDRAM generate signal dram_init_done : std_ulogic; signal dram_init_error : std_ulogic; - signal soc_rst_0 : std_ulogic; - signal soc_rst_1 : std_ulogic; + signal dram_sys_rst : std_ulogic; begin -- Eventually dig out the frequency from the generator @@ -150,15 +149,17 @@ begin reset_controller: entity work.soc_reset generic map( - RESET_LOW => RESET_LOW + RESET_LOW => RESET_LOW, + PLL_RESET_BITS => 18, + SOC_RESET_BITS => 1 ) port map( ext_clk => ext_clk, pll_clk => system_clk, - pll_locked_in => system_clk_locked, + pll_locked_in => '1', ext_rst_in => ext_rst, pll_rst_out => pll_rst, - rst_out => soc_rst_0 + rst_out => open ); dram: entity work.litedram_wrapper @@ -170,7 +171,7 @@ begin clk_in => ext_clk, rst => pll_rst, system_clk => system_clk, - system_reset => soc_rst_1, + system_reset => soc_rst, pll_locked => system_clk_locked, wb_in => wb_dram_in, @@ -203,7 +204,6 @@ begin led0 <= dram_init_done and not dram_init_error; led1 <= dram_init_error; -- Make it blink ? - soc_rst <= soc_rst_0 or soc_rst_1; end generate; end architecture behaviour; From acbdd396a5fedbe160bcb1271b37e941f3eaa45c Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 15 May 2020 13:30:01 +1000 Subject: [PATCH 09/10] soc/core: Add reset latches This adds one-cycle latches to the various resets out of the soc and into the various core modules. It *seems* to help vivado P&R a bit and has shown to avoid timing violations under some circumstances. Interestingly those resets never seem to appear in the bad timing path. It looks like those long resets simply impose placement constraints that Vivado satisfies at the expense of timing elsewhere. Signed-off-by: Benjamin Herrenschmidt --- core.vhdl | 52 +++++++++++++++++++++++++++++++++++++++------------- soc.vhdl | 43 +++++++++++++++++++++++++++++++++++-------- 2 files changed, 74 insertions(+), 21 deletions(-) diff --git a/core.vhdl b/core.vhdl index 9895dc8..0664c73 100644 --- a/core.vhdl +++ b/core.vhdl @@ -91,7 +91,19 @@ architecture behave of core is signal complete: std_ulogic; signal terminate: std_ulogic; signal core_rst: std_ulogic; - signal icache_rst: std_ulogic; + signal icache_inv: std_ulogic; + + -- Delayed/Latched resets and alt_reset + signal rst_fetch1 : std_ulogic := '1'; + signal rst_fetch2 : std_ulogic := '1'; + signal rst_icache : std_ulogic := '1'; + signal rst_dcache : std_ulogic := '1'; + signal rst_dec1 : std_ulogic := '1'; + signal rst_dec2 : std_ulogic := '1'; + signal rst_ex1 : std_ulogic := '1'; + signal rst_ls1 : std_ulogic := '1'; + signal rst_dbg : std_ulogic := '1'; + signal alt_reset_d : std_ulogic; signal sim_cr_dump: std_ulogic; @@ -128,6 +140,22 @@ begin core_rst <= dbg_core_rst or rst; + resets: process(clk) + begin + if rising_edge(clk) then + rst_fetch1 <= core_rst; + rst_fetch2 <= core_rst; + rst_icache <= core_rst or dbg_icache_rst or ex1_icache_inval; + rst_dcache <= core_rst; + rst_dec1 <= core_rst; + rst_dec2 <= core_rst; + rst_ex1 <= core_rst; + rst_ls1 <= core_rst; + rst_dbg <= rst; + alt_reset_d <= alt_reset; + end if; + end process; + fetch1_0: entity work.fetch1 generic map ( RESET_ADDRESS => (others => '0'), @@ -135,8 +163,8 @@ begin ) port map ( clk => clk, - rst => core_rst, - alt_reset_in => alt_reset, + rst => rst_fetch1, + alt_reset_in => alt_reset_d, stall_in => fetch1_stall_in, flush_in => flush, stop_in => dbg_core_stop, @@ -155,7 +183,7 @@ begin ) port map( clk => clk, - rst => icache_rst, + rst => rst_icache, i_in => fetch1_to_icache, i_out => icache_to_fetch2, flush_in => flush, @@ -164,12 +192,10 @@ begin wishbone_in => wishbone_insn_in ); - icache_rst <= rst or dbg_icache_rst or ex1_icache_inval; - fetch2_0: entity work.fetch2 port map ( clk => clk, - rst => core_rst, + rst => rst_fetch2, stall_in => fetch2_stall_in, flush_in => flush, i_in => icache_to_fetch2, @@ -181,7 +207,7 @@ begin decode1_0: entity work.decode1 port map ( clk => clk, - rst => core_rst, + rst => rst_dec1, stall_in => decode1_stall_in, flush_in => flush, f_in => fetch2_to_decode1, @@ -196,7 +222,7 @@ begin ) port map ( clk => clk, - rst => core_rst, + rst => rst_dec2, stall_in => decode2_stall_in, stall_out => decode2_stall_out, flush_in => flush, @@ -242,7 +268,7 @@ begin ) port map ( clk => clk, - rst => core_rst, + rst => rst_ex1, flush_out => flush, stall_out => ex1_stall_out, e_in => decode2_to_execute1, @@ -257,7 +283,7 @@ begin loadstore1_0: entity work.loadstore1 port map ( clk => clk, - rst => core_rst, + rst => rst_ls1, l_in => execute1_to_loadstore1, l_out => loadstore1_to_writeback, d_out => loadstore1_to_dcache, @@ -274,7 +300,7 @@ begin ) port map ( clk => clk, - rst => core_rst, + rst => rst_dcache, d_in => loadstore1_to_dcache, d_out => dcache_to_loadstore1, stall_out => dcache_stall_out, @@ -295,7 +321,7 @@ begin debug_0: entity work.core_debug port map ( clk => clk, - rst => rst, + rst => rst_dbg, dmi_addr => dmi_addr, dmi_din => dmi_din, dmi_dout => dmi_dout, diff --git a/soc.vhdl b/soc.vhdl index 212314b..e9e9470 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -109,8 +109,33 @@ architecture behaviour of soc is signal dmi_core_dout : std_ulogic_vector(63 downto 0); signal dmi_core_req : std_ulogic; signal dmi_core_ack : std_ulogic; + + -- Delayed/latched resets and alt_reset + signal rst_core : std_ulogic := '1'; + signal rst_uart : std_ulogic := '1'; + signal rst_xics : std_ulogic := '1'; + signal rst_bram : std_ulogic := '1'; + signal rst_dtm : std_ulogic := '1'; + signal rst_wbar : std_ulogic := '1'; + signal rst_wbdb : std_ulogic := '1'; + signal alt_reset_d : std_ulogic; + begin + resets: process(system_clk) + begin + if rising_edge(system_clk) then + rst_core <= rst or core_reset; + rst_uart <= rst; + rst_xics <= rst; + rst_bram <= rst; + rst_dtm <= rst; + rst_wbar <= rst; + rst_wbdb <= rst; + alt_reset_d <= alt_reset; + end if; + end process; + -- Processor core processor: entity work.core generic map( @@ -120,8 +145,8 @@ begin ) port map( clk => system_clk, - rst => rst or core_reset, - alt_reset => alt_reset, + rst => rst_core, + alt_reset => alt_reset_d, wishbone_insn_in => wishbone_icore_in, wishbone_insn_out => wishbone_icore_out, wishbone_data_in => wishbone_dcore_in, @@ -147,7 +172,8 @@ begin NUM_MASTERS => NUM_WB_MASTERS ) port map( - clk => system_clk, rst => rst, + clk => system_clk, + rst => rst_wbar, wb_masters_in => wb_masters_out, wb_masters_out => wb_masters_in, wb_slave_out => wb_master_out, @@ -271,7 +297,7 @@ begin ) port map( clk => system_clk, - reset => rst, + reset => rst_uart, txd => uart0_txd, rxd => uart0_rxd, irq => int_level_in(0), @@ -292,7 +318,7 @@ begin ) port map( clk => system_clk, - rst => rst, + rst => rst_xics, wb_in => wb_xics0_in, wb_out => wb_xics0_out, int_level_in => int_level_in, @@ -307,7 +333,7 @@ begin ) port map( clk => system_clk, - rst => rst, + rst => rst_bram, wishbone_in => wb_bram_in, wishbone_out => wb_bram_out ); @@ -320,7 +346,7 @@ begin ) port map( sys_clk => system_clk, - sys_reset => rst, + sys_reset => rst_dtm, dmi_addr => dmi_addr, dmi_din => dmi_din, dmi_dout => dmi_dout, @@ -378,7 +404,8 @@ begin -- Wishbone debug master (TODO: Add a DMI address decoder) wishbone_debug: entity work.wishbone_debug_master - port map(clk => system_clk, rst => rst, + port map(clk => system_clk, + rst => rst_wbdb, dmi_addr => dmi_addr(1 downto 0), dmi_dout => dmi_wb_dout, dmi_din => dmi_dout, From 6efb31c924862622ccaab53236218e2196c8f51f Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 15 May 2020 13:31:11 +1000 Subject: [PATCH 10/10] litedram: Regenerate Signed-off-by: Benjamin Herrenschmidt --- litedram/generated/arty/litedram-wrapper.vhdl | 4 +- litedram/generated/arty/litedram_core.init | 166 +++++++++--------- litedram/generated/arty/litedram_core.v | 2 +- .../nexys-video/litedram-wrapper.vhdl | 4 +- .../generated/nexys-video/litedram_core.init | 166 +++++++++--------- .../generated/nexys-video/litedram_core.v | 2 +- 6 files changed, 170 insertions(+), 174 deletions(-) diff --git a/litedram/generated/arty/litedram-wrapper.vhdl b/litedram/generated/arty/litedram-wrapper.vhdl index fd9f3bd..c4d702e 100644 --- a/litedram/generated/arty/litedram-wrapper.vhdl +++ b/litedram/generated/arty/litedram-wrapper.vhdl @@ -229,7 +229,9 @@ begin -- We don't do pipelining yet. wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - -- Use alternate core reset address set when DRAM is not initialized. + -- Reset ignored, the reset controller use the pll lock signal, + -- and alternate core reset address set when DRAM is not initialized. + -- core_alt_reset <= not init_done; -- State machine diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 508f707..b1a75f8 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -519,11 +519,11 @@ f8c101a838800140 38c101987c651b78 7fe3fb78f8e101b0 f92101c0f90101b8 -4800163df94101c8 +4800161df94101c8 7c7e1b7860000000 -480011c17fe3fb78 +480011a17fe3fb78 3821017060000000 -48001bfc7fc3f378 +48001bdc7fc3f378 0100000000000000 4e80002000000280 0000000000000000 @@ -531,51 +531,47 @@ f92101c0f90101b8 7c0802a638429e74 7d908026fbe1fff8 f801001091810008 -480010cdf821ff91 -3940271060000000 -7d4903a63d20c000 -7929002061292010 -7d404eaa7c0004ac -3c62ffff4200fff8 -4bffff2d38637d80 +480010adf821ff91 +3c62ffff60000000 +4bffff4d38637d60 548400023880ffff 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637da0 -3c62ffff4bffff09 -38637dc07bff0020 -7c0004ac4bfffef9 +63ff000838637d80 +3c62ffff4bffff29 +38637da07bff0020 +7c0004ac4bffff19 73e900017fe0feea 3c62ffff41820010 -4bfffedd38637dd8 +4bfffefd38637db8 4e00000073e90002 3c62ffff41820010 -4bfffec538637de0 -3bff7fc83fe2ffff -4bfffeb57fe3fb78 +4bfffee538637dc0 +3bff7fa83fe2ffff +4bfffed57fe3fb78 608400103c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637de87884b282 -419200284bfffe91 +38637dc87884b282 +419200284bfffeb1 608400183c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637e0878846502 -3d20c0004bfffe69 +38637de878846502 +3d20c0004bfffe89 7929002061290020 7d204eea7c0004ac 3c62ffff3c80000f -38637e2860844240 -4bfffe3d7c892392 -4bfffe357fe3fb78 +38637e0860844240 +4bfffe5d7c892392 +4bfffe557fe3fb78 3ca2ffff41920028 3c62ffff3c82ffff -38847e5838a57e48 -4bfffe1538637e60 +38847e3838a57e28 +4bfffe3538637e40 6000000048000dd5 -38637e903c62ffff -382100704bfffe01 +38637e703c62ffff +382100704bfffe21 7d90812081810008 0000000048001a54 0000018003000000 @@ -635,11 +631,11 @@ f801001091810008 9864000099240001 000000004e800020 0000000000000000 -38429b183c4c0001 +38429b383c4c0001 480017ed7c0802a6 7c7e1b78f821ff21 -38637f603c62ffff -600000004bfffc01 +38637f403c62ffff +600000004bfffc21 390100603ca08020 3940000460a50003 7d1d43783920002a @@ -690,7 +686,7 @@ f801001091810008 793500203ee2ffff 7d2907b47ed607b4 3b0100703be00000 -7f3db2143af77f88 +7f3db2143af77f68 7f5d4a147ebdaa14 3860000f4bfffd75 4bfffca93b800000 @@ -731,8 +727,8 @@ f801001091810008 4bffffcc3b400000 7fbfe2142f9f0020 409e006c7fbd0e70 -38637f703c62ffff -600000004bfff919 +38637f503c62ffff +600000004bfff939 3be000007fc3f378 7f9fe8004bfffb8d 3d40c010419c0070 @@ -746,42 +742,42 @@ f801001091810008 480014e4382100e0 3c62ffff7cbfe050 7ca501947ca50e70 -38637f787fa4eb78 -4bfff89d7ca507b4 +38637f587fa4eb78 +4bfff8bd7ca507b4 4bffff8460000000 3bff00017fc3f378 7fff07b44bfffb59 000000004bffff7c 00000b8001000000 -384297683c4c0001 +384297883c4c0001 3d40c0107c0802a6 3920000e614a0800 f8010010794a0020 7c0004acf821ffa1 600000007d20572a -4bfff83d38628038 +4bfff85d38628018 3821006060000000 7c0803a6e8010010 000000004e800020 0000008001000000 -384297103c4c0001 +384297303c4c0001 3d40c0107c0802a6 39200001614a0800 f8010010794a0020 7c0004acf821ffa1 3c62ffff7d20572a -4bfff7e538637fa8 +4bfff80538637f88 3821006060000000 7c0803a6e8010010 000000004e800020 0000008001000000 -384296b83c4c0001 +384296d83c4c0001 390000807c0802a6 3d40aaaa7d0903a6 614aaaaa3d204000 f821ff8148001399 3929000491490000 -4bfff8014200fff8 +4bfff8214200fff8 3940008060000000 7d4903a63d00aaaa 3be000003d204000 @@ -793,7 +789,7 @@ f821ff8148001399 3d2040007d0903a6 91490000614a5555 4200fff839290004 -600000004bfff7a5 +600000004bfff7c5 3d00555539400080 3d2040007d4903a6 8149000061085555 @@ -802,8 +798,8 @@ f821ff8148001399 4200ffe839290004 419e001c2fbf0000 38a001003c62ffff -38637ea87fe4fb78 -600000004bfff6e1 +38637e887fe4fb78 +600000004bfff701 3ce080203d000008 60e700037d0903a6 392000013d404000 @@ -811,7 +807,7 @@ f821ff8148001399 7d2900d0792907e0 7d293838394a0004 912afffc7d294278 -4bfff7114200ffe4 +4bfff7314200ffe4 3d00000860000000 7d0903a63ce08020 3d40400060e70003 @@ -825,13 +821,13 @@ f821ff8148001399 2fbd00004200ffd4 3c62ffff419e001c 7fa4eb783ca00008 -4bfff62d38637ed0 +4bfff64d38637eb0 3920200060000000 7d2903a639400000 794800203d2a1000 394a000139290002 9109000079291764 -4bfff6714200ffe8 +4bfff6914200ffe8 3920200060000000 7d2903a639400000 3d2a10003bc00000 @@ -842,12 +838,12 @@ f821ff8148001399 2fbe00004200ffdc 3c62ffff419e001c 7fc4f37838a02000 -4bfff5a538637ef8 +4bfff5c538637ed8 7fffea1460000000 7ffff21438600000 409e00a82f9f0000 -38637f203c62ffff -600000004bfff581 +38637f003c62ffff +600000004bfff5a1 3d4000087c9602a6 7d4903a678840020 3d49100039200000 @@ -855,7 +851,7 @@ f821ff8148001399 910a000039290001 7ff602a64200ffec 3fe064007c9f2050 -4bfff5b17fff2396 +4bfff5d17fff2396 7bff002060000000 3d0000087d3602a6 7d0903a679290020 @@ -864,12 +860,12 @@ f821ff8148001399 7d2548507cb602a6 7ca54b963ca06400 7fe4fb783c62ffff -78a5006038637f30 -600000004bfff4f1 +78a5006038637f10 +600000004bfff511 3821008038600001 0000000048001128 0000038001000000 -384293c83c4c0001 +384293e83c4c0001 480010817c0802a6 3fe0c010f821fec1 63ff00283bc00001 @@ -885,16 +881,16 @@ f821ff8148001399 7c0004ac7d20ff2a 7c0004ac7fc0e72a 3c62ffff7fa0ff2a -38637fe83b810070 -4bfff4453e02ffff +38637fc83b810070 +4bfff4653e02ffff 3d22ffff60000000 -60000000fb810080 -6000000039297ff8 +3de2fffffb810080 +3dc2ffff39297fd8 3ae100633e42ffff 3ac10061f9210098 -3a107f883be00000 -39c2801039e28008 -392100643a527fc8 +3a107f683be00000 +39ce7ff039ef7fe8 +392100643a527fa8 3e80c0103b200001 f92100883ea0c010 7f39f83039210068 @@ -957,7 +953,7 @@ e88100884bfff63d 7f604f2a7c0004ac 7fa5eb78e8610098 3b4000207fe4fb78 -4bfff20d3b600000 +4bfff22d3b600000 7fe3fb7860000000 4bfff5194bfff485 3a2000013860000f @@ -971,25 +967,25 @@ e94100a04bfff581 409e00907f883800 2baa0010394a0004 7e248b78409effc0 -4bfff19d7de37b78 +4bfff1bd7de37b78 3b5affff60000000 4bfff45d7fe3fb78 7f7b8a147b5a0021 4082ff807f7b07b4 -4bfff1757dc37378 +4bfff1957dc37378 3920000060000000 7d20a72a7c0004ac 7d20af2a7c0004ac 4bfff3753860000b 4bfff3a93860000f 4bfff52d7fe3fb78 -4bfff13d7e439378 +4bfff15d7e439378 7f98d80060000000 7f1bc378419cfd70 3a2000004bfffd6c -600000004bffff70 +3c62ffff4bffff70 7fe4fb787fc5f378 -4bfff10d38628018 +4bfff12d38637ff8 3d20c01060000000 7929002061290028 7f204f2a7c0004ac @@ -1004,7 +1000,7 @@ e94100a04bfff581 4200003438e00000 3af7ffff7fe3fb78 7e4393784bfff489 -4bfff0953b9cffff +4bfff0b53b9cffff 2f9f000160000000 419e00283ad6ffff 4bfffc783be00001 @@ -1015,12 +1011,12 @@ e94100a04bfff581 48000c6038600001 0100000000000000 3c4c000100001280 -7c0802a638428f3c -38637fd03c62ffff +7c0802a638428f5c +38637fb03c62ffff f821ff7148000c1d 3be000003f60c010 7b7b0020637b1000 -600000004bfff019 +600000004bfff039 7fe0df2a7c0004ac 635a10083f40c010 7c0004ac7b5a0020 @@ -1068,28 +1064,28 @@ f821ff7148000c1d 386000017f80df2a 000000004bffffec 0000068001000000 -38428d903c4c0001 +38428db03c4c0001 600000003d20c000 7929002061292000 -3d20c000f92280b0 +3d20c000f9228090 7929002061290020 7d204eea7c0004ac 614a20003d40001c -e94280b07d295392 +e94280907d295392 3929ffff394a0018 7d2057ea7c0004ac 000000004e800020 0000000000000000 -38428d303c4c0001 -e92280b060000000 +38428d503c4c0001 +e922809060000000 7c0004ac39290010 712900087d204eea 5469063e4082ffe8 -7c0004ace94280b0 +7c0004ace9428090 4e8000207d2057ea 0000000000000000 3c4c000100000000 -7c0802a638428cec +7c0802a638428d0c fbe1fff8fbc1fff0 f80100103bc3ffff 8ffe0001f821ffd1 @@ -1149,7 +1145,7 @@ e8e400007c691a14 7c6307b43863ffe0 000000004e800020 0000000000000000 -38428b083c4c0001 +38428b283c4c0001 3d2037367c0802a6 612935347d908026 65293332792907c6 @@ -1183,7 +1179,7 @@ fbfd00007fe9fa14 4bfffff07d29f392 0300000000000000 3c4c000100000580 -7c0802a6384289fc +7c0802a638428a1c f821ffb1480006e9 7c7f1b78eb630000 7cbd2b787c9c2378 @@ -1199,7 +1195,7 @@ f821ffb1480006e9 4bffffb8f93f0000 0100000000000000 3c4c000100000580 -7c0802a63842897c +7c0802a63842899c f821ffa148000661 7c9b23787c7d1b78 388000007ca32b78 @@ -1230,7 +1226,7 @@ e95d00009b270000 f95d0000394a0001 000000004bffffa8 0000078001000000 -384288803c4c0001 +384288a03c4c0001 480005397c0802a6 7c741b79f821fed1 38600000f8610060 @@ -1239,7 +1235,7 @@ f95d0000394a0001 3ac4ffff60000000 f92100703b410020 3ae0000060000000 -3a428060392280a8 +3a42804039228088 f92100783ba10060 ebc1006089250000 419e00102fa90000 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 991adbd..9208d87 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 09:40:26 +// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 13:30:46 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, diff --git a/litedram/generated/nexys-video/litedram-wrapper.vhdl b/litedram/generated/nexys-video/litedram-wrapper.vhdl index fd9f3bd..c4d702e 100644 --- a/litedram/generated/nexys-video/litedram-wrapper.vhdl +++ b/litedram/generated/nexys-video/litedram-wrapper.vhdl @@ -229,7 +229,9 @@ begin -- We don't do pipelining yet. wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - -- Use alternate core reset address set when DRAM is not initialized. + -- Reset ignored, the reset controller use the pll lock signal, + -- and alternate core reset address set when DRAM is not initialized. + -- core_alt_reset <= not init_done; -- State machine diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index 508f707..b1a75f8 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -519,11 +519,11 @@ f8c101a838800140 38c101987c651b78 7fe3fb78f8e101b0 f92101c0f90101b8 -4800163df94101c8 +4800161df94101c8 7c7e1b7860000000 -480011c17fe3fb78 +480011a17fe3fb78 3821017060000000 -48001bfc7fc3f378 +48001bdc7fc3f378 0100000000000000 4e80002000000280 0000000000000000 @@ -531,51 +531,47 @@ f92101c0f90101b8 7c0802a638429e74 7d908026fbe1fff8 f801001091810008 -480010cdf821ff91 -3940271060000000 -7d4903a63d20c000 -7929002061292010 -7d404eaa7c0004ac -3c62ffff4200fff8 -4bffff2d38637d80 +480010adf821ff91 +3c62ffff60000000 +4bffff4d38637d60 548400023880ffff 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637da0 -3c62ffff4bffff09 -38637dc07bff0020 -7c0004ac4bfffef9 +63ff000838637d80 +3c62ffff4bffff29 +38637da07bff0020 +7c0004ac4bffff19 73e900017fe0feea 3c62ffff41820010 -4bfffedd38637dd8 +4bfffefd38637db8 4e00000073e90002 3c62ffff41820010 -4bfffec538637de0 -3bff7fc83fe2ffff -4bfffeb57fe3fb78 +4bfffee538637dc0 +3bff7fa83fe2ffff +4bfffed57fe3fb78 608400103c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637de87884b282 -419200284bfffe91 +38637dc87884b282 +419200284bfffeb1 608400183c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637e0878846502 -3d20c0004bfffe69 +38637de878846502 +3d20c0004bfffe89 7929002061290020 7d204eea7c0004ac 3c62ffff3c80000f -38637e2860844240 -4bfffe3d7c892392 -4bfffe357fe3fb78 +38637e0860844240 +4bfffe5d7c892392 +4bfffe557fe3fb78 3ca2ffff41920028 3c62ffff3c82ffff -38847e5838a57e48 -4bfffe1538637e60 +38847e3838a57e28 +4bfffe3538637e40 6000000048000dd5 -38637e903c62ffff -382100704bfffe01 +38637e703c62ffff +382100704bfffe21 7d90812081810008 0000000048001a54 0000018003000000 @@ -635,11 +631,11 @@ f801001091810008 9864000099240001 000000004e800020 0000000000000000 -38429b183c4c0001 +38429b383c4c0001 480017ed7c0802a6 7c7e1b78f821ff21 -38637f603c62ffff -600000004bfffc01 +38637f403c62ffff +600000004bfffc21 390100603ca08020 3940000460a50003 7d1d43783920002a @@ -690,7 +686,7 @@ f801001091810008 793500203ee2ffff 7d2907b47ed607b4 3b0100703be00000 -7f3db2143af77f88 +7f3db2143af77f68 7f5d4a147ebdaa14 3860000f4bfffd75 4bfffca93b800000 @@ -731,8 +727,8 @@ f801001091810008 4bffffcc3b400000 7fbfe2142f9f0020 409e006c7fbd0e70 -38637f703c62ffff -600000004bfff919 +38637f503c62ffff +600000004bfff939 3be000007fc3f378 7f9fe8004bfffb8d 3d40c010419c0070 @@ -746,42 +742,42 @@ f801001091810008 480014e4382100e0 3c62ffff7cbfe050 7ca501947ca50e70 -38637f787fa4eb78 -4bfff89d7ca507b4 +38637f587fa4eb78 +4bfff8bd7ca507b4 4bffff8460000000 3bff00017fc3f378 7fff07b44bfffb59 000000004bffff7c 00000b8001000000 -384297683c4c0001 +384297883c4c0001 3d40c0107c0802a6 3920000e614a0800 f8010010794a0020 7c0004acf821ffa1 600000007d20572a -4bfff83d38628038 +4bfff85d38628018 3821006060000000 7c0803a6e8010010 000000004e800020 0000008001000000 -384297103c4c0001 +384297303c4c0001 3d40c0107c0802a6 39200001614a0800 f8010010794a0020 7c0004acf821ffa1 3c62ffff7d20572a -4bfff7e538637fa8 +4bfff80538637f88 3821006060000000 7c0803a6e8010010 000000004e800020 0000008001000000 -384296b83c4c0001 +384296d83c4c0001 390000807c0802a6 3d40aaaa7d0903a6 614aaaaa3d204000 f821ff8148001399 3929000491490000 -4bfff8014200fff8 +4bfff8214200fff8 3940008060000000 7d4903a63d00aaaa 3be000003d204000 @@ -793,7 +789,7 @@ f821ff8148001399 3d2040007d0903a6 91490000614a5555 4200fff839290004 -600000004bfff7a5 +600000004bfff7c5 3d00555539400080 3d2040007d4903a6 8149000061085555 @@ -802,8 +798,8 @@ f821ff8148001399 4200ffe839290004 419e001c2fbf0000 38a001003c62ffff -38637ea87fe4fb78 -600000004bfff6e1 +38637e887fe4fb78 +600000004bfff701 3ce080203d000008 60e700037d0903a6 392000013d404000 @@ -811,7 +807,7 @@ f821ff8148001399 7d2900d0792907e0 7d293838394a0004 912afffc7d294278 -4bfff7114200ffe4 +4bfff7314200ffe4 3d00000860000000 7d0903a63ce08020 3d40400060e70003 @@ -825,13 +821,13 @@ f821ff8148001399 2fbd00004200ffd4 3c62ffff419e001c 7fa4eb783ca00008 -4bfff62d38637ed0 +4bfff64d38637eb0 3920200060000000 7d2903a639400000 794800203d2a1000 394a000139290002 9109000079291764 -4bfff6714200ffe8 +4bfff6914200ffe8 3920200060000000 7d2903a639400000 3d2a10003bc00000 @@ -842,12 +838,12 @@ f821ff8148001399 2fbe00004200ffdc 3c62ffff419e001c 7fc4f37838a02000 -4bfff5a538637ef8 +4bfff5c538637ed8 7fffea1460000000 7ffff21438600000 409e00a82f9f0000 -38637f203c62ffff -600000004bfff581 +38637f003c62ffff +600000004bfff5a1 3d4000087c9602a6 7d4903a678840020 3d49100039200000 @@ -855,7 +851,7 @@ f821ff8148001399 910a000039290001 7ff602a64200ffec 3fe064007c9f2050 -4bfff5b17fff2396 +4bfff5d17fff2396 7bff002060000000 3d0000087d3602a6 7d0903a679290020 @@ -864,12 +860,12 @@ f821ff8148001399 7d2548507cb602a6 7ca54b963ca06400 7fe4fb783c62ffff -78a5006038637f30 -600000004bfff4f1 +78a5006038637f10 +600000004bfff511 3821008038600001 0000000048001128 0000038001000000 -384293c83c4c0001 +384293e83c4c0001 480010817c0802a6 3fe0c010f821fec1 63ff00283bc00001 @@ -885,16 +881,16 @@ f821ff8148001399 7c0004ac7d20ff2a 7c0004ac7fc0e72a 3c62ffff7fa0ff2a -38637fe83b810070 -4bfff4453e02ffff +38637fc83b810070 +4bfff4653e02ffff 3d22ffff60000000 -60000000fb810080 -6000000039297ff8 +3de2fffffb810080 +3dc2ffff39297fd8 3ae100633e42ffff 3ac10061f9210098 -3a107f883be00000 -39c2801039e28008 -392100643a527fc8 +3a107f683be00000 +39ce7ff039ef7fe8 +392100643a527fa8 3e80c0103b200001 f92100883ea0c010 7f39f83039210068 @@ -957,7 +953,7 @@ e88100884bfff63d 7f604f2a7c0004ac 7fa5eb78e8610098 3b4000207fe4fb78 -4bfff20d3b600000 +4bfff22d3b600000 7fe3fb7860000000 4bfff5194bfff485 3a2000013860000f @@ -971,25 +967,25 @@ e94100a04bfff581 409e00907f883800 2baa0010394a0004 7e248b78409effc0 -4bfff19d7de37b78 +4bfff1bd7de37b78 3b5affff60000000 4bfff45d7fe3fb78 7f7b8a147b5a0021 4082ff807f7b07b4 -4bfff1757dc37378 +4bfff1957dc37378 3920000060000000 7d20a72a7c0004ac 7d20af2a7c0004ac 4bfff3753860000b 4bfff3a93860000f 4bfff52d7fe3fb78 -4bfff13d7e439378 +4bfff15d7e439378 7f98d80060000000 7f1bc378419cfd70 3a2000004bfffd6c -600000004bffff70 +3c62ffff4bffff70 7fe4fb787fc5f378 -4bfff10d38628018 +4bfff12d38637ff8 3d20c01060000000 7929002061290028 7f204f2a7c0004ac @@ -1004,7 +1000,7 @@ e94100a04bfff581 4200003438e00000 3af7ffff7fe3fb78 7e4393784bfff489 -4bfff0953b9cffff +4bfff0b53b9cffff 2f9f000160000000 419e00283ad6ffff 4bfffc783be00001 @@ -1015,12 +1011,12 @@ e94100a04bfff581 48000c6038600001 0100000000000000 3c4c000100001280 -7c0802a638428f3c -38637fd03c62ffff +7c0802a638428f5c +38637fb03c62ffff f821ff7148000c1d 3be000003f60c010 7b7b0020637b1000 -600000004bfff019 +600000004bfff039 7fe0df2a7c0004ac 635a10083f40c010 7c0004ac7b5a0020 @@ -1068,28 +1064,28 @@ f821ff7148000c1d 386000017f80df2a 000000004bffffec 0000068001000000 -38428d903c4c0001 +38428db03c4c0001 600000003d20c000 7929002061292000 -3d20c000f92280b0 +3d20c000f9228090 7929002061290020 7d204eea7c0004ac 614a20003d40001c -e94280b07d295392 +e94280907d295392 3929ffff394a0018 7d2057ea7c0004ac 000000004e800020 0000000000000000 -38428d303c4c0001 -e92280b060000000 +38428d503c4c0001 +e922809060000000 7c0004ac39290010 712900087d204eea 5469063e4082ffe8 -7c0004ace94280b0 +7c0004ace9428090 4e8000207d2057ea 0000000000000000 3c4c000100000000 -7c0802a638428cec +7c0802a638428d0c fbe1fff8fbc1fff0 f80100103bc3ffff 8ffe0001f821ffd1 @@ -1149,7 +1145,7 @@ e8e400007c691a14 7c6307b43863ffe0 000000004e800020 0000000000000000 -38428b083c4c0001 +38428b283c4c0001 3d2037367c0802a6 612935347d908026 65293332792907c6 @@ -1183,7 +1179,7 @@ fbfd00007fe9fa14 4bfffff07d29f392 0300000000000000 3c4c000100000580 -7c0802a6384289fc +7c0802a638428a1c f821ffb1480006e9 7c7f1b78eb630000 7cbd2b787c9c2378 @@ -1199,7 +1195,7 @@ f821ffb1480006e9 4bffffb8f93f0000 0100000000000000 3c4c000100000580 -7c0802a63842897c +7c0802a63842899c f821ffa148000661 7c9b23787c7d1b78 388000007ca32b78 @@ -1230,7 +1226,7 @@ e95d00009b270000 f95d0000394a0001 000000004bffffa8 0000078001000000 -384288803c4c0001 +384288a03c4c0001 480005397c0802a6 7c741b79f821fed1 38600000f8610060 @@ -1239,7 +1235,7 @@ f95d0000394a0001 3ac4ffff60000000 f92100703b410020 3ae0000060000000 -3a428060392280a8 +3a42804039228088 f92100783ba10060 ebc1006089250000 419e00102fa90000 diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index 57ecfd7..dd29267 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 09:40:28 +// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 13:30:49 //-------------------------------------------------------------------------------- module litedram_core( input wire clk,