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@ -22,15 +22,25 @@ use work.wishbone_types.all;
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-- 0xc0002000: UART0
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-- 0xc0004000: XICS ICP
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-- 0xc0006000: SPI Flash controller
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-- 0xc0100000: LiteDRAM control (CSRs)
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-- 0xc8nnnnnn: External IO bus
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-- 0xf0000000: Flash "ROM" mapping
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-- 0xff000000: DRAM init code (if any) or flash ROM
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-- 0xff000000: DRAM init code (if any) or flash ROM (**)
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-- External IO bus:
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-- 0xc8000000: LiteDRAM control (CSRs)
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-- (**) DRAM init code is currently special and goes to the external
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-- IO bus, this will be fixed when it's moved out of litedram and
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-- into the main SoC once we have a common "firmware".
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-- Interrupt numbers:
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--
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-- 0 : UART0
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entity soc is
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generic (
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MEMORY_SIZE : natural;
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RAM_INIT_FILE : string;
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RESET_LOW : boolean;
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CLK_FREQ : positive;
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SIM : boolean;
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DISABLE_FLATTEN_CORE : boolean := false;
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@ -47,27 +57,29 @@ entity soc is
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rst : in std_ulogic;
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system_clk : in std_ulogic;
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-- DRAM controller signals
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-- "Large" (64-bit) DRAM wishbone
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wb_dram_in : out wishbone_master_out;
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wb_dram_out : in wishbone_slave_out;
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wb_dram_ctrl_in : out wb_io_master_out;
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wb_dram_ctrl_out : in wb_io_slave_out;
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wb_dram_is_csr : out std_ulogic;
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wb_dram_is_init : out std_ulogic;
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wb_dram_out : in wishbone_slave_out := wishbone_slave_out_init;
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-- "Small" (32-bit) external IO wishbone
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wb_ext_io_in : out wb_io_master_out;
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wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init;
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wb_ext_is_dram_csr : out std_ulogic;
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wb_ext_is_dram_init : out std_ulogic;
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-- UART0 signals:
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uart0_txd : out std_ulogic;
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uart0_rxd : in std_ulogic;
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uart0_rxd : in std_ulogic := '0';
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-- SPI Flash signals
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spi_flash_sck : out std_ulogic;
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spi_flash_cs_n : out std_ulogic;
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spi_flash_sdat_o : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
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spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
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spi_flash_sdat_i : in std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
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spi_flash_sdat_i : in std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
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-- DRAM controller signals
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alt_reset : in std_ulogic
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alt_reset : in std_ulogic := '0'
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);
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end entity soc;
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@ -108,7 +120,8 @@ architecture behaviour of soc is
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-- UART0 signals:
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signal wb_uart0_in : wb_io_master_out;
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signal wb_uart0_out : wb_io_slave_out;
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signal uart_dat8 : std_ulogic_vector(7 downto 0);
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signal uart0_dat8 : std_ulogic_vector(7 downto 0);
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signal uart0_irq : std_ulogic;
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-- SPI Flash controller signals:
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signal wb_spiflash_in : wb_io_master_out;
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@ -154,15 +167,14 @@ architecture behaviour of soc is
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signal rst_wbdb : std_ulogic := '1';
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signal alt_reset_d : std_ulogic;
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-- IO branch split:
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type slave_io_type is (SLAVE_IO_SYSCON,
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SLAVE_IO_UART,
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SLAVE_IO_DRAM_INIT,
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SLAVE_IO_DRAM_CSR,
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SLAVE_IO_ICP_0,
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SLAVE_IO_SPI_FLASH_REG,
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SLAVE_IO_SPI_FLASH_MAP,
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SLAVE_IO_NONE);
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-- IO branch split:
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type slave_io_type is (SLAVE_IO_SYSCON,
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SLAVE_IO_UART,
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SLAVE_IO_ICP_0,
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SLAVE_IO_SPI_FLASH_REG,
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SLAVE_IO_SPI_FLASH_MAP,
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SLAVE_IO_EXTERNAL,
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SLAVE_IO_NONE);
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signal slave_io_dbg : slave_io_type;
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begin
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@ -268,8 +280,14 @@ begin
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wb_bram_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_bram_out;
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when SLAVE_TOP_DRAM =>
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wb_dram_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_dram_out;
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if HAS_DRAM then
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wb_dram_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_dram_out;
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else
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wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
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wb_master_in.dat <= (others => '1');
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wb_master_in.stall <= '0';
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end if;
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when SLAVE_TOP_IO =>
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wb_io_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_io_out;
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@ -421,25 +439,26 @@ begin
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-- IO wishbone slave intercon.
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--
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slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out,
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wb_dram_ctrl_out, wb_xics0_out, wb_spiflash_out)
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wb_ext_io_out, wb_xics0_out, wb_spiflash_out)
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variable slave_io : slave_io_type;
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variable match : std_ulogic_vector(31 downto 12);
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variable ext_valid : boolean;
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begin
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-- Simple address decoder.
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slave_io := SLAVE_IO_NONE;
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match := "11" & wb_sio_out.adr(29 downto 12);
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if std_match(match, x"FF---") and HAS_DRAM then
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slave_io := SLAVE_IO_DRAM_INIT;
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slave_io := SLAVE_IO_EXTERNAL;
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elsif std_match(match, x"F----") then
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slave_io := SLAVE_IO_SPI_FLASH_MAP;
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elsif std_match(match, x"C0000") then
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slave_io := SLAVE_IO_SYSCON;
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elsif std_match(match, x"C0002") then
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slave_io := SLAVE_IO_UART;
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elsif std_match(match, x"C01--") then
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slave_io := SLAVE_IO_DRAM_CSR;
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elsif std_match(match, x"C8---") then
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slave_io := SLAVE_IO_EXTERNAL;
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elsif std_match(match, x"C0004") then
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slave_io := SLAVE_IO_ICP_0;
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elsif std_match(match, x"C0006") then
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@ -459,23 +478,41 @@ begin
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wb_xics0_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
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wb_xics0_in.cyc <= '0';
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wb_dram_ctrl_in <= wb_sio_out;
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wb_dram_ctrl_in.cyc <= '0';
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wb_dram_is_csr <= '0';
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wb_dram_is_init <= '0';
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wb_ext_io_in <= wb_sio_out;
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wb_ext_io_in.cyc <= '0';
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wb_syscon_in <= wb_sio_out;
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wb_syscon_in.cyc <= '0';
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wb_ext_is_dram_csr <= '0';
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wb_ext_is_dram_init <= '0';
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-- Default response, ack & return all 1's
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wb_sio_in.dat <= (others => '1');
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wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
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wb_sio_in.stall <= '0';
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case slave_io is
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when SLAVE_IO_DRAM_INIT =>
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wb_dram_ctrl_in.cyc <= wb_sio_out.cyc;
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wb_sio_in <= wb_dram_ctrl_out;
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wb_dram_is_init <= '1';
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when SLAVE_IO_DRAM_CSR =>
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wb_dram_ctrl_in.cyc <= wb_sio_out.cyc;
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wb_sio_in <= wb_dram_ctrl_out;
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wb_dram_is_csr <= '1';
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when SLAVE_IO_EXTERNAL =>
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-- Ext IO "chip selects"
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--
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-- DRAM init is special at 0xFF* so we just test the top
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-- bit. Everything else is at 0xC8* so we test only bits
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-- 23 downto 16.
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--
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ext_valid := false;
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if wb_sio_out.adr(29) = '1' and HAS_DRAM then -- DRAM init is special
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wb_ext_is_dram_init <= '1';
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ext_valid := true;
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elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
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wb_ext_is_dram_csr <= '1';
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ext_valid := true;
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end if;
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if ext_valid then
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wb_ext_io_in.cyc <= wb_sio_out.cyc;
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wb_sio_in <= wb_ext_io_out;
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end if;
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when SLAVE_IO_SYSCON =>
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wb_syscon_in.cyc <= wb_sio_out.cyc;
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wb_sio_in <= wb_syscon_out;
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@ -497,9 +534,6 @@ begin
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wb_sio_in <= wb_spiflash_out;
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wb_spiflash_is_reg <= '1';
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when others =>
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wb_sio_in.dat <= (others => '1');
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wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
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wb_sio_in.stall <= '0';
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end case;
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end process;
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@ -538,16 +572,16 @@ begin
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reset => rst_uart,
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txd => uart0_txd,
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rxd => uart0_rxd,
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irq => int_level_in(0),
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irq => uart0_irq,
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wb_adr_in => wb_uart0_in.adr(11 downto 0),
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wb_dat_in => wb_uart0_in.dat(7 downto 0),
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wb_dat_out => uart_dat8,
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wb_dat_out => uart0_dat8,
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wb_cyc_in => wb_uart0_in.cyc,
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wb_stb_in => wb_uart0_in.stb,
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wb_we_in => wb_uart0_in.we,
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wb_ack_out => wb_uart0_out.ack
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);
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wb_uart0_out.dat <= x"000000" & uart_dat8;
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wb_uart0_out.dat <= x"000000" & uart0_dat8;
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wb_uart0_out.stall <= not wb_uart0_out.ack;
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spiflash_gen: if HAS_SPI_FLASH generate
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@ -591,6 +625,13 @@ begin
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core_irq_out => core_ext_irq
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);
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-- Assign external interrupts
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interrupts: process(all)
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begin
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int_level_in <= (others => '0');
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int_level_in(0) <= uart0_irq;
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end process;
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-- BRAM Memory slave
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bram: if MEMORY_SIZE /= 0 generate
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bram0: entity work.wishbone_bram_wrapper
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