Merge pull request #255 from antonblanchard/log-length

Add LOG_LENGTH to top-generic.vhdl
jtag-port
Anton Blanchard 4 years ago committed by GitHub
commit 081dc64d39
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@ -12,6 +12,7 @@ entity toplevel is
CLK_INPUT : positive := 100000000;
CLK_FREQUENCY : positive := 100000000;
HAS_FPU : boolean := true;
LOG_LENGTH : natural := 512;
DISABLE_FLATTEN_CORE : boolean := false;
UART_IS_16550 : boolean := true
);
@ -70,6 +71,7 @@ begin
SIM => false,
CLK_FREQ => CLK_FREQUENCY,
HAS_FPU => HAS_FPU,
LOG_LENGTH => LOG_LENGTH,
DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
UART0_IS_16550 => UART_IS_16550
)

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