microwatt/tests/xics/xics.h

#include <stdint.h>

#include "microwatt_soc.h"
#include "io.h"

#define XICS_XIRR_POLL 0x0
#define XICS_XIRR      0x4
#define XICS_RESV      0x8
#define XICS_MFRR      0xC

uint8_t xics_read8(int offset)
{
	return readb(XICS_BASE + offset);
}

void xics_write8(int offset, uint8_t val)
{
	writeb(val, XICS_BASE + offset);
}

uint32_t xics_read32(int offset)
{
	return readl(XICS_BASE + offset);
}

void xics_write32(int offset, uint32_t val)
{
	writel(val, XICS_BASE + offset);
}
XICS test case Checks interrupt masking and priorities. Adds to `make test_xics` which is run in `make check` also. Signed-off-by: Michael Neuling <mikey@neuling.org> 5 years ago			`#include <stdint.h>`

soc: Rework interconnect This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`#include "microwatt_soc.h"`
			`#include "io.h"`
XICS test case Checks interrupt masking and priorities. Adds to `make test_xics` which is run in `make check` also. Signed-off-by: Michael Neuling <mikey@neuling.org> 5 years ago
			`#define XICS_XIRR_POLL 0x0`
			`#define XICS_XIRR 0x4`
			`#define XICS_RESV 0x8`
			`#define XICS_MFRR 0xC`

			`uint8_t xics_read8(int offset)`
			`{`
soc: Rework interconnect This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`return readb(XICS_BASE + offset);`
XICS test case Checks interrupt masking and priorities. Adds to `make test_xics` which is run in `make check` also. Signed-off-by: Michael Neuling <mikey@neuling.org> 5 years ago			`}`

			`void xics_write8(int offset, uint8_t val)`
			`{`
soc: Rework interconnect This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`writeb(val, XICS_BASE + offset);`
XICS test case Checks interrupt masking and priorities. Adds to `make test_xics` which is run in `make check` also. Signed-off-by: Michael Neuling <mikey@neuling.org> 5 years ago			`}`

			`uint32_t xics_read32(int offset)`
			`{`
soc: Rework interconnect This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`return readl(XICS_BASE + offset);`
XICS test case Checks interrupt masking and priorities. Adds to `make test_xics` which is run in `make check` also. Signed-off-by: Michael Neuling <mikey@neuling.org> 5 years ago			`}`

			`void xics_write32(int offset, uint32_t val)`
			`{`
soc: Rework interconnect This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`writel(val, XICS_BASE + offset);`
XICS test case Checks interrupt masking and priorities. Adds to `make test_xics` which is run in `make check` also. Signed-off-by: Michael Neuling <mikey@neuling.org> 5 years ago			`}`