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fpu-init
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microwatt/fpga/arty_a7.xdc

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Rename a few reset signals clk -> ext_clk reset_n -> ext_rst reset -> rst Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }];
Added support for building for Arty A7 boards
5 years ago
Rename a few reset signals clk -> ext_clk reset_n -> ext_rst reset -> rst Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }];
Added support for building for Arty A7 boards
5 years ago
Arty A7 reset pin is C2 Use C2 for reset, and fix up a few whitespace issues. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
Added support for building for Arty A7 boards
5 years ago
set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }];
Add CONFIG_VOLTAGE and CFGBVS entries Remove a couple of warnings from Vivado. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]