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microwatt/fpga/soc_reset_tb.vhdl

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Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
library ieee;
use ieee.std_logic_1164.all;
entity soc_reset_tb is
end soc_reset_tb;
architecture behave of soc_reset_tb is
signal ext_clk : std_ulogic;
signal pll_clk : std_ulogic;
signal pll_locked_in : std_ulogic;
signal ext_rst_in : std_ulogic;
signal pll_rst_out : std_ulogic;
signal rst_out : std_ulogic;
constant clk_period : time := 10 ns;
type test_vector is record
pll_locked_in : std_ulogic;
ext_rst_in : std_ulogic;
soc_reset: Use counters, add synchronizers In some cases we need to keep the reset held for much longer, so use counters rather than shift registers. Additionally, some signals such as ext_rst and pll_locked or signals going from the ext_clk domain to the pll_clk domain need to be treated as async, and testing them without synchronizers is asking for trouble. Finally, make the external reset also reset the PLL. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
pll_rst_out : std_ulogic;
Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
rst_out : std_ulogic;
end record;
type test_vector_array is array (natural range <>) of test_vector;
constant test_vectors : test_vector_array := (
-- PLL not locked, reset button not pressed
('0', '1', '1', '1'),
('0', '1', '1', '1'),
('0', '1', '1', '1'),
('0', '1', '1', '1'),
soc_reset: Use counters, add synchronizers In some cases we need to keep the reset held for much longer, so use counters rather than shift registers. Additionally, some signals such as ext_rst and pll_locked or signals going from the ext_clk domain to the pll_clk domain need to be treated as async, and testing them without synchronizers is asking for trouble. Finally, make the external reset also reset the PLL. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
('0', '1', '1', '1'),
('0', '1', '1', '1'),
Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
-- Reset is removed from the PLL
('0', '1', '0', '1'),
('0', '1', '0', '1'),
('0', '1', '0', '1'),
-- At some point PLL comes out of reset
('1', '1', '0', '1'),
('1', '1', '0', '1'),
('1', '1', '0', '1'),
('1', '1', '0', '1'),
soc_reset: Use counters, add synchronizers In some cases we need to keep the reset held for much longer, so use counters rather than shift registers. Additionally, some signals such as ext_rst and pll_locked or signals going from the ext_clk domain to the pll_clk domain need to be treated as async, and testing them without synchronizers is asking for trouble. Finally, make the external reset also reset the PLL. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
('1', '1', '0', '1'),
('1', '1', '0', '1'),
Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
-- Finally SOC comes out of reset
('1', '1', '0', '0'),
('1', '1', '0', '0'),
-- PLL locked, reset button pressed
soc_reset: Use counters, add synchronizers In some cases we need to keep the reset held for much longer, so use counters rather than shift registers. Additionally, some signals such as ext_rst and pll_locked or signals going from the ext_clk domain to the pll_clk domain need to be treated as async, and testing them without synchronizers is asking for trouble. Finally, make the external reset also reset the PLL. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
('1', '0', '0', '0'),
('1', '0', '0', '0'),
('1', '0', '0', '0'),
('1', '0', '1', '1'),
Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
-- PLL locked, reset button released
soc_reset: Use counters, add synchronizers In some cases we need to keep the reset held for much longer, so use counters rather than shift registers. Additionally, some signals such as ext_rst and pll_locked or signals going from the ext_clk domain to the pll_clk domain need to be treated as async, and testing them without synchronizers is asking for trouble. Finally, make the external reset also reset the PLL. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
('1', '1', '1', '1'),
('1', '1', '1', '1'),
('1', '1', '1', '1'),
('1', '1', '1', '1'),
('1', '1', '1', '1'),
('1', '1', '1', '1'),
('1', '1', '0', '1'),
('1', '1', '0', '1'),
('1', '1', '0', '1'),
Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
('1', '1', '0', '1'),
('1', '1', '0', '1'),
('1', '1', '0', '1'),
-- Finally SOC comes out of reset
('1', '1', '0', '0')
);
begin
soc_reset_0: entity work.soc_reset
generic map (
soc_reset: Use counters, add synchronizers In some cases we need to keep the reset held for much longer, so use counters rather than shift registers. Additionally, some signals such as ext_rst and pll_locked or signals going from the ext_clk domain to the pll_clk domain need to be treated as async, and testing them without synchronizers is asking for trouble. Finally, make the external reset also reset the PLL. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
PLL_RESET_BITS => 2,
SOC_RESET_BITS => 2,
Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
RESET_LOW => true
)
port map (
ext_clk => ext_clk,
pll_clk => pll_clk,
pll_locked_in => pll_locked_in,
ext_rst_in => ext_rst_in,
pll_rst_out => pll_rst_out,
rst_out => rst_out
);
clock: process
begin
ext_clk <= '0';
pll_clk <= '0';
wait for clk_period/2;
ext_clk <= '1';
pll_clk <= '1';
wait for clk_period/2;
end process clock;
stim: process
soc_reset: Use counters, add synchronizers In some cases we need to keep the reset held for much longer, so use counters rather than shift registers. Additionally, some signals such as ext_rst and pll_locked or signals going from the ext_clk domain to the pll_clk domain need to be treated as async, and testing them without synchronizers is asking for trouble. Finally, make the external reset also reset the PLL. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
variable tv : test_vector;
Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
begin
soc_reset: Use counters, add synchronizers In some cases we need to keep the reset held for much longer, so use counters rather than shift registers. Additionally, some signals such as ext_rst and pll_locked or signals going from the ext_clk domain to the pll_clk domain need to be treated as async, and testing them without synchronizers is asking for trouble. Finally, make the external reset also reset the PLL. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
-- skew us a bit
wait for clk_period/4;
Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
for i in test_vectors'range loop
soc_reset: Use counters, add synchronizers In some cases we need to keep the reset held for much longer, so use counters rather than shift registers. Additionally, some signals such as ext_rst and pll_locked or signals going from the ext_clk domain to the pll_clk domain need to be treated as async, and testing them without synchronizers is asking for trouble. Finally, make the external reset also reset the PLL. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
tv := test_vectors(i);
pll_locked_in <= tv.pll_locked_in;
ext_rst_in <= tv.ext_rst_in;
Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
soc_reset: Use counters, add synchronizers In some cases we need to keep the reset held for much longer, so use counters rather than shift registers. Additionally, some signals such as ext_rst and pll_locked or signals going from the ext_clk domain to the pll_clk domain need to be treated as async, and testing them without synchronizers is asking for trouble. Finally, make the external reset also reset the PLL. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
report " ** STEP " & integer'image(i);
report "pll_locked_in " & std_ulogic'image(pll_locked_in);
report "ext_rst_in " & std_ulogic'image(ext_rst_in);
report "pll_rst_out " & std_ulogic'image(pll_rst_out);
report "rst_out" & std_ulogic'image(rst_out);
Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
soc_reset: Use counters, add synchronizers In some cases we need to keep the reset held for much longer, so use counters rather than shift registers. Additionally, some signals such as ext_rst and pll_locked or signals going from the ext_clk domain to the pll_clk domain need to be treated as async, and testing them without synchronizers is asking for trouble. Finally, make the external reset also reset the PLL. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
assert tv.pll_rst_out = pll_rst_out report
"pll_rst_out bad exp=" & std_ulogic'image(tv.pll_rst_out) &
" got=" & std_ulogic'image(pll_rst_out);
assert tv.rst_out = rst_out report
"rst_out bad exp=" & std_ulogic'image(tv.rst_out) &
" got=" & std_ulogic'image(rst_out);
Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
wait for clk_period;
end loop;
wait for clk_period;
assert false report "end of test" severity failure;
wait;
end process;
end behave;