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3968 lines
161 KiB
Coq
3968 lines
161 KiB
Coq
5 years ago
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// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8
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// Date : 23/03/2020, 17:06:53
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// Component : VexRiscv
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`define Src2CtrlEnum_defaultEncoding_type [1:0]
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`define Src2CtrlEnum_defaultEncoding_RS 2'b00
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`define Src2CtrlEnum_defaultEncoding_IMI 2'b01
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`define Src2CtrlEnum_defaultEncoding_IMS 2'b10
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`define Src2CtrlEnum_defaultEncoding_PC 2'b11
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`define EnvCtrlEnum_defaultEncoding_type [1:0]
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`define EnvCtrlEnum_defaultEncoding_NONE 2'b00
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`define EnvCtrlEnum_defaultEncoding_XRET 2'b01
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`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10
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`define Src1CtrlEnum_defaultEncoding_type [1:0]
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`define Src1CtrlEnum_defaultEncoding_RS 2'b00
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`define Src1CtrlEnum_defaultEncoding_IMU 2'b01
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`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10
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`define Src1CtrlEnum_defaultEncoding_URS1 2'b11
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`define BranchCtrlEnum_defaultEncoding_type [1:0]
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`define BranchCtrlEnum_defaultEncoding_INC 2'b00
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`define BranchCtrlEnum_defaultEncoding_B 2'b01
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`define BranchCtrlEnum_defaultEncoding_JAL 2'b10
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`define BranchCtrlEnum_defaultEncoding_JALR 2'b11
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`define AluCtrlEnum_defaultEncoding_type [1:0]
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`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00
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`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01
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`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10
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`define ShiftCtrlEnum_defaultEncoding_type [1:0]
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`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00
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`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01
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`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10
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`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11
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`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0]
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`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00
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`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01
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`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10
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module StreamFifoLowLatency (
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input io_push_valid,
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output io_push_ready,
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input io_push_payload_error,
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input [31:0] io_push_payload_inst,
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output reg io_pop_valid,
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input io_pop_ready,
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output reg io_pop_payload_error,
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output reg [31:0] io_pop_payload_inst,
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input io_flush,
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output [0:0] io_occupancy,
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input clk,
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input reset);
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wire _zz_5_;
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wire [0:0] _zz_6_;
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reg _zz_1_;
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reg pushPtr_willIncrement;
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reg pushPtr_willClear;
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wire pushPtr_willOverflowIfInc;
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wire pushPtr_willOverflow;
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reg popPtr_willIncrement;
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reg popPtr_willClear;
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wire popPtr_willOverflowIfInc;
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wire popPtr_willOverflow;
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wire ptrMatch;
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reg risingOccupancy;
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wire empty;
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wire full;
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wire pushing;
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wire popping;
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wire [32:0] _zz_2_;
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wire [32:0] _zz_3_;
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reg [32:0] _zz_4_;
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assign _zz_5_ = (! empty);
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assign _zz_6_ = _zz_2_[0 : 0];
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always @ (*) begin
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_zz_1_ = 1'b0;
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if(pushing)begin
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_zz_1_ = 1'b1;
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end
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end
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always @ (*) begin
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pushPtr_willIncrement = 1'b0;
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if(pushing)begin
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pushPtr_willIncrement = 1'b1;
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end
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end
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always @ (*) begin
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pushPtr_willClear = 1'b0;
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if(io_flush)begin
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pushPtr_willClear = 1'b1;
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end
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end
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assign pushPtr_willOverflowIfInc = 1'b1;
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assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
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always @ (*) begin
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popPtr_willIncrement = 1'b0;
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if(popping)begin
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popPtr_willIncrement = 1'b1;
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end
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end
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always @ (*) begin
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popPtr_willClear = 1'b0;
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if(io_flush)begin
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popPtr_willClear = 1'b1;
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end
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end
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assign popPtr_willOverflowIfInc = 1'b1;
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assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
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assign ptrMatch = 1'b1;
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assign empty = (ptrMatch && (! risingOccupancy));
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assign full = (ptrMatch && risingOccupancy);
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assign pushing = (io_push_valid && io_push_ready);
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assign popping = (io_pop_valid && io_pop_ready);
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assign io_push_ready = (! full);
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always @ (*) begin
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if(_zz_5_)begin
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io_pop_valid = 1'b1;
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end else begin
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io_pop_valid = io_push_valid;
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end
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end
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assign _zz_2_ = _zz_3_;
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always @ (*) begin
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if(_zz_5_)begin
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io_pop_payload_error = _zz_6_[0];
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end else begin
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io_pop_payload_error = io_push_payload_error;
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end
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end
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always @ (*) begin
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if(_zz_5_)begin
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io_pop_payload_inst = _zz_2_[32 : 1];
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end else begin
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io_pop_payload_inst = io_push_payload_inst;
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end
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end
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assign io_occupancy = (risingOccupancy && ptrMatch);
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assign _zz_3_ = _zz_4_;
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always @ (posedge clk) begin
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if(reset) begin
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risingOccupancy <= 1'b0;
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end else begin
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if((pushing != popping))begin
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risingOccupancy <= pushing;
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end
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if(io_flush)begin
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risingOccupancy <= 1'b0;
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end
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end
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end
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always @ (posedge clk) begin
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if(_zz_1_)begin
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_zz_4_ <= {io_push_payload_inst,io_push_payload_error};
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end
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end
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endmodule
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module VexRiscv (
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input [31:0] externalResetVector,
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input timerInterrupt,
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input softwareInterrupt,
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input [31:0] externalInterruptArray,
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output iBusWishbone_CYC,
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output iBusWishbone_STB,
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input iBusWishbone_ACK,
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output iBusWishbone_WE,
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output [29:0] iBusWishbone_ADR,
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input [31:0] iBusWishbone_DAT_MISO,
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output [31:0] iBusWishbone_DAT_MOSI,
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output [3:0] iBusWishbone_SEL,
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input iBusWishbone_ERR,
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output [1:0] iBusWishbone_BTE,
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output [2:0] iBusWishbone_CTI,
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output dBusWishbone_CYC,
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output dBusWishbone_STB,
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input dBusWishbone_ACK,
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output dBusWishbone_WE,
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output [29:0] dBusWishbone_ADR,
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input [31:0] dBusWishbone_DAT_MISO,
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output [31:0] dBusWishbone_DAT_MOSI,
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output reg [3:0] dBusWishbone_SEL,
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input dBusWishbone_ERR,
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output [1:0] dBusWishbone_BTE,
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output [2:0] dBusWishbone_CTI,
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input clk,
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input reset);
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reg [31:0] _zz_161_;
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reg [31:0] _zz_162_;
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reg [31:0] _zz_163_;
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wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready;
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wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid;
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wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;
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wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;
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wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy;
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wire _zz_164_;
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wire _zz_165_;
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wire _zz_166_;
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wire _zz_167_;
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wire _zz_168_;
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wire _zz_169_;
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wire _zz_170_;
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wire [1:0] _zz_171_;
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wire _zz_172_;
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wire _zz_173_;
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wire _zz_174_;
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wire _zz_175_;
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wire _zz_176_;
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wire _zz_177_;
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wire _zz_178_;
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wire _zz_179_;
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wire _zz_180_;
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wire _zz_181_;
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wire _zz_182_;
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wire _zz_183_;
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wire _zz_184_;
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wire _zz_185_;
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wire _zz_186_;
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wire _zz_187_;
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wire [1:0] _zz_188_;
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wire _zz_189_;
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wire [3:0] _zz_190_;
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wire [2:0] _zz_191_;
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wire [31:0] _zz_192_;
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wire [2:0] _zz_193_;
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wire [0:0] _zz_194_;
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wire [2:0] _zz_195_;
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wire [0:0] _zz_196_;
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wire [2:0] _zz_197_;
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wire [0:0] _zz_198_;
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wire [2:0] _zz_199_;
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wire [0:0] _zz_200_;
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wire [2:0] _zz_201_;
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wire [2:0] _zz_202_;
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wire [0:0] _zz_203_;
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wire [0:0] _zz_204_;
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wire [0:0] _zz_205_;
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wire [0:0] _zz_206_;
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wire [0:0] _zz_207_;
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wire [0:0] _zz_208_;
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wire [0:0] _zz_209_;
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wire [0:0] _zz_210_;
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wire [0:0] _zz_211_;
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wire [0:0] _zz_212_;
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wire [0:0] _zz_213_;
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wire [0:0] _zz_214_;
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wire [2:0] _zz_215_;
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wire [4:0] _zz_216_;
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wire [11:0] _zz_217_;
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wire [11:0] _zz_218_;
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wire [31:0] _zz_219_;
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wire [31:0] _zz_220_;
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wire [31:0] _zz_221_;
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wire [31:0] _zz_222_;
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wire [31:0] _zz_223_;
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wire [31:0] _zz_224_;
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wire [31:0] _zz_225_;
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wire [31:0] _zz_226_;
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wire [32:0] _zz_227_;
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wire [19:0] _zz_228_;
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wire [11:0] _zz_229_;
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wire [11:0] _zz_230_;
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wire [1:0] _zz_231_;
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wire [1:0] _zz_232_;
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wire [1:0] _zz_233_;
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wire [1:0] _zz_234_;
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wire [0:0] _zz_235_;
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wire [0:0] _zz_236_;
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wire [0:0] _zz_237_;
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wire [0:0] _zz_238_;
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wire [0:0] _zz_239_;
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wire [0:0] _zz_240_;
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wire [6:0] _zz_241_;
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wire _zz_242_;
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wire _zz_243_;
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wire [1:0] _zz_244_;
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wire [31:0] _zz_245_;
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wire [31:0] _zz_246_;
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wire [31:0] _zz_247_;
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wire _zz_248_;
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wire [0:0] _zz_249_;
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wire [0:0] _zz_250_;
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wire _zz_251_;
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wire [0:0] _zz_252_;
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wire [18:0] _zz_253_;
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wire [31:0] _zz_254_;
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wire [31:0] _zz_255_;
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wire [31:0] _zz_256_;
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wire [31:0] _zz_257_;
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wire [31:0] _zz_258_;
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wire [31:0] _zz_259_;
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wire _zz_260_;
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wire [1:0] _zz_261_;
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wire [1:0] _zz_262_;
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wire _zz_263_;
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wire [0:0] _zz_264_;
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wire [14:0] _zz_265_;
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wire [31:0] _zz_266_;
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wire [31:0] _zz_267_;
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wire [31:0] _zz_268_;
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wire [31:0] _zz_269_;
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wire [0:0] _zz_270_;
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wire [0:0] _zz_271_;
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wire [0:0] _zz_272_;
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wire [0:0] _zz_273_;
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wire _zz_274_;
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wire [0:0] _zz_275_;
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wire [11:0] _zz_276_;
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wire [31:0] _zz_277_;
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wire [31:0] _zz_278_;
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wire [31:0] _zz_279_;
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wire _zz_280_;
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wire [0:0] _zz_281_;
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wire [1:0] _zz_282_;
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wire [0:0] _zz_283_;
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wire [0:0] _zz_284_;
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wire [1:0] _zz_285_;
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wire [1:0] _zz_286_;
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wire _zz_287_;
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wire [0:0] _zz_288_;
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||
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wire [8:0] _zz_289_;
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wire [31:0] _zz_290_;
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wire [31:0] _zz_291_;
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wire [31:0] _zz_292_;
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wire [31:0] _zz_293_;
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wire [31:0] _zz_294_;
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wire [31:0] _zz_295_;
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wire [31:0] _zz_296_;
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wire [31:0] _zz_297_;
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wire _zz_298_;
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||
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wire _zz_299_;
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||
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wire [0:0] _zz_300_;
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||
|
|
wire [0:0] _zz_301_;
|
||
|
|
wire [1:0] _zz_302_;
|
||
|
|
wire [1:0] _zz_303_;
|
||
|
|
wire _zz_304_;
|
||
|
|
wire [0:0] _zz_305_;
|
||
|
|
wire [5:0] _zz_306_;
|
||
|
|
wire [31:0] _zz_307_;
|
||
|
|
wire [31:0] _zz_308_;
|
||
|
|
wire [31:0] _zz_309_;
|
||
|
|
wire [31:0] _zz_310_;
|
||
|
|
wire _zz_311_;
|
||
|
|
wire _zz_312_;
|
||
|
|
wire [1:0] _zz_313_;
|
||
|
|
wire [1:0] _zz_314_;
|
||
|
|
wire _zz_315_;
|
||
|
|
wire [0:0] _zz_316_;
|
||
|
|
wire [2:0] _zz_317_;
|
||
|
|
wire [31:0] _zz_318_;
|
||
|
|
wire [31:0] _zz_319_;
|
||
|
|
wire [31:0] _zz_320_;
|
||
|
|
wire [31:0] _zz_321_;
|
||
|
|
wire _zz_322_;
|
||
|
|
wire [0:0] _zz_323_;
|
||
|
|
wire [0:0] _zz_324_;
|
||
|
|
wire [0:0] _zz_325_;
|
||
|
|
wire [1:0] _zz_326_;
|
||
|
|
wire [5:0] _zz_327_;
|
||
|
|
wire [5:0] _zz_328_;
|
||
|
|
wire _zz_329_;
|
||
|
|
wire _zz_330_;
|
||
|
|
wire [31:0] _zz_331_;
|
||
|
|
wire [31:0] _zz_332_;
|
||
|
|
wire [31:0] _zz_333_;
|
||
|
|
wire [31:0] _zz_334_;
|
||
|
|
wire [31:0] _zz_335_;
|
||
|
|
wire [31:0] _zz_336_;
|
||
|
|
wire [31:0] _zz_337_;
|
||
|
|
wire _zz_338_;
|
||
|
|
wire [0:0] _zz_339_;
|
||
|
|
wire [2:0] _zz_340_;
|
||
|
|
wire [31:0] _zz_341_;
|
||
|
|
wire [31:0] _zz_342_;
|
||
|
|
wire _zz_343_;
|
||
|
|
wire _zz_344_;
|
||
|
|
wire [31:0] _zz_345_;
|
||
|
|
wire [31:0] _zz_346_;
|
||
|
|
wire [31:0] _zz_347_;
|
||
|
|
wire _zz_348_;
|
||
|
|
wire [0:0] _zz_349_;
|
||
|
|
wire [12:0] _zz_350_;
|
||
|
|
wire [31:0] _zz_351_;
|
||
|
|
wire [31:0] _zz_352_;
|
||
|
|
wire [31:0] _zz_353_;
|
||
|
|
wire _zz_354_;
|
||
|
|
wire [0:0] _zz_355_;
|
||
|
|
wire [6:0] _zz_356_;
|
||
|
|
wire [31:0] _zz_357_;
|
||
|
|
wire [31:0] _zz_358_;
|
||
|
|
wire [31:0] _zz_359_;
|
||
|
|
wire _zz_360_;
|
||
|
|
wire [0:0] _zz_361_;
|
||
|
|
wire [0:0] _zz_362_;
|
||
|
|
wire [31:0] decode_RS1;
|
||
|
|
wire execute_BRANCH_DO;
|
||
|
|
wire execute_BYPASSABLE_MEMORY_STAGE;
|
||
|
|
wire decode_BYPASSABLE_MEMORY_STAGE;
|
||
|
|
wire decode_SRC2_FORCE_ZERO;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_1_;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_2_;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_3_;
|
||
|
|
wire [31:0] writeBack_REGFILE_WRITE_DATA;
|
||
|
|
wire [31:0] execute_REGFILE_WRITE_DATA;
|
||
|
|
wire decode_CSR_WRITE_OPCODE;
|
||
|
|
wire [31:0] execute_BRANCH_CALC;
|
||
|
|
wire [31:0] writeBack_FORMAL_PC_NEXT;
|
||
|
|
wire [31:0] memory_FORMAL_PC_NEXT;
|
||
|
|
wire [31:0] execute_FORMAL_PC_NEXT;
|
||
|
|
wire [31:0] decode_FORMAL_PC_NEXT;
|
||
|
|
wire decode_SRC_LESS_UNSIGNED;
|
||
|
|
wire decode_MEMORY_STORE;
|
||
|
|
wire [31:0] memory_MEMORY_READ_DATA;
|
||
|
|
wire decode_BYPASSABLE_EXECUTE_STAGE;
|
||
|
|
wire decode_IS_CSR;
|
||
|
|
wire [31:0] decode_RS2;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_4_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_5_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_6_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_7_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_8_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_9_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_10_;
|
||
|
|
wire [1:0] memory_MEMORY_ADDRESS_LOW;
|
||
|
|
wire [1:0] execute_MEMORY_ADDRESS_LOW;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_11_;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_12_;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_13_;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_14_;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_15_;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_16_;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_17_;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_18_;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_19_;
|
||
|
|
wire decode_CSR_READ_OPCODE;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_23_;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_24_;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_25_;
|
||
|
|
wire execute_CSR_READ_OPCODE;
|
||
|
|
wire execute_CSR_WRITE_OPCODE;
|
||
|
|
wire execute_IS_CSR;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_26_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_27_;
|
||
|
|
wire _zz_28_;
|
||
|
|
wire _zz_29_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_30_;
|
||
|
|
wire [31:0] memory_BRANCH_CALC;
|
||
|
|
wire memory_BRANCH_DO;
|
||
|
|
wire [31:0] _zz_31_;
|
||
|
|
wire [31:0] execute_PC;
|
||
|
|
wire [31:0] execute_RS1;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_32_;
|
||
|
|
wire _zz_33_;
|
||
|
|
wire decode_RS2_USE;
|
||
|
|
wire decode_RS1_USE;
|
||
|
|
wire execute_REGFILE_WRITE_VALID;
|
||
|
|
wire execute_BYPASSABLE_EXECUTE_STAGE;
|
||
|
|
wire memory_REGFILE_WRITE_VALID;
|
||
|
|
wire [31:0] memory_INSTRUCTION;
|
||
|
|
wire memory_BYPASSABLE_MEMORY_STAGE;
|
||
|
|
wire writeBack_REGFILE_WRITE_VALID;
|
||
|
|
reg [31:0] _zz_34_;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_35_;
|
||
|
|
wire _zz_36_;
|
||
|
|
wire [31:0] _zz_37_;
|
||
|
|
wire [31:0] _zz_38_;
|
||
|
|
wire execute_SRC_LESS_UNSIGNED;
|
||
|
|
wire execute_SRC2_FORCE_ZERO;
|
||
|
|
wire execute_SRC_USE_SUB_LESS;
|
||
|
|
wire [31:0] _zz_39_;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_40_;
|
||
|
|
wire [31:0] _zz_41_;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_42_;
|
||
|
|
wire [31:0] _zz_43_;
|
||
|
|
wire decode_SRC_USE_SUB_LESS;
|
||
|
|
wire decode_SRC_ADD_ZERO;
|
||
|
|
wire _zz_44_;
|
||
|
|
wire [31:0] execute_SRC_ADD_SUB;
|
||
|
|
wire execute_SRC_LESS;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_45_;
|
||
|
|
wire [31:0] _zz_46_;
|
||
|
|
wire [31:0] execute_SRC2;
|
||
|
|
wire [31:0] execute_SRC1;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_47_;
|
||
|
|
wire [31:0] _zz_48_;
|
||
|
|
wire _zz_49_;
|
||
|
|
reg _zz_50_;
|
||
|
|
wire [31:0] _zz_51_;
|
||
|
|
wire [31:0] _zz_52_;
|
||
|
|
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
|
||
|
|
reg decode_REGFILE_WRITE_VALID;
|
||
|
|
wire decode_LEGAL_INSTRUCTION;
|
||
|
|
wire decode_INSTRUCTION_READY;
|
||
|
|
wire _zz_53_;
|
||
|
|
wire _zz_54_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_55_;
|
||
|
|
wire _zz_56_;
|
||
|
|
wire _zz_57_;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_59_;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_60_;
|
||
|
|
wire _zz_61_;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_62_;
|
||
|
|
wire _zz_63_;
|
||
|
|
wire _zz_64_;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_65_;
|
||
|
|
wire _zz_66_;
|
||
|
|
wire _zz_67_;
|
||
|
|
wire _zz_68_;
|
||
|
|
wire _zz_69_;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_70_;
|
||
|
|
wire _zz_71_;
|
||
|
|
wire writeBack_MEMORY_STORE;
|
||
|
|
reg [31:0] _zz_72_;
|
||
|
|
wire writeBack_MEMORY_ENABLE;
|
||
|
|
wire [1:0] writeBack_MEMORY_ADDRESS_LOW;
|
||
|
|
wire [31:0] writeBack_MEMORY_READ_DATA;
|
||
|
|
wire memory_MMU_FAULT;
|
||
|
|
wire [31:0] memory_MMU_RSP_physicalAddress;
|
||
|
|
wire memory_MMU_RSP_isIoAccess;
|
||
|
|
wire memory_MMU_RSP_allowRead;
|
||
|
|
wire memory_MMU_RSP_allowWrite;
|
||
|
|
wire memory_MMU_RSP_allowExecute;
|
||
|
|
wire memory_MMU_RSP_exception;
|
||
|
|
wire memory_MMU_RSP_refilling;
|
||
|
|
wire [31:0] memory_PC;
|
||
|
|
wire memory_ALIGNEMENT_FAULT;
|
||
|
|
wire [31:0] memory_REGFILE_WRITE_DATA;
|
||
|
|
wire memory_MEMORY_STORE;
|
||
|
|
wire memory_MEMORY_ENABLE;
|
||
|
|
wire [31:0] _zz_73_;
|
||
|
|
wire [31:0] _zz_74_;
|
||
|
|
wire _zz_75_;
|
||
|
|
wire _zz_76_;
|
||
|
|
wire _zz_77_;
|
||
|
|
wire _zz_78_;
|
||
|
|
wire _zz_79_;
|
||
|
|
wire _zz_80_;
|
||
|
|
wire execute_MMU_FAULT;
|
||
|
|
wire [31:0] execute_MMU_RSP_physicalAddress;
|
||
|
|
wire execute_MMU_RSP_isIoAccess;
|
||
|
|
wire execute_MMU_RSP_allowRead;
|
||
|
|
wire execute_MMU_RSP_allowWrite;
|
||
|
|
wire execute_MMU_RSP_allowExecute;
|
||
|
|
wire execute_MMU_RSP_exception;
|
||
|
|
wire execute_MMU_RSP_refilling;
|
||
|
|
wire _zz_81_;
|
||
|
|
wire [31:0] execute_SRC_ADD;
|
||
|
|
wire [1:0] _zz_82_;
|
||
|
|
wire [31:0] execute_RS2;
|
||
|
|
wire [31:0] execute_INSTRUCTION;
|
||
|
|
wire execute_MEMORY_STORE;
|
||
|
|
wire execute_MEMORY_ENABLE;
|
||
|
|
wire execute_ALIGNEMENT_FAULT;
|
||
|
|
wire _zz_83_;
|
||
|
|
wire decode_MEMORY_ENABLE;
|
||
|
|
reg [31:0] _zz_84_;
|
||
|
|
reg [31:0] _zz_85_;
|
||
|
|
wire [31:0] decode_PC;
|
||
|
|
wire [31:0] _zz_86_;
|
||
|
|
wire [31:0] _zz_87_;
|
||
|
|
wire [31:0] _zz_88_;
|
||
|
|
wire [31:0] decode_INSTRUCTION;
|
||
|
|
wire [31:0] _zz_89_;
|
||
|
|
wire [31:0] writeBack_PC;
|
||
|
|
wire [31:0] writeBack_INSTRUCTION;
|
||
|
|
reg decode_arbitration_haltItself;
|
||
|
|
reg decode_arbitration_haltByOther;
|
||
|
|
reg decode_arbitration_removeIt;
|
||
|
|
reg decode_arbitration_flushIt;
|
||
|
|
reg decode_arbitration_flushNext;
|
||
|
|
wire decode_arbitration_isValid;
|
||
|
|
wire decode_arbitration_isStuck;
|
||
|
|
wire decode_arbitration_isStuckByOthers;
|
||
|
|
wire decode_arbitration_isFlushed;
|
||
|
|
wire decode_arbitration_isMoving;
|
||
|
|
wire decode_arbitration_isFiring;
|
||
|
|
reg execute_arbitration_haltItself;
|
||
|
|
wire execute_arbitration_haltByOther;
|
||
|
|
reg execute_arbitration_removeIt;
|
||
|
|
wire execute_arbitration_flushIt;
|
||
|
|
reg execute_arbitration_flushNext;
|
||
|
|
reg execute_arbitration_isValid;
|
||
|
|
wire execute_arbitration_isStuck;
|
||
|
|
wire execute_arbitration_isStuckByOthers;
|
||
|
|
wire execute_arbitration_isFlushed;
|
||
|
|
wire execute_arbitration_isMoving;
|
||
|
|
wire execute_arbitration_isFiring;
|
||
|
|
reg memory_arbitration_haltItself;
|
||
|
|
wire memory_arbitration_haltByOther;
|
||
|
|
reg memory_arbitration_removeIt;
|
||
|
|
reg memory_arbitration_flushIt;
|
||
|
|
reg memory_arbitration_flushNext;
|
||
|
|
reg memory_arbitration_isValid;
|
||
|
|
wire memory_arbitration_isStuck;
|
||
|
|
wire memory_arbitration_isStuckByOthers;
|
||
|
|
wire memory_arbitration_isFlushed;
|
||
|
|
wire memory_arbitration_isMoving;
|
||
|
|
wire memory_arbitration_isFiring;
|
||
|
|
wire writeBack_arbitration_haltItself;
|
||
|
|
wire writeBack_arbitration_haltByOther;
|
||
|
|
reg writeBack_arbitration_removeIt;
|
||
|
|
wire writeBack_arbitration_flushIt;
|
||
|
|
reg writeBack_arbitration_flushNext;
|
||
|
|
reg writeBack_arbitration_isValid;
|
||
|
|
wire writeBack_arbitration_isStuck;
|
||
|
|
wire writeBack_arbitration_isStuckByOthers;
|
||
|
|
wire writeBack_arbitration_isFlushed;
|
||
|
|
wire writeBack_arbitration_isMoving;
|
||
|
|
wire writeBack_arbitration_isFiring;
|
||
|
|
wire [31:0] lastStageInstruction /* verilator public */ ;
|
||
|
|
wire [31:0] lastStagePc /* verilator public */ ;
|
||
|
|
wire lastStageIsValid /* verilator public */ ;
|
||
|
|
wire lastStageIsFiring /* verilator public */ ;
|
||
|
|
reg IBusSimplePlugin_fetcherHalt;
|
||
|
|
reg IBusSimplePlugin_fetcherflushIt;
|
||
|
|
reg IBusSimplePlugin_incomingInstruction;
|
||
|
|
wire IBusSimplePlugin_pcValids_0;
|
||
|
|
wire IBusSimplePlugin_pcValids_1;
|
||
|
|
wire IBusSimplePlugin_pcValids_2;
|
||
|
|
wire IBusSimplePlugin_pcValids_3;
|
||
|
|
wire iBus_cmd_valid;
|
||
|
|
wire iBus_cmd_ready;
|
||
|
|
wire [31:0] iBus_cmd_payload_pc;
|
||
|
|
wire iBus_rsp_valid;
|
||
|
|
wire iBus_rsp_payload_error;
|
||
|
|
wire [31:0] iBus_rsp_payload_inst;
|
||
|
|
wire IBusSimplePlugin_decodeExceptionPort_valid;
|
||
|
|
reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code;
|
||
|
|
wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr;
|
||
|
|
wire IBusSimplePlugin_mmuBus_cmd_isValid;
|
||
|
|
wire [31:0] IBusSimplePlugin_mmuBus_cmd_virtualAddress;
|
||
|
|
wire IBusSimplePlugin_mmuBus_cmd_bypassTranslation;
|
||
|
|
wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress;
|
||
|
|
wire IBusSimplePlugin_mmuBus_rsp_isIoAccess;
|
||
|
|
wire IBusSimplePlugin_mmuBus_rsp_allowRead;
|
||
|
|
wire IBusSimplePlugin_mmuBus_rsp_allowWrite;
|
||
|
|
wire IBusSimplePlugin_mmuBus_rsp_allowExecute;
|
||
|
|
wire IBusSimplePlugin_mmuBus_rsp_exception;
|
||
|
|
wire IBusSimplePlugin_mmuBus_rsp_refilling;
|
||
|
|
wire IBusSimplePlugin_mmuBus_end;
|
||
|
|
wire IBusSimplePlugin_mmuBus_busy;
|
||
|
|
wire IBusSimplePlugin_redoBranch_valid;
|
||
|
|
wire [31:0] IBusSimplePlugin_redoBranch_payload;
|
||
|
|
reg DBusSimplePlugin_memoryExceptionPort_valid;
|
||
|
|
reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code;
|
||
|
|
wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr;
|
||
|
|
wire DBusSimplePlugin_mmuBus_cmd_isValid;
|
||
|
|
wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress;
|
||
|
|
wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation;
|
||
|
|
wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress;
|
||
|
|
wire DBusSimplePlugin_mmuBus_rsp_isIoAccess;
|
||
|
|
wire DBusSimplePlugin_mmuBus_rsp_allowRead;
|
||
|
|
wire DBusSimplePlugin_mmuBus_rsp_allowWrite;
|
||
|
|
wire DBusSimplePlugin_mmuBus_rsp_allowExecute;
|
||
|
|
wire DBusSimplePlugin_mmuBus_rsp_exception;
|
||
|
|
wire DBusSimplePlugin_mmuBus_rsp_refilling;
|
||
|
|
wire DBusSimplePlugin_mmuBus_end;
|
||
|
|
wire DBusSimplePlugin_mmuBus_busy;
|
||
|
|
reg DBusSimplePlugin_redoBranch_valid;
|
||
|
|
wire [31:0] DBusSimplePlugin_redoBranch_payload;
|
||
|
|
wire decodeExceptionPort_valid;
|
||
|
|
wire [3:0] decodeExceptionPort_payload_code;
|
||
|
|
wire [31:0] decodeExceptionPort_payload_badAddr;
|
||
|
|
wire BranchPlugin_jumpInterface_valid;
|
||
|
|
wire [31:0] BranchPlugin_jumpInterface_payload;
|
||
|
|
wire BranchPlugin_branchExceptionPort_valid;
|
||
|
|
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
|
||
|
|
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
|
||
|
|
reg CsrPlugin_jumpInterface_valid;
|
||
|
|
reg [31:0] CsrPlugin_jumpInterface_payload;
|
||
|
|
wire CsrPlugin_exceptionPendings_0;
|
||
|
|
wire CsrPlugin_exceptionPendings_1;
|
||
|
|
wire CsrPlugin_exceptionPendings_2;
|
||
|
|
wire CsrPlugin_exceptionPendings_3;
|
||
|
|
wire externalInterrupt;
|
||
|
|
wire contextSwitching;
|
||
|
|
reg [1:0] CsrPlugin_privilege;
|
||
|
|
wire CsrPlugin_forceMachineWire;
|
||
|
|
reg CsrPlugin_selfException_valid;
|
||
|
|
reg [3:0] CsrPlugin_selfException_payload_code;
|
||
|
|
wire [31:0] CsrPlugin_selfException_payload_badAddr;
|
||
|
|
wire CsrPlugin_allowInterrupts;
|
||
|
|
wire CsrPlugin_allowException;
|
||
|
|
wire IBusSimplePlugin_jump_pcLoad_valid;
|
||
|
|
wire [31:0] IBusSimplePlugin_jump_pcLoad_payload;
|
||
|
|
wire [3:0] _zz_90_;
|
||
|
|
wire [3:0] _zz_91_;
|
||
|
|
wire _zz_92_;
|
||
|
|
wire _zz_93_;
|
||
|
|
wire _zz_94_;
|
||
|
|
wire IBusSimplePlugin_fetchPc_output_valid;
|
||
|
|
wire IBusSimplePlugin_fetchPc_output_ready;
|
||
|
|
wire [31:0] IBusSimplePlugin_fetchPc_output_payload;
|
||
|
|
reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ;
|
||
|
|
reg IBusSimplePlugin_fetchPc_corrected;
|
||
|
|
reg IBusSimplePlugin_fetchPc_pcRegPropagate;
|
||
|
|
reg IBusSimplePlugin_fetchPc_booted;
|
||
|
|
reg IBusSimplePlugin_fetchPc_inc;
|
||
|
|
reg [31:0] IBusSimplePlugin_fetchPc_pc;
|
||
|
|
reg IBusSimplePlugin_iBusRsp_stages_0_input_valid;
|
||
|
|
reg IBusSimplePlugin_iBusRsp_stages_0_input_ready;
|
||
|
|
wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_stages_0_output_valid;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_stages_0_output_ready;
|
||
|
|
wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload;
|
||
|
|
reg IBusSimplePlugin_iBusRsp_stages_0_halt;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_stages_0_inputSample;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_stages_1_input_valid;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_stages_1_input_ready;
|
||
|
|
wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_stages_1_output_valid;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_stages_1_output_ready;
|
||
|
|
wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_stages_1_halt;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_stages_1_inputSample;
|
||
|
|
wire _zz_95_;
|
||
|
|
wire _zz_96_;
|
||
|
|
wire _zz_97_;
|
||
|
|
wire _zz_98_;
|
||
|
|
reg _zz_99_;
|
||
|
|
reg IBusSimplePlugin_iBusRsp_readyForError;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_inputBeforeStage_valid;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_inputBeforeStage_ready;
|
||
|
|
wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error;
|
||
|
|
wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst;
|
||
|
|
wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc;
|
||
|
|
wire IBusSimplePlugin_injector_decodeInput_valid;
|
||
|
|
wire IBusSimplePlugin_injector_decodeInput_ready;
|
||
|
|
wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc;
|
||
|
|
wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error;
|
||
|
|
wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
|
||
|
|
wire IBusSimplePlugin_injector_decodeInput_payload_isRvc;
|
||
|
|
reg _zz_100_;
|
||
|
|
reg [31:0] _zz_101_;
|
||
|
|
reg _zz_102_;
|
||
|
|
reg [31:0] _zz_103_;
|
||
|
|
reg _zz_104_;
|
||
|
|
reg IBusSimplePlugin_injector_nextPcCalc_valids_0;
|
||
|
|
reg IBusSimplePlugin_injector_nextPcCalc_valids_1;
|
||
|
|
reg IBusSimplePlugin_injector_nextPcCalc_valids_2;
|
||
|
|
reg IBusSimplePlugin_injector_nextPcCalc_valids_3;
|
||
|
|
reg IBusSimplePlugin_injector_nextPcCalc_valids_4;
|
||
|
|
reg IBusSimplePlugin_injector_decodeRemoved;
|
||
|
|
reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode;
|
||
|
|
reg IBusSimplePlugin_cmd_valid;
|
||
|
|
wire IBusSimplePlugin_cmd_ready;
|
||
|
|
wire [31:0] IBusSimplePlugin_cmd_payload_pc;
|
||
|
|
reg [2:0] IBusSimplePlugin_pendingCmd;
|
||
|
|
wire [2:0] IBusSimplePlugin_pendingCmdNext;
|
||
|
|
reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress;
|
||
|
|
reg IBusSimplePlugin_mmu_joinCtx_isIoAccess;
|
||
|
|
reg IBusSimplePlugin_mmu_joinCtx_allowRead;
|
||
|
|
reg IBusSimplePlugin_mmu_joinCtx_allowWrite;
|
||
|
|
reg IBusSimplePlugin_mmu_joinCtx_allowExecute;
|
||
|
|
reg IBusSimplePlugin_mmu_joinCtx_exception;
|
||
|
|
reg IBusSimplePlugin_mmu_joinCtx_refilling;
|
||
|
|
reg [2:0] IBusSimplePlugin_rspJoin_discardCounter;
|
||
|
|
wire IBusSimplePlugin_rspJoin_rspBufferOutput_valid;
|
||
|
|
wire IBusSimplePlugin_rspJoin_rspBufferOutput_ready;
|
||
|
|
wire IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error;
|
||
|
|
wire [31:0] IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst;
|
||
|
|
wire iBus_rsp_takeWhen_valid;
|
||
|
|
wire iBus_rsp_takeWhen_payload_error;
|
||
|
|
wire [31:0] iBus_rsp_takeWhen_payload_inst;
|
||
|
|
wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc;
|
||
|
|
reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error;
|
||
|
|
wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;
|
||
|
|
wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc;
|
||
|
|
wire IBusSimplePlugin_rspJoin_join_valid;
|
||
|
|
wire IBusSimplePlugin_rspJoin_join_ready;
|
||
|
|
wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc;
|
||
|
|
wire IBusSimplePlugin_rspJoin_join_payload_rsp_error;
|
||
|
|
wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst;
|
||
|
|
wire IBusSimplePlugin_rspJoin_join_payload_isRvc;
|
||
|
|
reg IBusSimplePlugin_rspJoin_exceptionDetected;
|
||
|
|
reg IBusSimplePlugin_rspJoin_redoRequired;
|
||
|
|
wire _zz_105_;
|
||
|
|
wire dBus_cmd_valid;
|
||
|
|
wire dBus_cmd_ready;
|
||
|
|
wire dBus_cmd_payload_wr;
|
||
|
|
wire [31:0] dBus_cmd_payload_address;
|
||
|
|
wire [31:0] dBus_cmd_payload_data;
|
||
|
|
wire [1:0] dBus_cmd_payload_size;
|
||
|
|
wire dBus_rsp_ready;
|
||
|
|
wire dBus_rsp_error;
|
||
|
|
wire [31:0] dBus_rsp_data;
|
||
|
|
wire _zz_106_;
|
||
|
|
reg execute_DBusSimplePlugin_skipCmd;
|
||
|
|
reg [31:0] _zz_107_;
|
||
|
|
reg [3:0] _zz_108_;
|
||
|
|
wire [3:0] execute_DBusSimplePlugin_formalMask;
|
||
|
|
reg [31:0] writeBack_DBusSimplePlugin_rspShifted;
|
||
|
|
wire _zz_109_;
|
||
|
|
reg [31:0] _zz_110_;
|
||
|
|
wire _zz_111_;
|
||
|
|
reg [31:0] _zz_112_;
|
||
|
|
reg [31:0] writeBack_DBusSimplePlugin_rspFormated;
|
||
|
|
wire [25:0] _zz_113_;
|
||
|
|
wire _zz_114_;
|
||
|
|
wire _zz_115_;
|
||
|
|
wire _zz_116_;
|
||
|
|
wire _zz_117_;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_118_;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_119_;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_120_;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_121_;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_122_;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_123_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_124_;
|
||
|
|
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
|
||
|
|
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
|
||
|
|
wire [31:0] decode_RegFilePlugin_rs1Data;
|
||
|
|
wire [31:0] decode_RegFilePlugin_rs2Data;
|
||
|
|
reg lastStageRegFileWrite_valid /* verilator public */ ;
|
||
|
|
wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
|
||
|
|
wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
|
||
|
|
reg _zz_125_;
|
||
|
|
reg [31:0] execute_IntAluPlugin_bitwise;
|
||
|
|
reg [31:0] _zz_126_;
|
||
|
|
reg [31:0] _zz_127_;
|
||
|
|
wire _zz_128_;
|
||
|
|
reg [19:0] _zz_129_;
|
||
|
|
wire _zz_130_;
|
||
|
|
reg [19:0] _zz_131_;
|
||
|
|
reg [31:0] _zz_132_;
|
||
|
|
reg [31:0] execute_SrcPlugin_addSub;
|
||
|
|
wire execute_SrcPlugin_less;
|
||
|
|
reg execute_LightShifterPlugin_isActive;
|
||
|
|
wire execute_LightShifterPlugin_isShift;
|
||
|
|
reg [4:0] execute_LightShifterPlugin_amplitudeReg;
|
||
|
|
wire [4:0] execute_LightShifterPlugin_amplitude;
|
||
|
|
wire [31:0] execute_LightShifterPlugin_shiftInput;
|
||
|
|
wire execute_LightShifterPlugin_done;
|
||
|
|
reg [31:0] _zz_133_;
|
||
|
|
reg _zz_134_;
|
||
|
|
reg _zz_135_;
|
||
|
|
wire _zz_136_;
|
||
|
|
reg _zz_137_;
|
||
|
|
reg [4:0] _zz_138_;
|
||
|
|
wire execute_BranchPlugin_eq;
|
||
|
|
wire [2:0] _zz_139_;
|
||
|
|
reg _zz_140_;
|
||
|
|
reg _zz_141_;
|
||
|
|
wire [31:0] execute_BranchPlugin_branch_src1;
|
||
|
|
wire _zz_142_;
|
||
|
|
reg [10:0] _zz_143_;
|
||
|
|
wire _zz_144_;
|
||
|
|
reg [19:0] _zz_145_;
|
||
|
|
wire _zz_146_;
|
||
|
|
reg [18:0] _zz_147_;
|
||
|
|
reg [31:0] _zz_148_;
|
||
|
|
wire [31:0] execute_BranchPlugin_branch_src2;
|
||
|
|
wire [31:0] execute_BranchPlugin_branchAdder;
|
||
|
|
wire [1:0] CsrPlugin_misa_base;
|
||
|
|
wire [25:0] CsrPlugin_misa_extensions;
|
||
|
|
reg [1:0] CsrPlugin_mtvec_mode;
|
||
|
|
reg [29:0] CsrPlugin_mtvec_base;
|
||
|
|
reg [31:0] CsrPlugin_mepc;
|
||
|
|
reg CsrPlugin_mstatus_MIE;
|
||
|
|
reg CsrPlugin_mstatus_MPIE;
|
||
|
|
reg [1:0] CsrPlugin_mstatus_MPP;
|
||
|
|
reg CsrPlugin_mip_MEIP;
|
||
|
|
reg CsrPlugin_mip_MTIP;
|
||
|
|
reg CsrPlugin_mip_MSIP;
|
||
|
|
reg CsrPlugin_mie_MEIE;
|
||
|
|
reg CsrPlugin_mie_MTIE;
|
||
|
|
reg CsrPlugin_mie_MSIE;
|
||
|
|
reg CsrPlugin_mcause_interrupt;
|
||
|
|
reg [3:0] CsrPlugin_mcause_exceptionCode;
|
||
|
|
reg [31:0] CsrPlugin_mtval;
|
||
|
|
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
|
||
|
|
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
|
||
|
|
wire _zz_149_;
|
||
|
|
wire _zz_150_;
|
||
|
|
wire _zz_151_;
|
||
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
|
||
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
|
||
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
|
||
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
|
||
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
|
||
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
|
||
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
|
||
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
|
||
|
|
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
|
||
|
|
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
|
||
|
|
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
|
||
|
|
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
|
||
|
|
wire [1:0] _zz_152_;
|
||
|
|
wire _zz_153_;
|
||
|
|
wire [1:0] _zz_154_;
|
||
|
|
wire _zz_155_;
|
||
|
|
reg CsrPlugin_interrupt_valid;
|
||
|
|
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
|
||
|
|
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
|
||
|
|
wire CsrPlugin_exception;
|
||
|
|
wire CsrPlugin_lastStageWasWfi;
|
||
|
|
reg CsrPlugin_pipelineLiberator_done;
|
||
|
|
wire CsrPlugin_interruptJump /* verilator public */ ;
|
||
|
|
reg CsrPlugin_hadException;
|
||
|
|
reg [1:0] CsrPlugin_targetPrivilege;
|
||
|
|
reg [3:0] CsrPlugin_trapCause;
|
||
|
|
reg [1:0] CsrPlugin_xtvec_mode;
|
||
|
|
reg [29:0] CsrPlugin_xtvec_base;
|
||
|
|
wire execute_CsrPlugin_inWfi /* verilator public */ ;
|
||
|
|
reg execute_CsrPlugin_wfiWake;
|
||
|
|
wire execute_CsrPlugin_blockedBySideEffects;
|
||
|
|
reg execute_CsrPlugin_illegalAccess;
|
||
|
|
reg execute_CsrPlugin_illegalInstruction;
|
||
|
|
reg [31:0] execute_CsrPlugin_readData;
|
||
|
|
wire execute_CsrPlugin_writeInstruction;
|
||
|
|
wire execute_CsrPlugin_readInstruction;
|
||
|
|
wire execute_CsrPlugin_writeEnable;
|
||
|
|
wire execute_CsrPlugin_readEnable;
|
||
|
|
wire [31:0] execute_CsrPlugin_readToWriteData;
|
||
|
|
reg [31:0] execute_CsrPlugin_writeData;
|
||
|
|
wire [11:0] execute_CsrPlugin_csrAddress;
|
||
|
|
reg [31:0] externalInterruptArray_regNext;
|
||
|
|
reg [31:0] _zz_156_;
|
||
|
|
wire [31:0] _zz_157_;
|
||
|
|
reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL;
|
||
|
|
reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL;
|
||
|
|
reg decode_to_execute_SRC_USE_SUB_LESS;
|
||
|
|
reg execute_to_memory_MMU_FAULT;
|
||
|
|
reg decode_to_execute_CSR_READ_OPCODE;
|
||
|
|
reg [31:0] execute_to_memory_MMU_RSP_physicalAddress;
|
||
|
|
reg execute_to_memory_MMU_RSP_isIoAccess;
|
||
|
|
reg execute_to_memory_MMU_RSP_allowRead;
|
||
|
|
reg execute_to_memory_MMU_RSP_allowWrite;
|
||
|
|
reg execute_to_memory_MMU_RSP_allowExecute;
|
||
|
|
reg execute_to_memory_MMU_RSP_exception;
|
||
|
|
reg execute_to_memory_MMU_RSP_refilling;
|
||
|
|
reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL;
|
||
|
|
reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL;
|
||
|
|
reg execute_to_memory_ALIGNEMENT_FAULT;
|
||
|
|
reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL;
|
||
|
|
reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW;
|
||
|
|
reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW;
|
||
|
|
reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL;
|
||
|
|
reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL;
|
||
|
|
reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL;
|
||
|
|
reg [31:0] decode_to_execute_RS2;
|
||
|
|
reg decode_to_execute_IS_CSR;
|
||
|
|
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
|
||
|
|
reg [31:0] memory_to_writeBack_MEMORY_READ_DATA;
|
||
|
|
reg decode_to_execute_MEMORY_STORE;
|
||
|
|
reg execute_to_memory_MEMORY_STORE;
|
||
|
|
reg memory_to_writeBack_MEMORY_STORE;
|
||
|
|
reg decode_to_execute_SRC_LESS_UNSIGNED;
|
||
|
|
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
|
||
|
|
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
|
||
|
|
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
|
||
|
|
reg decode_to_execute_MEMORY_ENABLE;
|
||
|
|
reg execute_to_memory_MEMORY_ENABLE;
|
||
|
|
reg memory_to_writeBack_MEMORY_ENABLE;
|
||
|
|
reg [31:0] decode_to_execute_PC;
|
||
|
|
reg [31:0] execute_to_memory_PC;
|
||
|
|
reg [31:0] memory_to_writeBack_PC;
|
||
|
|
reg [31:0] execute_to_memory_BRANCH_CALC;
|
||
|
|
reg decode_to_execute_CSR_WRITE_OPCODE;
|
||
|
|
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
|
||
|
|
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
|
||
|
|
reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL;
|
||
|
|
reg decode_to_execute_SRC2_FORCE_ZERO;
|
||
|
|
reg [31:0] decode_to_execute_INSTRUCTION;
|
||
|
|
reg [31:0] execute_to_memory_INSTRUCTION;
|
||
|
|
reg [31:0] memory_to_writeBack_INSTRUCTION;
|
||
|
|
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
|
||
|
|
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
|
||
|
|
reg execute_to_memory_BRANCH_DO;
|
||
|
|
reg [31:0] decode_to_execute_RS1;
|
||
|
|
reg decode_to_execute_REGFILE_WRITE_VALID;
|
||
|
|
reg execute_to_memory_REGFILE_WRITE_VALID;
|
||
|
|
reg memory_to_writeBack_REGFILE_WRITE_VALID;
|
||
|
|
wire iBus_cmd_m2sPipe_valid;
|
||
|
|
wire iBus_cmd_m2sPipe_ready;
|
||
|
|
wire [31:0] iBus_cmd_m2sPipe_payload_pc;
|
||
|
|
reg _zz_158_;
|
||
|
|
reg [31:0] _zz_159_;
|
||
|
|
wire dBus_cmd_halfPipe_valid;
|
||
|
|
wire dBus_cmd_halfPipe_ready;
|
||
|
|
wire dBus_cmd_halfPipe_payload_wr;
|
||
|
|
wire [31:0] dBus_cmd_halfPipe_payload_address;
|
||
|
|
wire [31:0] dBus_cmd_halfPipe_payload_data;
|
||
|
|
wire [1:0] dBus_cmd_halfPipe_payload_size;
|
||
|
|
reg dBus_cmd_halfPipe_regs_valid;
|
||
|
|
reg dBus_cmd_halfPipe_regs_ready;
|
||
|
|
reg dBus_cmd_halfPipe_regs_payload_wr;
|
||
|
|
reg [31:0] dBus_cmd_halfPipe_regs_payload_address;
|
||
|
|
reg [31:0] dBus_cmd_halfPipe_regs_payload_data;
|
||
|
|
reg [1:0] dBus_cmd_halfPipe_regs_payload_size;
|
||
|
|
reg [3:0] _zz_160_;
|
||
|
|
`ifndef SYNTHESIS
|
||
|
|
reg [23:0] decode_SRC2_CTRL_string;
|
||
|
|
reg [23:0] _zz_1__string;
|
||
|
|
reg [23:0] _zz_2__string;
|
||
|
|
reg [23:0] _zz_3__string;
|
||
|
|
reg [39:0] _zz_4__string;
|
||
|
|
reg [39:0] _zz_5__string;
|
||
|
|
reg [39:0] _zz_6__string;
|
||
|
|
reg [39:0] _zz_7__string;
|
||
|
|
reg [39:0] decode_ENV_CTRL_string;
|
||
|
|
reg [39:0] _zz_8__string;
|
||
|
|
reg [39:0] _zz_9__string;
|
||
|
|
reg [39:0] _zz_10__string;
|
||
|
|
reg [95:0] decode_SRC1_CTRL_string;
|
||
|
|
reg [95:0] _zz_11__string;
|
||
|
|
reg [95:0] _zz_12__string;
|
||
|
|
reg [95:0] _zz_13__string;
|
||
|
|
reg [31:0] decode_BRANCH_CTRL_string;
|
||
|
|
reg [31:0] _zz_14__string;
|
||
|
|
reg [31:0] _zz_15__string;
|
||
|
|
reg [31:0] _zz_16__string;
|
||
|
|
reg [63:0] decode_ALU_CTRL_string;
|
||
|
|
reg [63:0] _zz_17__string;
|
||
|
|
reg [63:0] _zz_18__string;
|
||
|
|
reg [63:0] _zz_19__string;
|
||
|
|
reg [71:0] decode_SHIFT_CTRL_string;
|
||
|
|
reg [71:0] _zz_20__string;
|
||
|
|
reg [71:0] _zz_21__string;
|
||
|
|
reg [71:0] _zz_22__string;
|
||
|
|
reg [39:0] decode_ALU_BITWISE_CTRL_string;
|
||
|
|
reg [39:0] _zz_23__string;
|
||
|
|
reg [39:0] _zz_24__string;
|
||
|
|
reg [39:0] _zz_25__string;
|
||
|
|
reg [39:0] memory_ENV_CTRL_string;
|
||
|
|
reg [39:0] _zz_26__string;
|
||
|
|
reg [39:0] execute_ENV_CTRL_string;
|
||
|
|
reg [39:0] _zz_27__string;
|
||
|
|
reg [39:0] writeBack_ENV_CTRL_string;
|
||
|
|
reg [39:0] _zz_30__string;
|
||
|
|
reg [31:0] execute_BRANCH_CTRL_string;
|
||
|
|
reg [31:0] _zz_32__string;
|
||
|
|
reg [71:0] execute_SHIFT_CTRL_string;
|
||
|
|
reg [71:0] _zz_35__string;
|
||
|
|
reg [23:0] execute_SRC2_CTRL_string;
|
||
|
|
reg [23:0] _zz_40__string;
|
||
|
|
reg [95:0] execute_SRC1_CTRL_string;
|
||
|
|
reg [95:0] _zz_42__string;
|
||
|
|
reg [63:0] execute_ALU_CTRL_string;
|
||
|
|
reg [63:0] _zz_45__string;
|
||
|
|
reg [39:0] execute_ALU_BITWISE_CTRL_string;
|
||
|
|
reg [39:0] _zz_47__string;
|
||
|
|
reg [39:0] _zz_55__string;
|
||
|
|
reg [39:0] _zz_58__string;
|
||
|
|
reg [31:0] _zz_59__string;
|
||
|
|
reg [63:0] _zz_60__string;
|
||
|
|
reg [23:0] _zz_62__string;
|
||
|
|
reg [95:0] _zz_65__string;
|
||
|
|
reg [71:0] _zz_70__string;
|
||
|
|
reg [71:0] _zz_118__string;
|
||
|
|
reg [95:0] _zz_119__string;
|
||
|
|
reg [23:0] _zz_120__string;
|
||
|
|
reg [63:0] _zz_121__string;
|
||
|
|
reg [31:0] _zz_122__string;
|
||
|
|
reg [39:0] _zz_123__string;
|
||
|
|
reg [39:0] _zz_124__string;
|
||
|
|
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
|
||
|
|
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
|
||
|
|
reg [63:0] decode_to_execute_ALU_CTRL_string;
|
||
|
|
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
|
||
|
|
reg [95:0] decode_to_execute_SRC1_CTRL_string;
|
||
|
|
reg [39:0] decode_to_execute_ENV_CTRL_string;
|
||
|
|
reg [39:0] execute_to_memory_ENV_CTRL_string;
|
||
|
|
reg [39:0] memory_to_writeBack_ENV_CTRL_string;
|
||
|
|
reg [23:0] decode_to_execute_SRC2_CTRL_string;
|
||
|
|
`endif
|
||
|
|
|
||
|
|
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
|
||
|
|
assign _zz_164_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000)));
|
||
|
|
assign _zz_165_ = (execute_arbitration_isValid && execute_IS_CSR);
|
||
|
|
assign _zz_166_ = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != (2'b00));
|
||
|
|
assign _zz_167_ = (! execute_arbitration_isStuckByOthers);
|
||
|
|
assign _zz_168_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2'b00));
|
||
|
|
assign _zz_169_ = (CsrPlugin_hadException || CsrPlugin_interruptJump);
|
||
|
|
assign _zz_170_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET));
|
||
|
|
assign _zz_171_ = writeBack_INSTRUCTION[29 : 28];
|
||
|
|
assign _zz_172_ = (IBusSimplePlugin_mmuBus_rsp_exception || IBusSimplePlugin_mmuBus_rsp_refilling);
|
||
|
|
assign _zz_173_ = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute)));
|
||
|
|
assign _zz_174_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE));
|
||
|
|
assign _zz_175_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers))));
|
||
|
|
assign _zz_176_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
|
||
|
|
assign _zz_177_ = (1'b1 || (! 1'b1));
|
||
|
|
assign _zz_178_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
|
||
|
|
assign _zz_179_ = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE));
|
||
|
|
assign _zz_180_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
|
||
|
|
assign _zz_181_ = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE));
|
||
|
|
assign _zz_182_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL));
|
||
|
|
assign _zz_183_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11)));
|
||
|
|
assign _zz_184_ = ((_zz_149_ && 1'b1) && (! 1'b0));
|
||
|
|
assign _zz_185_ = ((_zz_150_ && 1'b1) && (! 1'b0));
|
||
|
|
assign _zz_186_ = ((_zz_151_ && 1'b1) && (! 1'b0));
|
||
|
|
assign _zz_187_ = (! dBus_cmd_halfPipe_regs_valid);
|
||
|
|
assign _zz_188_ = writeBack_INSTRUCTION[13 : 12];
|
||
|
|
assign _zz_189_ = execute_INSTRUCTION[13];
|
||
|
|
assign _zz_190_ = (_zz_90_ - (4'b0001));
|
||
|
|
assign _zz_191_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)};
|
||
|
|
assign _zz_192_ = {29'd0, _zz_191_};
|
||
|
|
assign _zz_193_ = (IBusSimplePlugin_pendingCmd + _zz_195_);
|
||
|
|
assign _zz_194_ = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready);
|
||
|
|
assign _zz_195_ = {2'd0, _zz_194_};
|
||
|
|
assign _zz_196_ = iBus_rsp_valid;
|
||
|
|
assign _zz_197_ = {2'd0, _zz_196_};
|
||
|
|
assign _zz_198_ = (iBus_rsp_valid && (IBusSimplePlugin_rspJoin_discardCounter != (3'b000)));
|
||
|
|
assign _zz_199_ = {2'd0, _zz_198_};
|
||
|
|
assign _zz_200_ = iBus_rsp_valid;
|
||
|
|
assign _zz_201_ = {2'd0, _zz_200_};
|
||
|
|
assign _zz_202_ = (memory_MEMORY_STORE ? (3'b110) : (3'b100));
|
||
|
|
assign _zz_203_ = _zz_113_[2 : 2];
|
||
|
|
assign _zz_204_ = _zz_113_[4 : 4];
|
||
|
|
assign _zz_205_ = _zz_113_[5 : 5];
|
||
|
|
assign _zz_206_ = _zz_113_[6 : 6];
|
||
|
|
assign _zz_207_ = _zz_113_[9 : 9];
|
||
|
|
assign _zz_208_ = _zz_113_[10 : 10];
|
||
|
|
assign _zz_209_ = _zz_113_[13 : 13];
|
||
|
|
assign _zz_210_ = _zz_113_[20 : 20];
|
||
|
|
assign _zz_211_ = _zz_113_[21 : 21];
|
||
|
|
assign _zz_212_ = _zz_113_[24 : 24];
|
||
|
|
assign _zz_213_ = _zz_113_[25 : 25];
|
||
|
|
assign _zz_214_ = execute_SRC_LESS;
|
||
|
|
assign _zz_215_ = (3'b100);
|
||
|
|
assign _zz_216_ = execute_INSTRUCTION[19 : 15];
|
||
|
|
assign _zz_217_ = execute_INSTRUCTION[31 : 20];
|
||
|
|
assign _zz_218_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
|
||
|
|
assign _zz_219_ = ($signed(_zz_220_) + $signed(_zz_223_));
|
||
|
|
assign _zz_220_ = ($signed(_zz_221_) + $signed(_zz_222_));
|
||
|
|
assign _zz_221_ = execute_SRC1;
|
||
|
|
assign _zz_222_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
|
||
|
|
assign _zz_223_ = (execute_SRC_USE_SUB_LESS ? _zz_224_ : _zz_225_);
|
||
|
|
assign _zz_224_ = (32'b00000000000000000000000000000001);
|
||
|
|
assign _zz_225_ = (32'b00000000000000000000000000000000);
|
||
|
|
assign _zz_226_ = (_zz_227_ >>> 1);
|
||
|
|
assign _zz_227_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput};
|
||
|
|
assign _zz_228_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
|
||
|
|
assign _zz_229_ = execute_INSTRUCTION[31 : 20];
|
||
|
|
assign _zz_230_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
|
||
|
|
assign _zz_231_ = (_zz_152_ & (~ _zz_232_));
|
||
|
|
assign _zz_232_ = (_zz_152_ - (2'b01));
|
||
|
|
assign _zz_233_ = (_zz_154_ & (~ _zz_234_));
|
||
|
|
assign _zz_234_ = (_zz_154_ - (2'b01));
|
||
|
|
assign _zz_235_ = execute_CsrPlugin_writeData[7 : 7];
|
||
|
|
assign _zz_236_ = execute_CsrPlugin_writeData[3 : 3];
|
||
|
|
assign _zz_237_ = execute_CsrPlugin_writeData[3 : 3];
|
||
|
|
assign _zz_238_ = execute_CsrPlugin_writeData[11 : 11];
|
||
|
|
assign _zz_239_ = execute_CsrPlugin_writeData[7 : 7];
|
||
|
|
assign _zz_240_ = execute_CsrPlugin_writeData[3 : 3];
|
||
|
|
assign _zz_241_ = ({3'd0,_zz_160_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]);
|
||
|
|
assign _zz_242_ = 1'b1;
|
||
|
|
assign _zz_243_ = 1'b1;
|
||
|
|
assign _zz_244_ = {_zz_94_,_zz_93_};
|
||
|
|
assign _zz_245_ = (32'b00000000000000000000000000010000);
|
||
|
|
assign _zz_246_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000));
|
||
|
|
assign _zz_247_ = (32'b00000000000000000000000001010000);
|
||
|
|
assign _zz_248_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000));
|
||
|
|
assign _zz_249_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000));
|
||
|
|
assign _zz_250_ = (1'b0);
|
||
|
|
assign _zz_251_ = ({(_zz_254_ == _zz_255_),(_zz_256_ == _zz_257_)} != (2'b00));
|
||
|
|
assign _zz_252_ = ((_zz_258_ == _zz_259_) != (1'b0));
|
||
|
|
assign _zz_253_ = {(_zz_260_ != (1'b0)),{(_zz_261_ != _zz_262_),{_zz_263_,{_zz_264_,_zz_265_}}}};
|
||
|
|
assign _zz_254_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100));
|
||
|
|
assign _zz_255_ = (32'b00000000000000000000000000100100);
|
||
|
|
assign _zz_256_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010100));
|
||
|
|
assign _zz_257_ = (32'b00000000000000000001000000010000);
|
||
|
|
assign _zz_258_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000));
|
||
|
|
assign _zz_259_ = (32'b00000000000000000001000000000000);
|
||
|
|
assign _zz_260_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000));
|
||
|
|
assign _zz_261_ = {_zz_115_,(_zz_266_ == _zz_267_)};
|
||
|
|
assign _zz_262_ = (2'b00);
|
||
|
|
assign _zz_263_ = ((_zz_268_ == _zz_269_) != (1'b0));
|
||
|
|
assign _zz_264_ = ({_zz_270_,_zz_271_} != (2'b00));
|
||
|
|
assign _zz_265_ = {(_zz_272_ != _zz_273_),{_zz_274_,{_zz_275_,_zz_276_}}};
|
||
|
|
assign _zz_266_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011100));
|
||
|
|
assign _zz_267_ = (32'b00000000000000000000000000000100);
|
||
|
|
assign _zz_268_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000));
|
||
|
|
assign _zz_269_ = (32'b00000000000000000000000001000000);
|
||
|
|
assign _zz_270_ = ((decode_INSTRUCTION & _zz_277_) == (32'b00000000000000000110000000010000));
|
||
|
|
assign _zz_271_ = ((decode_INSTRUCTION & _zz_278_) == (32'b00000000000000000100000000010000));
|
||
|
|
assign _zz_272_ = ((decode_INSTRUCTION & _zz_279_) == (32'b00000000000000000010000000010000));
|
||
|
|
assign _zz_273_ = (1'b0);
|
||
|
|
assign _zz_274_ = ({_zz_280_,{_zz_281_,_zz_282_}} != (4'b0000));
|
||
|
|
assign _zz_275_ = ({_zz_283_,_zz_284_} != (2'b00));
|
||
|
|
assign _zz_276_ = {(_zz_285_ != _zz_286_),{_zz_287_,{_zz_288_,_zz_289_}}};
|
||
|
|
assign _zz_277_ = (32'b00000000000000000110000000010100);
|
||
|
|
assign _zz_278_ = (32'b00000000000000000101000000010100);
|
||
|
|
assign _zz_279_ = (32'b00000000000000000110000000010100);
|
||
|
|
assign _zz_280_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000000));
|
||
|
|
assign _zz_281_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000000000000000000));
|
||
|
|
assign _zz_282_ = {(_zz_291_ == _zz_292_),(_zz_293_ == _zz_294_)};
|
||
|
|
assign _zz_283_ = _zz_117_;
|
||
|
|
assign _zz_284_ = ((decode_INSTRUCTION & _zz_295_) == (32'b00000000000000000000000000100000));
|
||
|
|
assign _zz_285_ = {_zz_117_,(_zz_296_ == _zz_297_)};
|
||
|
|
assign _zz_286_ = (2'b00);
|
||
|
|
assign _zz_287_ = ({_zz_298_,_zz_299_} != (2'b00));
|
||
|
|
assign _zz_288_ = ({_zz_300_,_zz_301_} != (2'b00));
|
||
|
|
assign _zz_289_ = {(_zz_302_ != _zz_303_),{_zz_304_,{_zz_305_,_zz_306_}}};
|
||
|
|
assign _zz_290_ = (32'b00000000000000000000000000011000);
|
||
|
|
assign _zz_291_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100));
|
||
|
|
assign _zz_292_ = (32'b00000000000000000010000000000000);
|
||
|
|
assign _zz_293_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100));
|
||
|
|
assign _zz_294_ = (32'b00000000000000000001000000000000);
|
||
|
|
assign _zz_295_ = (32'b00000000000000000000000001110000);
|
||
|
|
assign _zz_296_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000));
|
||
|
|
assign _zz_297_ = (32'b00000000000000000000000000000000);
|
||
|
|
assign _zz_298_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000));
|
||
|
|
assign _zz_299_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000));
|
||
|
|
assign _zz_300_ = ((decode_INSTRUCTION & _zz_307_) == (32'b00000000000000000001000001010000));
|
||
|
|
assign _zz_301_ = ((decode_INSTRUCTION & _zz_308_) == (32'b00000000000000000010000001010000));
|
||
|
|
assign _zz_302_ = {(_zz_309_ == _zz_310_),_zz_116_};
|
||
|
|
assign _zz_303_ = (2'b00);
|
||
|
|
assign _zz_304_ = ({_zz_311_,_zz_116_} != (2'b00));
|
||
|
|
assign _zz_305_ = (_zz_312_ != (1'b0));
|
||
|
|
assign _zz_306_ = {(_zz_313_ != _zz_314_),{_zz_315_,{_zz_316_,_zz_317_}}};
|
||
|
|
assign _zz_307_ = (32'b00000000000000000001000001010000);
|
||
|
|
assign _zz_308_ = (32'b00000000000000000010000001010000);
|
||
|
|
assign _zz_309_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100));
|
||
|
|
assign _zz_310_ = (32'b00000000000000000000000000000100);
|
||
|
|
assign _zz_311_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100));
|
||
|
|
assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000));
|
||
|
|
assign _zz_313_ = {(_zz_318_ == _zz_319_),(_zz_320_ == _zz_321_)};
|
||
|
|
assign _zz_314_ = (2'b00);
|
||
|
|
assign _zz_315_ = ({_zz_322_,{_zz_323_,_zz_324_}} != (3'b000));
|
||
|
|
assign _zz_316_ = ({_zz_325_,_zz_326_} != (3'b000));
|
||
|
|
assign _zz_317_ = {(_zz_327_ != _zz_328_),{_zz_329_,_zz_330_}};
|
||
|
|
assign _zz_318_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100));
|
||
|
|
assign _zz_319_ = (32'b00000000000000000000000000100000);
|
||
|
|
assign _zz_320_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100));
|
||
|
|
assign _zz_321_ = (32'b00000000000000000000000000100000);
|
||
|
|
assign _zz_322_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000));
|
||
|
|
assign _zz_323_ = ((decode_INSTRUCTION & _zz_331_) == (32'b00000000000000000010000000010000));
|
||
|
|
assign _zz_324_ = ((decode_INSTRUCTION & _zz_332_) == (32'b01000000000000000000000000110000));
|
||
|
|
assign _zz_325_ = ((decode_INSTRUCTION & _zz_333_) == (32'b00000000000000000000000001000000));
|
||
|
|
assign _zz_326_ = {(_zz_334_ == _zz_335_),(_zz_336_ == _zz_337_)};
|
||
|
|
assign _zz_327_ = {_zz_115_,{_zz_338_,{_zz_339_,_zz_340_}}};
|
||
|
|
assign _zz_328_ = (6'b000000);
|
||
|
|
assign _zz_329_ = ((_zz_341_ == _zz_342_) != (1'b0));
|
||
|
|
assign _zz_330_ = ({_zz_343_,_zz_344_} != (2'b00));
|
||
|
|
assign _zz_331_ = (32'b00000000000000000010000000010100);
|
||
|
|
assign _zz_332_ = (32'b01000000000000000100000000110100);
|
||
|
|
assign _zz_333_ = (32'b00000000000000000000000001010000);
|
||
|
|
assign _zz_334_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000));
|
||
|
|
assign _zz_335_ = (32'b00000000000000000000000000000000);
|
||
|
|
assign _zz_336_ = (decode_INSTRUCTION & (32'b00000000010000000011000001000000));
|
||
|
|
assign _zz_337_ = (32'b00000000000000000000000001000000);
|
||
|
|
assign _zz_338_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000001000000010000));
|
||
|
|
assign _zz_339_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000));
|
||
|
|
assign _zz_340_ = {_zz_114_,{((decode_INSTRUCTION & (32'b00000000000000000000000000001100)) == (32'b00000000000000000000000000000100)),((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000))}};
|
||
|
|
assign _zz_341_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100));
|
||
|
|
assign _zz_342_ = (32'b00000000000000000101000000010000);
|
||
|
|
assign _zz_343_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000));
|
||
|
|
assign _zz_344_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000));
|
||
|
|
assign _zz_345_ = (32'b00000000000000000001000001111111);
|
||
|
|
assign _zz_346_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111));
|
||
|
|
assign _zz_347_ = (32'b00000000000000000010000001110011);
|
||
|
|
assign _zz_348_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011));
|
||
|
|
assign _zz_349_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011));
|
||
|
|
assign _zz_350_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_351_) == (32'b00000000000000000000000000000011)),{(_zz_352_ == _zz_353_),{_zz_354_,{_zz_355_,_zz_356_}}}}}};
|
||
|
|
assign _zz_351_ = (32'b00000000000000000101000001011111);
|
||
|
|
assign _zz_352_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011));
|
||
|
|
assign _zz_353_ = (32'b00000000000000000000000001100011);
|
||
|
|
assign _zz_354_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111));
|
||
|
|
assign _zz_355_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011));
|
||
|
|
assign _zz_356_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_357_) == (32'b00000000000000000101000000110011)),{(_zz_358_ == _zz_359_),{_zz_360_,{_zz_361_,_zz_362_}}}}}};
|
||
|
|
assign _zz_357_ = (32'b10111110000000000111000001111111);
|
||
|
|
assign _zz_358_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111));
|
||
|
|
assign _zz_359_ = (32'b00000000000000000000000000110011);
|
||
|
|
assign _zz_360_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011));
|
||
|
|
assign _zz_361_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011));
|
||
|
|
assign _zz_362_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011));
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
if(_zz_50_) begin
|
||
|
|
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
if(_zz_242_) begin
|
||
|
|
_zz_161_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
if(_zz_243_) begin
|
||
|
|
_zz_162_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c (
|
||
|
|
.io_push_valid(iBus_rsp_takeWhen_valid),
|
||
|
|
.io_push_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready),
|
||
|
|
.io_push_payload_error(iBus_rsp_takeWhen_payload_error),
|
||
|
|
.io_push_payload_inst(iBus_rsp_takeWhen_payload_inst),
|
||
|
|
.io_pop_valid(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid),
|
||
|
|
.io_pop_ready(IBusSimplePlugin_rspJoin_rspBufferOutput_ready),
|
||
|
|
.io_pop_payload_error(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error),
|
||
|
|
.io_pop_payload_inst(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst),
|
||
|
|
.io_flush(IBusSimplePlugin_fetcherflushIt),
|
||
|
|
.io_occupancy(IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy),
|
||
|
|
.clk(clk),
|
||
|
|
.reset(reset)
|
||
|
|
);
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_244_)
|
||
|
|
2'b00 : begin
|
||
|
|
_zz_163_ = CsrPlugin_jumpInterface_payload;
|
||
|
|
end
|
||
|
|
2'b01 : begin
|
||
|
|
_zz_163_ = DBusSimplePlugin_redoBranch_payload;
|
||
|
|
end
|
||
|
|
2'b10 : begin
|
||
|
|
_zz_163_ = BranchPlugin_jumpInterface_payload;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_163_ = IBusSimplePlugin_redoBranch_payload;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
`ifndef SYNTHESIS
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_SRC2_CTRL)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC ";
|
||
|
|
default : decode_SRC2_CTRL_string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_1_)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_1__string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_1__string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_1__string = "PC ";
|
||
|
|
default : _zz_1__string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_2_)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_2__string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_2__string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_2__string = "PC ";
|
||
|
|
default : _zz_2__string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_3_)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_3__string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_3__string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_3__string = "PC ";
|
||
|
|
default : _zz_3__string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_4_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL";
|
||
|
|
default : _zz_4__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_5_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL";
|
||
|
|
default : _zz_5__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_6_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL";
|
||
|
|
default : _zz_6__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_7_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL";
|
||
|
|
default : _zz_7__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_ENV_CTRL)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL";
|
||
|
|
default : decode_ENV_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_8_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_8__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_8__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_8__string = "ECALL";
|
||
|
|
default : _zz_8__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_9_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_9__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_9__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_9__string = "ECALL";
|
||
|
|
default : _zz_9__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_10_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_10__string = "ECALL";
|
||
|
|
default : _zz_10__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_SRC1_CTRL)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 ";
|
||
|
|
default : decode_SRC1_CTRL_string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_11_)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_11__string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_11__string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_11__string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_11__string = "URS1 ";
|
||
|
|
default : _zz_11__string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_12_)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_12__string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_12__string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_12__string = "URS1 ";
|
||
|
|
default : _zz_12__string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_13_)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_13__string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_13__string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_13__string = "URS1 ";
|
||
|
|
default : _zz_13__string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_BRANCH_CTRL)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR";
|
||
|
|
default : decode_BRANCH_CTRL_string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_14_)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR";
|
||
|
|
default : _zz_14__string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_15_)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR";
|
||
|
|
default : _zz_15__string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_16_)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_16__string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_16__string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_16__string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_16__string = "JALR";
|
||
|
|
default : _zz_16__string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_ALU_CTRL)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
|
||
|
|
default : decode_ALU_CTRL_string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_17_)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17__string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17__string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_17__string = "BITWISE ";
|
||
|
|
default : _zz_17__string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_18_)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18__string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18__string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_18__string = "BITWISE ";
|
||
|
|
default : _zz_18__string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_19_)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE ";
|
||
|
|
default : _zz_19__string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_SHIFT_CTRL)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
|
||
|
|
default : decode_SHIFT_CTRL_string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_20_)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1 ";
|
||
|
|
default : _zz_20__string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_21_)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1 ";
|
||
|
|
default : _zz_21__string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_22_)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 ";
|
||
|
|
default : _zz_22__string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_ALU_BITWISE_CTRL)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
|
||
|
|
default : decode_ALU_BITWISE_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_23_)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_23__string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_23__string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_23__string = "AND_1";
|
||
|
|
default : _zz_23__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_24_)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_24__string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_24__string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_24__string = "AND_1";
|
||
|
|
default : _zz_24__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_25_)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_25__string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_25__string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_25__string = "AND_1";
|
||
|
|
default : _zz_25__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(memory_ENV_CTRL)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL";
|
||
|
|
default : memory_ENV_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_26_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL";
|
||
|
|
default : _zz_26__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_ENV_CTRL)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL";
|
||
|
|
default : execute_ENV_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_27_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_27__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_27__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_27__string = "ECALL";
|
||
|
|
default : _zz_27__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(writeBack_ENV_CTRL)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL";
|
||
|
|
default : writeBack_ENV_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_30_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_30__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_30__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_30__string = "ECALL";
|
||
|
|
default : _zz_30__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_BRANCH_CTRL)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR";
|
||
|
|
default : execute_BRANCH_CTRL_string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_32_)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_32__string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_32__string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_32__string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_32__string = "JALR";
|
||
|
|
default : _zz_32__string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_SHIFT_CTRL)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
|
||
|
|
default : execute_SHIFT_CTRL_string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_35_)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35__string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35__string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35__string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35__string = "SRA_1 ";
|
||
|
|
default : _zz_35__string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_SRC2_CTRL)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC ";
|
||
|
|
default : execute_SRC2_CTRL_string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_40_)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_40__string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_40__string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_40__string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_40__string = "PC ";
|
||
|
|
default : _zz_40__string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_SRC1_CTRL)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 ";
|
||
|
|
default : execute_SRC1_CTRL_string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_42_)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_42__string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_42__string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_42__string = "URS1 ";
|
||
|
|
default : _zz_42__string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_ALU_CTRL)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
|
||
|
|
default : execute_ALU_CTRL_string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_45_)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45__string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45__string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_45__string = "BITWISE ";
|
||
|
|
default : _zz_45__string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_ALU_BITWISE_CTRL)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
|
||
|
|
default : execute_ALU_BITWISE_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_47_)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_47__string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_47__string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_47__string = "AND_1";
|
||
|
|
default : _zz_47__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_55_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_55__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_55__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_55__string = "ECALL";
|
||
|
|
default : _zz_55__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_58_)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1";
|
||
|
|
default : _zz_58__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_59_)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_59__string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_59__string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_59__string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_59__string = "JALR";
|
||
|
|
default : _zz_59__string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_60_)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_60__string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_60__string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_60__string = "BITWISE ";
|
||
|
|
default : _zz_60__string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_62_)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_62__string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_62__string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_62__string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_62__string = "PC ";
|
||
|
|
default : _zz_62__string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_65_)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_65__string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_65__string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_65__string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_65__string = "URS1 ";
|
||
|
|
default : _zz_65__string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_70_)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_70__string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_70__string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_70__string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_70__string = "SRA_1 ";
|
||
|
|
default : _zz_70__string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_118_)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_118__string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_118__string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_118__string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_118__string = "SRA_1 ";
|
||
|
|
default : _zz_118__string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_119_)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_119__string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_119__string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_119__string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_119__string = "URS1 ";
|
||
|
|
default : _zz_119__string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_120_)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_120__string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_120__string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_120__string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_120__string = "PC ";
|
||
|
|
default : _zz_120__string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_121_)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_121__string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_121__string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_121__string = "BITWISE ";
|
||
|
|
default : _zz_121__string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_122_)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_122__string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_122__string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_122__string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_122__string = "JALR";
|
||
|
|
default : _zz_122__string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_123_)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_123__string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_123__string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_123__string = "AND_1";
|
||
|
|
default : _zz_123__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_124_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_124__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_124__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_124__string = "ECALL";
|
||
|
|
default : _zz_124__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_ALU_BITWISE_CTRL)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
|
||
|
|
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_SHIFT_CTRL)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
|
||
|
|
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_ALU_CTRL)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
|
||
|
|
default : decode_to_execute_ALU_CTRL_string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_BRANCH_CTRL)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
|
||
|
|
default : decode_to_execute_BRANCH_CTRL_string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_SRC1_CTRL)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
|
||
|
|
default : decode_to_execute_SRC1_CTRL_string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_ENV_CTRL)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
|
||
|
|
default : decode_to_execute_ENV_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_to_memory_ENV_CTRL)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
|
||
|
|
default : execute_to_memory_ENV_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(memory_to_writeBack_ENV_CTRL)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
|
||
|
|
default : memory_to_writeBack_ENV_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_SRC2_CTRL)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
|
||
|
|
default : decode_to_execute_SRC2_CTRL_string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
`endif
|
||
|
|
|
||
|
|
assign decode_RS1 = _zz_52_;
|
||
|
|
assign execute_BRANCH_DO = _zz_33_;
|
||
|
|
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
|
||
|
|
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_54_;
|
||
|
|
assign decode_SRC2_FORCE_ZERO = _zz_44_;
|
||
|
|
assign decode_SRC2_CTRL = _zz_1_;
|
||
|
|
assign _zz_2_ = _zz_3_;
|
||
|
|
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
|
||
|
|
assign execute_REGFILE_WRITE_DATA = _zz_46_;
|
||
|
|
assign decode_CSR_WRITE_OPCODE = _zz_29_;
|
||
|
|
assign execute_BRANCH_CALC = _zz_31_;
|
||
|
|
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
|
||
|
|
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
|
||
|
|
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
|
||
|
|
assign decode_FORMAL_PC_NEXT = _zz_86_;
|
||
|
|
assign decode_SRC_LESS_UNSIGNED = _zz_63_;
|
||
|
|
assign decode_MEMORY_STORE = _zz_56_;
|
||
|
|
assign memory_MEMORY_READ_DATA = _zz_73_;
|
||
|
|
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_53_;
|
||
|
|
assign decode_IS_CSR = _zz_64_;
|
||
|
|
assign decode_RS2 = _zz_51_;
|
||
|
|
assign _zz_4_ = _zz_5_;
|
||
|
|
assign _zz_6_ = _zz_7_;
|
||
|
|
assign decode_ENV_CTRL = _zz_8_;
|
||
|
|
assign _zz_9_ = _zz_10_;
|
||
|
|
assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW;
|
||
|
|
assign execute_MEMORY_ADDRESS_LOW = _zz_82_;
|
||
|
|
assign decode_SRC1_CTRL = _zz_11_;
|
||
|
|
assign _zz_12_ = _zz_13_;
|
||
|
|
assign decode_BRANCH_CTRL = _zz_14_;
|
||
|
|
assign _zz_15_ = _zz_16_;
|
||
|
|
assign decode_ALU_CTRL = _zz_17_;
|
||
|
|
assign _zz_18_ = _zz_19_;
|
||
|
|
assign decode_CSR_READ_OPCODE = _zz_28_;
|
||
|
|
assign decode_SHIFT_CTRL = _zz_20_;
|
||
|
|
assign _zz_21_ = _zz_22_;
|
||
|
|
assign decode_ALU_BITWISE_CTRL = _zz_23_;
|
||
|
|
assign _zz_24_ = _zz_25_;
|
||
|
|
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
|
||
|
|
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
|
||
|
|
assign execute_IS_CSR = decode_to_execute_IS_CSR;
|
||
|
|
assign memory_ENV_CTRL = _zz_26_;
|
||
|
|
assign execute_ENV_CTRL = _zz_27_;
|
||
|
|
assign writeBack_ENV_CTRL = _zz_30_;
|
||
|
|
assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC;
|
||
|
|
assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO;
|
||
|
|
assign execute_PC = decode_to_execute_PC;
|
||
|
|
assign execute_RS1 = decode_to_execute_RS1;
|
||
|
|
assign execute_BRANCH_CTRL = _zz_32_;
|
||
|
|
assign decode_RS2_USE = _zz_67_;
|
||
|
|
assign decode_RS1_USE = _zz_61_;
|
||
|
|
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
|
||
|
|
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
|
||
|
|
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
|
||
|
|
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
|
||
|
|
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
|
||
|
|
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_34_ = execute_REGFILE_WRITE_DATA;
|
||
|
|
if(_zz_164_)begin
|
||
|
|
_zz_34_ = _zz_133_;
|
||
|
|
end
|
||
|
|
if(_zz_165_)begin
|
||
|
|
_zz_34_ = execute_CsrPlugin_readData;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_SHIFT_CTRL = _zz_35_;
|
||
|
|
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
|
||
|
|
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
|
||
|
|
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
|
||
|
|
assign _zz_39_ = execute_PC;
|
||
|
|
assign execute_SRC2_CTRL = _zz_40_;
|
||
|
|
assign execute_SRC1_CTRL = _zz_42_;
|
||
|
|
assign decode_SRC_USE_SUB_LESS = _zz_68_;
|
||
|
|
assign decode_SRC_ADD_ZERO = _zz_57_;
|
||
|
|
assign execute_SRC_ADD_SUB = _zz_38_;
|
||
|
|
assign execute_SRC_LESS = _zz_36_;
|
||
|
|
assign execute_ALU_CTRL = _zz_45_;
|
||
|
|
assign execute_SRC2 = _zz_41_;
|
||
|
|
assign execute_SRC1 = _zz_43_;
|
||
|
|
assign execute_ALU_BITWISE_CTRL = _zz_47_;
|
||
|
|
assign _zz_48_ = writeBack_INSTRUCTION;
|
||
|
|
assign _zz_49_ = writeBack_REGFILE_WRITE_VALID;
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_50_ = 1'b0;
|
||
|
|
if(lastStageRegFileWrite_valid)begin
|
||
|
|
_zz_50_ = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign decode_INSTRUCTION_ANTICIPATED = _zz_89_;
|
||
|
|
always @ (*) begin
|
||
|
|
decode_REGFILE_WRITE_VALID = _zz_69_;
|
||
|
|
if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin
|
||
|
|
decode_REGFILE_WRITE_VALID = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign decode_LEGAL_INSTRUCTION = _zz_71_;
|
||
|
|
assign decode_INSTRUCTION_READY = 1'b1;
|
||
|
|
assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE;
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_72_ = writeBack_REGFILE_WRITE_DATA;
|
||
|
|
if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin
|
||
|
|
_zz_72_ = writeBack_DBusSimplePlugin_rspFormated;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
|
||
|
|
assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW;
|
||
|
|
assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA;
|
||
|
|
assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT;
|
||
|
|
assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress;
|
||
|
|
assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess;
|
||
|
|
assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead;
|
||
|
|
assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite;
|
||
|
|
assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute;
|
||
|
|
assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception;
|
||
|
|
assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling;
|
||
|
|
assign memory_PC = execute_to_memory_PC;
|
||
|
|
assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT;
|
||
|
|
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
|
||
|
|
assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE;
|
||
|
|
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
|
||
|
|
assign execute_MMU_FAULT = _zz_81_;
|
||
|
|
assign execute_MMU_RSP_physicalAddress = _zz_74_;
|
||
|
|
assign execute_MMU_RSP_isIoAccess = _zz_75_;
|
||
|
|
assign execute_MMU_RSP_allowRead = _zz_76_;
|
||
|
|
assign execute_MMU_RSP_allowWrite = _zz_77_;
|
||
|
|
assign execute_MMU_RSP_allowExecute = _zz_78_;
|
||
|
|
assign execute_MMU_RSP_exception = _zz_79_;
|
||
|
|
assign execute_MMU_RSP_refilling = _zz_80_;
|
||
|
|
assign execute_SRC_ADD = _zz_37_;
|
||
|
|
assign execute_RS2 = decode_to_execute_RS2;
|
||
|
|
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
|
||
|
|
assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE;
|
||
|
|
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
|
||
|
|
assign execute_ALIGNEMENT_FAULT = _zz_83_;
|
||
|
|
assign decode_MEMORY_ENABLE = _zz_66_;
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_84_ = memory_FORMAL_PC_NEXT;
|
||
|
|
if(DBusSimplePlugin_redoBranch_valid)begin
|
||
|
|
_zz_84_ = DBusSimplePlugin_redoBranch_payload;
|
||
|
|
end
|
||
|
|
if(BranchPlugin_jumpInterface_valid)begin
|
||
|
|
_zz_84_ = BranchPlugin_jumpInterface_payload;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_85_ = decode_FORMAL_PC_NEXT;
|
||
|
|
if(IBusSimplePlugin_redoBranch_valid)begin
|
||
|
|
_zz_85_ = IBusSimplePlugin_redoBranch_payload;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign decode_PC = _zz_88_;
|
||
|
|
assign decode_INSTRUCTION = _zz_87_;
|
||
|
|
assign writeBack_PC = memory_to_writeBack_PC;
|
||
|
|
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
|
||
|
|
always @ (*) begin
|
||
|
|
decode_arbitration_haltItself = 1'b0;
|
||
|
|
if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin
|
||
|
|
decode_arbitration_haltItself = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
decode_arbitration_haltByOther = 1'b0;
|
||
|
|
if((decode_arbitration_isValid && (_zz_134_ || _zz_135_)))begin
|
||
|
|
decode_arbitration_haltByOther = 1'b1;
|
||
|
|
end
|
||
|
|
if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin
|
||
|
|
decode_arbitration_haltByOther = decode_arbitration_isValid;
|
||
|
|
end
|
||
|
|
if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin
|
||
|
|
decode_arbitration_haltByOther = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
decode_arbitration_removeIt = 1'b0;
|
||
|
|
if(_zz_166_)begin
|
||
|
|
decode_arbitration_removeIt = 1'b1;
|
||
|
|
end
|
||
|
|
if(decode_arbitration_isFlushed)begin
|
||
|
|
decode_arbitration_removeIt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
decode_arbitration_flushIt = 1'b0;
|
||
|
|
if(IBusSimplePlugin_redoBranch_valid)begin
|
||
|
|
decode_arbitration_flushIt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
decode_arbitration_flushNext = 1'b0;
|
||
|
|
if(IBusSimplePlugin_redoBranch_valid)begin
|
||
|
|
decode_arbitration_flushNext = 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_166_)begin
|
||
|
|
decode_arbitration_flushNext = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
execute_arbitration_haltItself = 1'b0;
|
||
|
|
if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_106_)))begin
|
||
|
|
execute_arbitration_haltItself = 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_164_)begin
|
||
|
|
if(_zz_167_)begin
|
||
|
|
if(! execute_LightShifterPlugin_done) begin
|
||
|
|
execute_arbitration_haltItself = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(_zz_165_)begin
|
||
|
|
if(execute_CsrPlugin_blockedBySideEffects)begin
|
||
|
|
execute_arbitration_haltItself = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_arbitration_haltByOther = 1'b0;
|
||
|
|
always @ (*) begin
|
||
|
|
execute_arbitration_removeIt = 1'b0;
|
||
|
|
if(CsrPlugin_selfException_valid)begin
|
||
|
|
execute_arbitration_removeIt = 1'b1;
|
||
|
|
end
|
||
|
|
if(execute_arbitration_isFlushed)begin
|
||
|
|
execute_arbitration_removeIt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_arbitration_flushIt = 1'b0;
|
||
|
|
always @ (*) begin
|
||
|
|
execute_arbitration_flushNext = 1'b0;
|
||
|
|
if(CsrPlugin_selfException_valid)begin
|
||
|
|
execute_arbitration_flushNext = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
memory_arbitration_haltItself = 1'b0;
|
||
|
|
if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin
|
||
|
|
memory_arbitration_haltItself = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign memory_arbitration_haltByOther = 1'b0;
|
||
|
|
always @ (*) begin
|
||
|
|
memory_arbitration_removeIt = 1'b0;
|
||
|
|
if(_zz_168_)begin
|
||
|
|
memory_arbitration_removeIt = 1'b1;
|
||
|
|
end
|
||
|
|
if(memory_arbitration_isFlushed)begin
|
||
|
|
memory_arbitration_removeIt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
memory_arbitration_flushIt = 1'b0;
|
||
|
|
if(DBusSimplePlugin_redoBranch_valid)begin
|
||
|
|
memory_arbitration_flushIt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
memory_arbitration_flushNext = 1'b0;
|
||
|
|
if(DBusSimplePlugin_redoBranch_valid)begin
|
||
|
|
memory_arbitration_flushNext = 1'b1;
|
||
|
|
end
|
||
|
|
if(BranchPlugin_jumpInterface_valid)begin
|
||
|
|
memory_arbitration_flushNext = 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_168_)begin
|
||
|
|
memory_arbitration_flushNext = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign writeBack_arbitration_haltItself = 1'b0;
|
||
|
|
assign writeBack_arbitration_haltByOther = 1'b0;
|
||
|
|
always @ (*) begin
|
||
|
|
writeBack_arbitration_removeIt = 1'b0;
|
||
|
|
if(writeBack_arbitration_isFlushed)begin
|
||
|
|
writeBack_arbitration_removeIt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign writeBack_arbitration_flushIt = 1'b0;
|
||
|
|
always @ (*) begin
|
||
|
|
writeBack_arbitration_flushNext = 1'b0;
|
||
|
|
if(_zz_169_)begin
|
||
|
|
writeBack_arbitration_flushNext = 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_170_)begin
|
||
|
|
writeBack_arbitration_flushNext = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign lastStageInstruction = writeBack_INSTRUCTION;
|
||
|
|
assign lastStagePc = writeBack_PC;
|
||
|
|
assign lastStageIsValid = writeBack_arbitration_isValid;
|
||
|
|
assign lastStageIsFiring = writeBack_arbitration_isFiring;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_fetcherHalt = 1'b0;
|
||
|
|
if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin
|
||
|
|
IBusSimplePlugin_fetcherHalt = 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_169_)begin
|
||
|
|
IBusSimplePlugin_fetcherHalt = 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_170_)begin
|
||
|
|
IBusSimplePlugin_fetcherHalt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_fetcherflushIt = 1'b0;
|
||
|
|
if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin
|
||
|
|
IBusSimplePlugin_fetcherflushIt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_incomingInstruction = 1'b0;
|
||
|
|
if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin
|
||
|
|
IBusSimplePlugin_incomingInstruction = 1'b1;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_injector_decodeInput_valid)begin
|
||
|
|
IBusSimplePlugin_incomingInstruction = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_jumpInterface_valid = 1'b0;
|
||
|
|
if(_zz_169_)begin
|
||
|
|
CsrPlugin_jumpInterface_valid = 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_170_)begin
|
||
|
|
CsrPlugin_jumpInterface_valid = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
||
|
|
if(_zz_169_)begin
|
||
|
|
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)};
|
||
|
|
end
|
||
|
|
if(_zz_170_)begin
|
||
|
|
case(_zz_171_)
|
||
|
|
2'b11 : begin
|
||
|
|
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign CsrPlugin_forceMachineWire = 1'b0;
|
||
|
|
assign CsrPlugin_allowInterrupts = 1'b1;
|
||
|
|
assign CsrPlugin_allowException = 1'b1;
|
||
|
|
assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusSimplePlugin_redoBranch_valid}}} != (4'b0000));
|
||
|
|
assign _zz_90_ = {IBusSimplePlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}};
|
||
|
|
assign _zz_91_ = (_zz_90_ & (~ _zz_190_));
|
||
|
|
assign _zz_92_ = _zz_91_[3];
|
||
|
|
assign _zz_93_ = (_zz_91_[1] || _zz_92_);
|
||
|
|
assign _zz_94_ = (_zz_91_[2] || _zz_92_);
|
||
|
|
assign IBusSimplePlugin_jump_pcLoad_payload = _zz_163_;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_fetchPc_corrected = 1'b0;
|
||
|
|
if(IBusSimplePlugin_jump_pcLoad_valid)begin
|
||
|
|
IBusSimplePlugin_fetchPc_corrected = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0;
|
||
|
|
if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin
|
||
|
|
IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_192_);
|
||
|
|
if(IBusSimplePlugin_jump_pcLoad_valid)begin
|
||
|
|
IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload;
|
||
|
|
end
|
||
|
|
IBusSimplePlugin_fetchPc_pc[0] = 1'b0;
|
||
|
|
IBusSimplePlugin_fetchPc_pc[1] = 1'b0;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted);
|
||
|
|
assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid;
|
||
|
|
if(IBusSimplePlugin_mmuBus_busy)begin
|
||
|
|
IBusSimplePlugin_iBusRsp_stages_0_input_valid = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready;
|
||
|
|
assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload;
|
||
|
|
assign IBusSimplePlugin_iBusRsp_stages_0_inputSample = 1'b1;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0;
|
||
|
|
if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmd_valid) || (! IBusSimplePlugin_cmd_ready))))begin
|
||
|
|
IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_172_)begin
|
||
|
|
IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_95_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt);
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_95_);
|
||
|
|
if(IBusSimplePlugin_mmuBus_busy)begin
|
||
|
|
IBusSimplePlugin_iBusRsp_stages_0_input_ready = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_95_);
|
||
|
|
assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload;
|
||
|
|
assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0;
|
||
|
|
assign _zz_96_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt);
|
||
|
|
assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_96_);
|
||
|
|
assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_96_);
|
||
|
|
assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload;
|
||
|
|
assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_97_;
|
||
|
|
assign _zz_97_ = ((1'b0 && (! _zz_98_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready);
|
||
|
|
assign _zz_98_ = _zz_99_;
|
||
|
|
assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_98_;
|
||
|
|
assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_iBusRsp_readyForError = 1'b1;
|
||
|
|
if(IBusSimplePlugin_injector_decodeInput_valid)begin
|
||
|
|
IBusSimplePlugin_iBusRsp_readyForError = 1'b0;
|
||
|
|
end
|
||
|
|
if((! IBusSimplePlugin_pcValids_0))begin
|
||
|
|
IBusSimplePlugin_iBusRsp_readyForError = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign IBusSimplePlugin_iBusRsp_inputBeforeStage_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready);
|
||
|
|
assign IBusSimplePlugin_injector_decodeInput_valid = _zz_100_;
|
||
|
|
assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_101_;
|
||
|
|
assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_102_;
|
||
|
|
assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_103_;
|
||
|
|
assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_104_;
|
||
|
|
assign _zz_89_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst);
|
||
|
|
assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1;
|
||
|
|
assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2;
|
||
|
|
assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3;
|
||
|
|
assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4;
|
||
|
|
assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck);
|
||
|
|
assign decode_arbitration_isValid = (IBusSimplePlugin_injector_decodeInput_valid && (! IBusSimplePlugin_injector_decodeRemoved));
|
||
|
|
assign _zz_88_ = IBusSimplePlugin_injector_decodeInput_payload_pc;
|
||
|
|
assign _zz_87_ = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
|
||
|
|
assign _zz_86_ = (decode_PC + (32'b00000000000000000000000000000100));
|
||
|
|
assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid;
|
||
|
|
assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready;
|
||
|
|
assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc;
|
||
|
|
assign IBusSimplePlugin_pendingCmdNext = (_zz_193_ - _zz_197_);
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_cmd_valid = ((IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) && (IBusSimplePlugin_pendingCmd != (3'b111)));
|
||
|
|
if(_zz_172_)begin
|
||
|
|
IBusSimplePlugin_cmd_valid = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign IBusSimplePlugin_mmuBus_cmd_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid;
|
||
|
|
assign IBusSimplePlugin_mmuBus_cmd_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload;
|
||
|
|
assign IBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0;
|
||
|
|
assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_fetcherflushIt);
|
||
|
|
assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],(2'b00)};
|
||
|
|
assign iBus_rsp_takeWhen_valid = (iBus_rsp_valid && (! (IBusSimplePlugin_rspJoin_discardCounter != (3'b000))));
|
||
|
|
assign iBus_rsp_takeWhen_payload_error = iBus_rsp_payload_error;
|
||
|
|
assign iBus_rsp_takeWhen_payload_inst = iBus_rsp_payload_inst;
|
||
|
|
assign IBusSimplePlugin_rspJoin_rspBufferOutput_valid = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid;
|
||
|
|
assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;
|
||
|
|
assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;
|
||
|
|
assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error;
|
||
|
|
if((! IBusSimplePlugin_rspJoin_rspBufferOutput_valid))begin
|
||
|
|
IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0;
|
||
|
|
if(_zz_173_)begin
|
||
|
|
IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_rspJoin_redoRequired = 1'b0;
|
||
|
|
if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin
|
||
|
|
IBusSimplePlugin_rspJoin_redoRequired = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBufferOutput_valid);
|
||
|
|
assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc;
|
||
|
|
assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error;
|
||
|
|
assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;
|
||
|
|
assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc;
|
||
|
|
assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready);
|
||
|
|
assign IBusSimplePlugin_rspJoin_rspBufferOutput_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready);
|
||
|
|
assign _zz_105_ = (! (IBusSimplePlugin_rspJoin_exceptionDetected || IBusSimplePlugin_rspJoin_redoRequired));
|
||
|
|
assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_inputBeforeStage_ready && _zz_105_);
|
||
|
|
assign IBusSimplePlugin_iBusRsp_inputBeforeStage_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_105_);
|
||
|
|
assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc;
|
||
|
|
assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error;
|
||
|
|
assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst;
|
||
|
|
assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc;
|
||
|
|
assign IBusSimplePlugin_redoBranch_valid = (IBusSimplePlugin_rspJoin_redoRequired && IBusSimplePlugin_iBusRsp_readyForError);
|
||
|
|
assign IBusSimplePlugin_redoBranch_payload = decode_PC;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusSimplePlugin_decodeExceptionPort_payload_code = (4'bxxxx);
|
||
|
|
if(_zz_173_)begin
|
||
|
|
IBusSimplePlugin_decodeExceptionPort_payload_code = (4'b1100);
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],(2'b00)};
|
||
|
|
assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError);
|
||
|
|
assign _zz_106_ = 1'b0;
|
||
|
|
assign _zz_83_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0))));
|
||
|
|
always @ (*) begin
|
||
|
|
execute_DBusSimplePlugin_skipCmd = 1'b0;
|
||
|
|
if(execute_ALIGNEMENT_FAULT)begin
|
||
|
|
execute_DBusSimplePlugin_skipCmd = 1'b1;
|
||
|
|
end
|
||
|
|
if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin
|
||
|
|
execute_DBusSimplePlugin_skipCmd = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_106_));
|
||
|
|
assign dBus_cmd_payload_wr = execute_MEMORY_STORE;
|
||
|
|
assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12];
|
||
|
|
always @ (*) begin
|
||
|
|
case(dBus_cmd_payload_size)
|
||
|
|
2'b00 : begin
|
||
|
|
_zz_107_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
|
||
|
|
end
|
||
|
|
2'b01 : begin
|
||
|
|
_zz_107_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_107_ = execute_RS2[31 : 0];
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign dBus_cmd_payload_data = _zz_107_;
|
||
|
|
assign _zz_82_ = dBus_cmd_payload_address[1 : 0];
|
||
|
|
always @ (*) begin
|
||
|
|
case(dBus_cmd_payload_size)
|
||
|
|
2'b00 : begin
|
||
|
|
_zz_108_ = (4'b0001);
|
||
|
|
end
|
||
|
|
2'b01 : begin
|
||
|
|
_zz_108_ = (4'b0011);
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_108_ = (4'b1111);
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_DBusSimplePlugin_formalMask = (_zz_108_ <<< dBus_cmd_payload_address[1 : 0]);
|
||
|
|
assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
|
||
|
|
assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD;
|
||
|
|
assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0;
|
||
|
|
assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
|
||
|
|
assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress;
|
||
|
|
assign _zz_81_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE)));
|
||
|
|
assign _zz_74_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress;
|
||
|
|
assign _zz_75_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess;
|
||
|
|
assign _zz_76_ = DBusSimplePlugin_mmuBus_rsp_allowRead;
|
||
|
|
assign _zz_77_ = DBusSimplePlugin_mmuBus_rsp_allowWrite;
|
||
|
|
assign _zz_78_ = DBusSimplePlugin_mmuBus_rsp_allowExecute;
|
||
|
|
assign _zz_79_ = DBusSimplePlugin_mmuBus_rsp_exception;
|
||
|
|
assign _zz_80_ = DBusSimplePlugin_mmuBus_rsp_refilling;
|
||
|
|
assign _zz_73_ = dBus_rsp_data;
|
||
|
|
always @ (*) begin
|
||
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
|
||
|
|
if(_zz_174_)begin
|
||
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
|
||
|
|
end
|
||
|
|
if(memory_ALIGNEMENT_FAULT)begin
|
||
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
|
||
|
|
end
|
||
|
|
if(memory_MMU_RSP_refilling)begin
|
||
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
|
||
|
|
end else begin
|
||
|
|
if(memory_MMU_FAULT)begin
|
||
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(_zz_175_)begin
|
||
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx);
|
||
|
|
if(_zz_174_)begin
|
||
|
|
DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101);
|
||
|
|
end
|
||
|
|
if(memory_ALIGNEMENT_FAULT)begin
|
||
|
|
DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_202_};
|
||
|
|
end
|
||
|
|
if(! memory_MMU_RSP_refilling) begin
|
||
|
|
if(memory_MMU_FAULT)begin
|
||
|
|
DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101));
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA;
|
||
|
|
always @ (*) begin
|
||
|
|
DBusSimplePlugin_redoBranch_valid = 1'b0;
|
||
|
|
if(memory_MMU_RSP_refilling)begin
|
||
|
|
DBusSimplePlugin_redoBranch_valid = 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_175_)begin
|
||
|
|
DBusSimplePlugin_redoBranch_valid = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign DBusSimplePlugin_redoBranch_payload = memory_PC;
|
||
|
|
always @ (*) begin
|
||
|
|
writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA;
|
||
|
|
case(writeBack_MEMORY_ADDRESS_LOW)
|
||
|
|
2'b01 : begin
|
||
|
|
writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8];
|
||
|
|
end
|
||
|
|
2'b10 : begin
|
||
|
|
writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16];
|
||
|
|
end
|
||
|
|
2'b11 : begin
|
||
|
|
writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24];
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_109_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14]));
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_110_[31] = _zz_109_;
|
||
|
|
_zz_110_[30] = _zz_109_;
|
||
|
|
_zz_110_[29] = _zz_109_;
|
||
|
|
_zz_110_[28] = _zz_109_;
|
||
|
|
_zz_110_[27] = _zz_109_;
|
||
|
|
_zz_110_[26] = _zz_109_;
|
||
|
|
_zz_110_[25] = _zz_109_;
|
||
|
|
_zz_110_[24] = _zz_109_;
|
||
|
|
_zz_110_[23] = _zz_109_;
|
||
|
|
_zz_110_[22] = _zz_109_;
|
||
|
|
_zz_110_[21] = _zz_109_;
|
||
|
|
_zz_110_[20] = _zz_109_;
|
||
|
|
_zz_110_[19] = _zz_109_;
|
||
|
|
_zz_110_[18] = _zz_109_;
|
||
|
|
_zz_110_[17] = _zz_109_;
|
||
|
|
_zz_110_[16] = _zz_109_;
|
||
|
|
_zz_110_[15] = _zz_109_;
|
||
|
|
_zz_110_[14] = _zz_109_;
|
||
|
|
_zz_110_[13] = _zz_109_;
|
||
|
|
_zz_110_[12] = _zz_109_;
|
||
|
|
_zz_110_[11] = _zz_109_;
|
||
|
|
_zz_110_[10] = _zz_109_;
|
||
|
|
_zz_110_[9] = _zz_109_;
|
||
|
|
_zz_110_[8] = _zz_109_;
|
||
|
|
_zz_110_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0];
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_111_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14]));
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_112_[31] = _zz_111_;
|
||
|
|
_zz_112_[30] = _zz_111_;
|
||
|
|
_zz_112_[29] = _zz_111_;
|
||
|
|
_zz_112_[28] = _zz_111_;
|
||
|
|
_zz_112_[27] = _zz_111_;
|
||
|
|
_zz_112_[26] = _zz_111_;
|
||
|
|
_zz_112_[25] = _zz_111_;
|
||
|
|
_zz_112_[24] = _zz_111_;
|
||
|
|
_zz_112_[23] = _zz_111_;
|
||
|
|
_zz_112_[22] = _zz_111_;
|
||
|
|
_zz_112_[21] = _zz_111_;
|
||
|
|
_zz_112_[20] = _zz_111_;
|
||
|
|
_zz_112_[19] = _zz_111_;
|
||
|
|
_zz_112_[18] = _zz_111_;
|
||
|
|
_zz_112_[17] = _zz_111_;
|
||
|
|
_zz_112_[16] = _zz_111_;
|
||
|
|
_zz_112_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0];
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
case(_zz_188_)
|
||
|
|
2'b00 : begin
|
||
|
|
writeBack_DBusSimplePlugin_rspFormated = _zz_110_;
|
||
|
|
end
|
||
|
|
2'b01 : begin
|
||
|
|
writeBack_DBusSimplePlugin_rspFormated = _zz_112_;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_virtualAddress;
|
||
|
|
assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1;
|
||
|
|
assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1;
|
||
|
|
assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1;
|
||
|
|
assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31];
|
||
|
|
assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0;
|
||
|
|
assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0;
|
||
|
|
assign IBusSimplePlugin_mmuBus_busy = 1'b0;
|
||
|
|
assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress;
|
||
|
|
assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1;
|
||
|
|
assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1;
|
||
|
|
assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1;
|
||
|
|
assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31];
|
||
|
|
assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0;
|
||
|
|
assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0;
|
||
|
|
assign DBusSimplePlugin_mmuBus_busy = 1'b0;
|
||
|
|
assign _zz_114_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000));
|
||
|
|
assign _zz_115_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000));
|
||
|
|
assign _zz_116_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000));
|
||
|
|
assign _zz_117_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100));
|
||
|
|
assign _zz_113_ = {(_zz_114_ != (1'b0)),{(((decode_INSTRUCTION & _zz_245_) == (32'b00000000000000000000000000010000)) != (1'b0)),{((_zz_246_ == _zz_247_) != (1'b0)),{(_zz_248_ != (1'b0)),{(_zz_249_ != _zz_250_),{_zz_251_,{_zz_252_,_zz_253_}}}}}}};
|
||
|
|
assign _zz_71_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_345_) == (32'b00000000000000000001000001110011)),{(_zz_346_ == _zz_347_),{_zz_348_,{_zz_349_,_zz_350_}}}}}}} != (20'b00000000000000000000));
|
||
|
|
assign _zz_118_ = _zz_113_[1 : 0];
|
||
|
|
assign _zz_70_ = _zz_118_;
|
||
|
|
assign _zz_69_ = _zz_203_[0];
|
||
|
|
assign _zz_68_ = _zz_204_[0];
|
||
|
|
assign _zz_67_ = _zz_205_[0];
|
||
|
|
assign _zz_66_ = _zz_206_[0];
|
||
|
|
assign _zz_119_ = _zz_113_[8 : 7];
|
||
|
|
assign _zz_65_ = _zz_119_;
|
||
|
|
assign _zz_64_ = _zz_207_[0];
|
||
|
|
assign _zz_63_ = _zz_208_[0];
|
||
|
|
assign _zz_120_ = _zz_113_[12 : 11];
|
||
|
|
assign _zz_62_ = _zz_120_;
|
||
|
|
assign _zz_61_ = _zz_209_[0];
|
||
|
|
assign _zz_121_ = _zz_113_[15 : 14];
|
||
|
|
assign _zz_60_ = _zz_121_;
|
||
|
|
assign _zz_122_ = _zz_113_[17 : 16];
|
||
|
|
assign _zz_59_ = _zz_122_;
|
||
|
|
assign _zz_123_ = _zz_113_[19 : 18];
|
||
|
|
assign _zz_58_ = _zz_123_;
|
||
|
|
assign _zz_57_ = _zz_210_[0];
|
||
|
|
assign _zz_56_ = _zz_211_[0];
|
||
|
|
assign _zz_124_ = _zz_113_[23 : 22];
|
||
|
|
assign _zz_55_ = _zz_124_;
|
||
|
|
assign _zz_54_ = _zz_212_[0];
|
||
|
|
assign _zz_53_ = _zz_213_[0];
|
||
|
|
assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION));
|
||
|
|
assign decodeExceptionPort_payload_code = (4'b0010);
|
||
|
|
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
|
||
|
|
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
|
||
|
|
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
|
||
|
|
assign decode_RegFilePlugin_rs1Data = _zz_161_;
|
||
|
|
assign decode_RegFilePlugin_rs2Data = _zz_162_;
|
||
|
|
assign _zz_52_ = decode_RegFilePlugin_rs1Data;
|
||
|
|
assign _zz_51_ = decode_RegFilePlugin_rs2Data;
|
||
|
|
always @ (*) begin
|
||
|
|
lastStageRegFileWrite_valid = (_zz_49_ && writeBack_arbitration_isFiring);
|
||
|
|
if(_zz_125_)begin
|
||
|
|
lastStageRegFileWrite_valid = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign lastStageRegFileWrite_payload_address = _zz_48_[11 : 7];
|
||
|
|
assign lastStageRegFileWrite_payload_data = _zz_72_;
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_ALU_BITWISE_CTRL)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin
|
||
|
|
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
|
||
|
|
end
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin
|
||
|
|
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_ALU_CTRL)
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : begin
|
||
|
|
_zz_126_ = execute_IntAluPlugin_bitwise;
|
||
|
|
end
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : begin
|
||
|
|
_zz_126_ = {31'd0, _zz_214_};
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_126_ = execute_SRC_ADD_SUB;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_46_ = _zz_126_;
|
||
|
|
assign _zz_44_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_SRC1_CTRL)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : begin
|
||
|
|
_zz_127_ = execute_RS1;
|
||
|
|
end
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin
|
||
|
|
_zz_127_ = {29'd0, _zz_215_};
|
||
|
|
end
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : begin
|
||
|
|
_zz_127_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)};
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_127_ = {27'd0, _zz_216_};
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_43_ = _zz_127_;
|
||
|
|
assign _zz_128_ = _zz_217_[11];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_129_[19] = _zz_128_;
|
||
|
|
_zz_129_[18] = _zz_128_;
|
||
|
|
_zz_129_[17] = _zz_128_;
|
||
|
|
_zz_129_[16] = _zz_128_;
|
||
|
|
_zz_129_[15] = _zz_128_;
|
||
|
|
_zz_129_[14] = _zz_128_;
|
||
|
|
_zz_129_[13] = _zz_128_;
|
||
|
|
_zz_129_[12] = _zz_128_;
|
||
|
|
_zz_129_[11] = _zz_128_;
|
||
|
|
_zz_129_[10] = _zz_128_;
|
||
|
|
_zz_129_[9] = _zz_128_;
|
||
|
|
_zz_129_[8] = _zz_128_;
|
||
|
|
_zz_129_[7] = _zz_128_;
|
||
|
|
_zz_129_[6] = _zz_128_;
|
||
|
|
_zz_129_[5] = _zz_128_;
|
||
|
|
_zz_129_[4] = _zz_128_;
|
||
|
|
_zz_129_[3] = _zz_128_;
|
||
|
|
_zz_129_[2] = _zz_128_;
|
||
|
|
_zz_129_[1] = _zz_128_;
|
||
|
|
_zz_129_[0] = _zz_128_;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_130_ = _zz_218_[11];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_131_[19] = _zz_130_;
|
||
|
|
_zz_131_[18] = _zz_130_;
|
||
|
|
_zz_131_[17] = _zz_130_;
|
||
|
|
_zz_131_[16] = _zz_130_;
|
||
|
|
_zz_131_[15] = _zz_130_;
|
||
|
|
_zz_131_[14] = _zz_130_;
|
||
|
|
_zz_131_[13] = _zz_130_;
|
||
|
|
_zz_131_[12] = _zz_130_;
|
||
|
|
_zz_131_[11] = _zz_130_;
|
||
|
|
_zz_131_[10] = _zz_130_;
|
||
|
|
_zz_131_[9] = _zz_130_;
|
||
|
|
_zz_131_[8] = _zz_130_;
|
||
|
|
_zz_131_[7] = _zz_130_;
|
||
|
|
_zz_131_[6] = _zz_130_;
|
||
|
|
_zz_131_[5] = _zz_130_;
|
||
|
|
_zz_131_[4] = _zz_130_;
|
||
|
|
_zz_131_[3] = _zz_130_;
|
||
|
|
_zz_131_[2] = _zz_130_;
|
||
|
|
_zz_131_[1] = _zz_130_;
|
||
|
|
_zz_131_[0] = _zz_130_;
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_SRC2_CTRL)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : begin
|
||
|
|
_zz_132_ = execute_RS2;
|
||
|
|
end
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : begin
|
||
|
|
_zz_132_ = {_zz_129_,execute_INSTRUCTION[31 : 20]};
|
||
|
|
end
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : begin
|
||
|
|
_zz_132_ = {_zz_131_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_132_ = _zz_39_;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_41_ = _zz_132_;
|
||
|
|
always @ (*) begin
|
||
|
|
execute_SrcPlugin_addSub = _zz_219_;
|
||
|
|
if(execute_SRC2_FORCE_ZERO)begin
|
||
|
|
execute_SrcPlugin_addSub = execute_SRC1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
|
||
|
|
assign _zz_38_ = execute_SrcPlugin_addSub;
|
||
|
|
assign _zz_37_ = execute_SrcPlugin_addSub;
|
||
|
|
assign _zz_36_ = execute_SrcPlugin_less;
|
||
|
|
assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1);
|
||
|
|
assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]);
|
||
|
|
assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1);
|
||
|
|
assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000));
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_SHIFT_CTRL)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : begin
|
||
|
|
_zz_133_ = (execute_LightShifterPlugin_shiftInput <<< 1);
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_133_ = _zz_226_;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_134_ = 1'b0;
|
||
|
|
if(_zz_137_)begin
|
||
|
|
if((_zz_138_ == decode_INSTRUCTION[19 : 15]))begin
|
||
|
|
_zz_134_ = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(_zz_176_)begin
|
||
|
|
if(_zz_177_)begin
|
||
|
|
if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
|
||
|
|
_zz_134_ = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(_zz_178_)begin
|
||
|
|
if(_zz_179_)begin
|
||
|
|
if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
|
||
|
|
_zz_134_ = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(_zz_180_)begin
|
||
|
|
if(_zz_181_)begin
|
||
|
|
if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
|
||
|
|
_zz_134_ = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if((! decode_RS1_USE))begin
|
||
|
|
_zz_134_ = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_135_ = 1'b0;
|
||
|
|
if(_zz_137_)begin
|
||
|
|
if((_zz_138_ == decode_INSTRUCTION[24 : 20]))begin
|
||
|
|
_zz_135_ = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(_zz_176_)begin
|
||
|
|
if(_zz_177_)begin
|
||
|
|
if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
|
||
|
|
_zz_135_ = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(_zz_178_)begin
|
||
|
|
if(_zz_179_)begin
|
||
|
|
if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
|
||
|
|
_zz_135_ = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(_zz_180_)begin
|
||
|
|
if(_zz_181_)begin
|
||
|
|
if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
|
||
|
|
_zz_135_ = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if((! decode_RS2_USE))begin
|
||
|
|
_zz_135_ = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_136_ = (_zz_49_ && writeBack_arbitration_isFiring);
|
||
|
|
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
|
||
|
|
assign _zz_139_ = execute_INSTRUCTION[14 : 12];
|
||
|
|
always @ (*) begin
|
||
|
|
if((_zz_139_ == (3'b000))) begin
|
||
|
|
_zz_140_ = execute_BranchPlugin_eq;
|
||
|
|
end else if((_zz_139_ == (3'b001))) begin
|
||
|
|
_zz_140_ = (! execute_BranchPlugin_eq);
|
||
|
|
end else if((((_zz_139_ & (3'b101)) == (3'b101)))) begin
|
||
|
|
_zz_140_ = (! execute_SRC_LESS);
|
||
|
|
end else begin
|
||
|
|
_zz_140_ = execute_SRC_LESS;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_BRANCH_CTRL)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : begin
|
||
|
|
_zz_141_ = 1'b0;
|
||
|
|
end
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : begin
|
||
|
|
_zz_141_ = 1'b1;
|
||
|
|
end
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : begin
|
||
|
|
_zz_141_ = 1'b1;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_141_ = _zz_140_;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_33_ = _zz_141_;
|
||
|
|
assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC);
|
||
|
|
assign _zz_142_ = _zz_228_[19];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_143_[10] = _zz_142_;
|
||
|
|
_zz_143_[9] = _zz_142_;
|
||
|
|
_zz_143_[8] = _zz_142_;
|
||
|
|
_zz_143_[7] = _zz_142_;
|
||
|
|
_zz_143_[6] = _zz_142_;
|
||
|
|
_zz_143_[5] = _zz_142_;
|
||
|
|
_zz_143_[4] = _zz_142_;
|
||
|
|
_zz_143_[3] = _zz_142_;
|
||
|
|
_zz_143_[2] = _zz_142_;
|
||
|
|
_zz_143_[1] = _zz_142_;
|
||
|
|
_zz_143_[0] = _zz_142_;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_144_ = _zz_229_[11];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_145_[19] = _zz_144_;
|
||
|
|
_zz_145_[18] = _zz_144_;
|
||
|
|
_zz_145_[17] = _zz_144_;
|
||
|
|
_zz_145_[16] = _zz_144_;
|
||
|
|
_zz_145_[15] = _zz_144_;
|
||
|
|
_zz_145_[14] = _zz_144_;
|
||
|
|
_zz_145_[13] = _zz_144_;
|
||
|
|
_zz_145_[12] = _zz_144_;
|
||
|
|
_zz_145_[11] = _zz_144_;
|
||
|
|
_zz_145_[10] = _zz_144_;
|
||
|
|
_zz_145_[9] = _zz_144_;
|
||
|
|
_zz_145_[8] = _zz_144_;
|
||
|
|
_zz_145_[7] = _zz_144_;
|
||
|
|
_zz_145_[6] = _zz_144_;
|
||
|
|
_zz_145_[5] = _zz_144_;
|
||
|
|
_zz_145_[4] = _zz_144_;
|
||
|
|
_zz_145_[3] = _zz_144_;
|
||
|
|
_zz_145_[2] = _zz_144_;
|
||
|
|
_zz_145_[1] = _zz_144_;
|
||
|
|
_zz_145_[0] = _zz_144_;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_146_ = _zz_230_[11];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_147_[18] = _zz_146_;
|
||
|
|
_zz_147_[17] = _zz_146_;
|
||
|
|
_zz_147_[16] = _zz_146_;
|
||
|
|
_zz_147_[15] = _zz_146_;
|
||
|
|
_zz_147_[14] = _zz_146_;
|
||
|
|
_zz_147_[13] = _zz_146_;
|
||
|
|
_zz_147_[12] = _zz_146_;
|
||
|
|
_zz_147_[11] = _zz_146_;
|
||
|
|
_zz_147_[10] = _zz_146_;
|
||
|
|
_zz_147_[9] = _zz_146_;
|
||
|
|
_zz_147_[8] = _zz_146_;
|
||
|
|
_zz_147_[7] = _zz_146_;
|
||
|
|
_zz_147_[6] = _zz_146_;
|
||
|
|
_zz_147_[5] = _zz_146_;
|
||
|
|
_zz_147_[4] = _zz_146_;
|
||
|
|
_zz_147_[3] = _zz_146_;
|
||
|
|
_zz_147_[2] = _zz_146_;
|
||
|
|
_zz_147_[1] = _zz_146_;
|
||
|
|
_zz_147_[0] = _zz_146_;
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_BRANCH_CTRL)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : begin
|
||
|
|
_zz_148_ = {{_zz_143_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
|
||
|
|
end
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : begin
|
||
|
|
_zz_148_ = {_zz_145_,execute_INSTRUCTION[31 : 20]};
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_148_ = {{_zz_147_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_BranchPlugin_branch_src2 = _zz_148_;
|
||
|
|
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
|
||
|
|
assign _zz_31_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)};
|
||
|
|
assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0));
|
||
|
|
assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC;
|
||
|
|
assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]);
|
||
|
|
assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000);
|
||
|
|
assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload;
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_privilege = (2'b11);
|
||
|
|
if(CsrPlugin_forceMachineWire)begin
|
||
|
|
CsrPlugin_privilege = (2'b11);
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign CsrPlugin_misa_base = (2'b01);
|
||
|
|
assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010);
|
||
|
|
assign _zz_149_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
|
||
|
|
assign _zz_150_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
|
||
|
|
assign _zz_151_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
|
||
|
|
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11);
|
||
|
|
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
|
||
|
|
assign _zz_152_ = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid};
|
||
|
|
assign _zz_153_ = _zz_231_[0];
|
||
|
|
assign _zz_154_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid};
|
||
|
|
assign _zz_155_ = _zz_233_[0];
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
|
||
|
|
if(_zz_166_)begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
|
||
|
|
end
|
||
|
|
if(decode_arbitration_isFlushed)begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
|
||
|
|
if(CsrPlugin_selfException_valid)begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
|
||
|
|
end
|
||
|
|
if(execute_arbitration_isFlushed)begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
|
||
|
|
if(_zz_168_)begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1;
|
||
|
|
end
|
||
|
|
if(memory_arbitration_isFlushed)begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
|
||
|
|
if(writeBack_arbitration_isFlushed)begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
|
||
|
|
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
|
||
|
|
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
|
||
|
|
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
|
||
|
|
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
|
||
|
|
assign CsrPlugin_lastStageWasWfi = 1'b0;
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusSimplePlugin_pcValids_3);
|
||
|
|
if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin
|
||
|
|
CsrPlugin_pipelineLiberator_done = 1'b0;
|
||
|
|
end
|
||
|
|
if(CsrPlugin_hadException)begin
|
||
|
|
CsrPlugin_pipelineLiberator_done = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
|
||
|
|
if(CsrPlugin_hadException)begin
|
||
|
|
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
|
||
|
|
if(CsrPlugin_hadException)begin
|
||
|
|
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_xtvec_mode = (2'bxx);
|
||
|
|
case(CsrPlugin_targetPrivilege)
|
||
|
|
2'b11 : begin
|
||
|
|
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
||
|
|
case(CsrPlugin_targetPrivilege)
|
||
|
|
2'b11 : begin
|
||
|
|
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign contextSwitching = CsrPlugin_jumpInterface_valid;
|
||
|
|
assign _zz_29_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000)))));
|
||
|
|
assign _zz_28_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000));
|
||
|
|
assign execute_CsrPlugin_inWfi = 1'b0;
|
||
|
|
assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00));
|
||
|
|
always @ (*) begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b1;
|
||
|
|
case(execute_CsrPlugin_csrAddress)
|
||
|
|
12'b101111000000 : begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
12'b001100000000 : begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
12'b001101000001 : begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
12'b001100000101 : begin
|
||
|
|
if(execute_CSR_WRITE_OPCODE)begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001101000100 : begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
12'b001101000011 : begin
|
||
|
|
if(execute_CSR_READ_OPCODE)begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b111111000000 : begin
|
||
|
|
if(execute_CSR_READ_OPCODE)begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001100000100 : begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
12'b001101000010 : begin
|
||
|
|
if(execute_CSR_READ_OPCODE)begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b1;
|
||
|
|
end
|
||
|
|
if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
execute_CsrPlugin_illegalInstruction = 1'b0;
|
||
|
|
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin
|
||
|
|
if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin
|
||
|
|
execute_CsrPlugin_illegalInstruction = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_selfException_valid = 1'b0;
|
||
|
|
if(_zz_182_)begin
|
||
|
|
CsrPlugin_selfException_valid = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_selfException_payload_code = (4'bxxxx);
|
||
|
|
if(_zz_182_)begin
|
||
|
|
case(CsrPlugin_privilege)
|
||
|
|
2'b00 : begin
|
||
|
|
CsrPlugin_selfException_payload_code = (4'b1000);
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
CsrPlugin_selfException_payload_code = (4'b1011);
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
|
||
|
|
always @ (*) begin
|
||
|
|
execute_CsrPlugin_readData = (32'b00000000000000000000000000000000);
|
||
|
|
case(execute_CsrPlugin_csrAddress)
|
||
|
|
12'b101111000000 : begin
|
||
|
|
execute_CsrPlugin_readData[31 : 0] = _zz_156_;
|
||
|
|
end
|
||
|
|
12'b001100000000 : begin
|
||
|
|
execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP;
|
||
|
|
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE;
|
||
|
|
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE;
|
||
|
|
end
|
||
|
|
12'b001101000001 : begin
|
||
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc;
|
||
|
|
end
|
||
|
|
12'b001100000101 : begin
|
||
|
|
end
|
||
|
|
12'b001101000100 : begin
|
||
|
|
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP;
|
||
|
|
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP;
|
||
|
|
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP;
|
||
|
|
end
|
||
|
|
12'b001101000011 : begin
|
||
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval;
|
||
|
|
end
|
||
|
|
12'b111111000000 : begin
|
||
|
|
execute_CsrPlugin_readData[31 : 0] = _zz_157_;
|
||
|
|
end
|
||
|
|
12'b001100000100 : begin
|
||
|
|
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE;
|
||
|
|
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE;
|
||
|
|
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE;
|
||
|
|
end
|
||
|
|
12'b001101000010 : begin
|
||
|
|
execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt;
|
||
|
|
execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
|
||
|
|
assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
|
||
|
|
assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
|
||
|
|
assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
|
||
|
|
assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData;
|
||
|
|
always @ (*) begin
|
||
|
|
case(_zz_189_)
|
||
|
|
1'b0 : begin
|
||
|
|
execute_CsrPlugin_writeData = execute_SRC1;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
|
||
|
|
assign _zz_157_ = (_zz_156_ & externalInterruptArray_regNext);
|
||
|
|
assign externalInterrupt = (_zz_157_ != (32'b00000000000000000000000000000000));
|
||
|
|
assign _zz_25_ = decode_ALU_BITWISE_CTRL;
|
||
|
|
assign _zz_23_ = _zz_58_;
|
||
|
|
assign _zz_47_ = decode_to_execute_ALU_BITWISE_CTRL;
|
||
|
|
assign _zz_22_ = decode_SHIFT_CTRL;
|
||
|
|
assign _zz_20_ = _zz_70_;
|
||
|
|
assign _zz_35_ = decode_to_execute_SHIFT_CTRL;
|
||
|
|
assign _zz_19_ = decode_ALU_CTRL;
|
||
|
|
assign _zz_17_ = _zz_60_;
|
||
|
|
assign _zz_45_ = decode_to_execute_ALU_CTRL;
|
||
|
|
assign _zz_16_ = decode_BRANCH_CTRL;
|
||
|
|
assign _zz_14_ = _zz_59_;
|
||
|
|
assign _zz_32_ = decode_to_execute_BRANCH_CTRL;
|
||
|
|
assign _zz_13_ = decode_SRC1_CTRL;
|
||
|
|
assign _zz_11_ = _zz_65_;
|
||
|
|
assign _zz_42_ = decode_to_execute_SRC1_CTRL;
|
||
|
|
assign _zz_10_ = decode_ENV_CTRL;
|
||
|
|
assign _zz_7_ = execute_ENV_CTRL;
|
||
|
|
assign _zz_5_ = memory_ENV_CTRL;
|
||
|
|
assign _zz_8_ = _zz_55_;
|
||
|
|
assign _zz_27_ = decode_to_execute_ENV_CTRL;
|
||
|
|
assign _zz_26_ = execute_to_memory_ENV_CTRL;
|
||
|
|
assign _zz_30_ = memory_to_writeBack_ENV_CTRL;
|
||
|
|
assign _zz_3_ = decode_SRC2_CTRL;
|
||
|
|
assign _zz_1_ = _zz_62_;
|
||
|
|
assign _zz_40_ = decode_to_execute_SRC2_CTRL;
|
||
|
|
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000)));
|
||
|
|
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000)));
|
||
|
|
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00)));
|
||
|
|
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0)));
|
||
|
|
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
|
||
|
|
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
|
||
|
|
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
|
||
|
|
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
|
||
|
|
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
|
||
|
|
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
|
||
|
|
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
|
||
|
|
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
|
||
|
|
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
|
||
|
|
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
|
||
|
|
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
|
||
|
|
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
|
||
|
|
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
|
||
|
|
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
|
||
|
|
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
|
||
|
|
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
|
||
|
|
assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready);
|
||
|
|
assign iBus_cmd_m2sPipe_valid = _zz_158_;
|
||
|
|
assign iBus_cmd_m2sPipe_payload_pc = _zz_159_;
|
||
|
|
assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2);
|
||
|
|
assign iBusWishbone_CTI = (3'b000);
|
||
|
|
assign iBusWishbone_BTE = (2'b00);
|
||
|
|
assign iBusWishbone_SEL = (4'b1111);
|
||
|
|
assign iBusWishbone_WE = 1'b0;
|
||
|
|
assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
||
|
|
assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid;
|
||
|
|
assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid;
|
||
|
|
assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK);
|
||
|
|
assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK);
|
||
|
|
assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO;
|
||
|
|
assign iBus_rsp_payload_error = 1'b0;
|
||
|
|
assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid;
|
||
|
|
assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr;
|
||
|
|
assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address;
|
||
|
|
assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data;
|
||
|
|
assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size;
|
||
|
|
assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready;
|
||
|
|
assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2);
|
||
|
|
assign dBusWishbone_CTI = (3'b000);
|
||
|
|
assign dBusWishbone_BTE = (2'b00);
|
||
|
|
always @ (*) begin
|
||
|
|
case(dBus_cmd_halfPipe_payload_size)
|
||
|
|
2'b00 : begin
|
||
|
|
_zz_160_ = (4'b0001);
|
||
|
|
end
|
||
|
|
2'b01 : begin
|
||
|
|
_zz_160_ = (4'b0011);
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_160_ = (4'b1111);
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
dBusWishbone_SEL = _zz_241_[3:0];
|
||
|
|
if((! dBus_cmd_halfPipe_payload_wr))begin
|
||
|
|
dBusWishbone_SEL = (4'b1111);
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr;
|
||
|
|
assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data;
|
||
|
|
assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK);
|
||
|
|
assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid;
|
||
|
|
assign dBusWishbone_STB = dBus_cmd_halfPipe_valid;
|
||
|
|
assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
|
||
|
|
assign dBus_rsp_data = dBusWishbone_DAT_MISO;
|
||
|
|
assign dBus_rsp_error = 1'b0;
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
if(reset) begin
|
||
|
|
IBusSimplePlugin_fetchPc_pcReg <= externalResetVector;
|
||
|
|
IBusSimplePlugin_fetchPc_booted <= 1'b0;
|
||
|
|
IBusSimplePlugin_fetchPc_inc <= 1'b0;
|
||
|
|
_zz_99_ <= 1'b0;
|
||
|
|
_zz_100_ <= 1'b0;
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0;
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0;
|
||
|
|
IBusSimplePlugin_injector_decodeRemoved <= 1'b0;
|
||
|
|
IBusSimplePlugin_pendingCmd <= (3'b000);
|
||
|
|
IBusSimplePlugin_rspJoin_discardCounter <= (3'b000);
|
||
|
|
_zz_125_ <= 1'b1;
|
||
|
|
execute_LightShifterPlugin_isActive <= 1'b0;
|
||
|
|
_zz_137_ <= 1'b0;
|
||
|
|
CsrPlugin_mstatus_MIE <= 1'b0;
|
||
|
|
CsrPlugin_mstatus_MPIE <= 1'b0;
|
||
|
|
CsrPlugin_mstatus_MPP <= (2'b11);
|
||
|
|
CsrPlugin_mie_MEIE <= 1'b0;
|
||
|
|
CsrPlugin_mie_MTIE <= 1'b0;
|
||
|
|
CsrPlugin_mie_MSIE <= 1'b0;
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
|
||
|
|
CsrPlugin_interrupt_valid <= 1'b0;
|
||
|
|
CsrPlugin_hadException <= 1'b0;
|
||
|
|
execute_CsrPlugin_wfiWake <= 1'b0;
|
||
|
|
_zz_156_ <= (32'b00000000000000000000000000000000);
|
||
|
|
execute_arbitration_isValid <= 1'b0;
|
||
|
|
memory_arbitration_isValid <= 1'b0;
|
||
|
|
writeBack_arbitration_isValid <= 1'b0;
|
||
|
|
memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000);
|
||
|
|
memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000);
|
||
|
|
_zz_158_ <= 1'b0;
|
||
|
|
dBus_cmd_halfPipe_regs_valid <= 1'b0;
|
||
|
|
dBus_cmd_halfPipe_regs_ready <= 1'b1;
|
||
|
|
end else begin
|
||
|
|
IBusSimplePlugin_fetchPc_booted <= 1'b1;
|
||
|
|
if((IBusSimplePlugin_fetchPc_corrected || IBusSimplePlugin_fetchPc_pcRegPropagate))begin
|
||
|
|
IBusSimplePlugin_fetchPc_inc <= 1'b0;
|
||
|
|
end
|
||
|
|
if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin
|
||
|
|
IBusSimplePlugin_fetchPc_inc <= 1'b1;
|
||
|
|
end
|
||
|
|
if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin
|
||
|
|
IBusSimplePlugin_fetchPc_inc <= 1'b0;
|
||
|
|
end
|
||
|
|
if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetcherflushIt) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin
|
||
|
|
IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
_zz_99_ <= 1'b0;
|
||
|
|
end
|
||
|
|
if(_zz_97_)begin
|
||
|
|
_zz_99_ <= IBusSimplePlugin_iBusRsp_stages_0_output_valid;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin
|
||
|
|
_zz_100_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_valid;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
_zz_100_ <= 1'b0;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0;
|
||
|
|
end
|
||
|
|
if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;
|
||
|
|
end
|
||
|
|
if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0;
|
||
|
|
end
|
||
|
|
if((! writeBack_arbitration_isStuck))begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0;
|
||
|
|
end
|
||
|
|
if(decode_arbitration_removeIt)begin
|
||
|
|
IBusSimplePlugin_injector_decodeRemoved <= 1'b1;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
IBusSimplePlugin_injector_decodeRemoved <= 1'b0;
|
||
|
|
end
|
||
|
|
IBusSimplePlugin_pendingCmd <= IBusSimplePlugin_pendingCmdNext;
|
||
|
|
IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_rspJoin_discardCounter - _zz_199_);
|
||
|
|
if(IBusSimplePlugin_fetcherflushIt)begin
|
||
|
|
IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_pendingCmd - _zz_201_);
|
||
|
|
end
|
||
|
|
_zz_125_ <= 1'b0;
|
||
|
|
if(_zz_164_)begin
|
||
|
|
if(_zz_167_)begin
|
||
|
|
execute_LightShifterPlugin_isActive <= 1'b1;
|
||
|
|
if(execute_LightShifterPlugin_done)begin
|
||
|
|
execute_LightShifterPlugin_isActive <= 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(execute_arbitration_removeIt)begin
|
||
|
|
execute_LightShifterPlugin_isActive <= 1'b0;
|
||
|
|
end
|
||
|
|
_zz_137_ <= _zz_136_;
|
||
|
|
if((! decode_arbitration_isStuck))begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
|
||
|
|
end else begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
|
||
|
|
end else begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
|
||
|
|
end else begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
|
||
|
|
end
|
||
|
|
if((! writeBack_arbitration_isStuck))begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
|
||
|
|
end else begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
|
||
|
|
end
|
||
|
|
CsrPlugin_interrupt_valid <= 1'b0;
|
||
|
|
if(_zz_183_)begin
|
||
|
|
if(_zz_184_)begin
|
||
|
|
CsrPlugin_interrupt_valid <= 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_185_)begin
|
||
|
|
CsrPlugin_interrupt_valid <= 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_186_)begin
|
||
|
|
CsrPlugin_interrupt_valid <= 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
CsrPlugin_hadException <= CsrPlugin_exception;
|
||
|
|
if(_zz_169_)begin
|
||
|
|
case(CsrPlugin_targetPrivilege)
|
||
|
|
2'b11 : begin
|
||
|
|
CsrPlugin_mstatus_MIE <= 1'b0;
|
||
|
|
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
|
||
|
|
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
if(_zz_170_)begin
|
||
|
|
case(_zz_171_)
|
||
|
|
2'b11 : begin
|
||
|
|
CsrPlugin_mstatus_MPP <= (2'b00);
|
||
|
|
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
|
||
|
|
CsrPlugin_mstatus_MPIE <= 1'b1;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
execute_CsrPlugin_wfiWake <= ({_zz_151_,{_zz_150_,_zz_149_}} != (3'b000));
|
||
|
|
if((! writeBack_arbitration_isStuck))begin
|
||
|
|
memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA;
|
||
|
|
end
|
||
|
|
if((! writeBack_arbitration_isStuck))begin
|
||
|
|
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
|
||
|
|
end
|
||
|
|
if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin
|
||
|
|
execute_arbitration_isValid <= 1'b0;
|
||
|
|
end
|
||
|
|
if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin
|
||
|
|
execute_arbitration_isValid <= decode_arbitration_isValid;
|
||
|
|
end
|
||
|
|
if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin
|
||
|
|
memory_arbitration_isValid <= 1'b0;
|
||
|
|
end
|
||
|
|
if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin
|
||
|
|
memory_arbitration_isValid <= execute_arbitration_isValid;
|
||
|
|
end
|
||
|
|
if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin
|
||
|
|
writeBack_arbitration_isValid <= 1'b0;
|
||
|
|
end
|
||
|
|
if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin
|
||
|
|
writeBack_arbitration_isValid <= memory_arbitration_isValid;
|
||
|
|
end
|
||
|
|
case(execute_CsrPlugin_csrAddress)
|
||
|
|
12'b101111000000 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
_zz_156_ <= execute_CsrPlugin_writeData[31 : 0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001100000000 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11];
|
||
|
|
CsrPlugin_mstatus_MPIE <= _zz_235_[0];
|
||
|
|
CsrPlugin_mstatus_MIE <= _zz_236_[0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001101000001 : begin
|
||
|
|
end
|
||
|
|
12'b001100000101 : begin
|
||
|
|
end
|
||
|
|
12'b001101000100 : begin
|
||
|
|
end
|
||
|
|
12'b001101000011 : begin
|
||
|
|
end
|
||
|
|
12'b111111000000 : begin
|
||
|
|
end
|
||
|
|
12'b001100000100 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
CsrPlugin_mie_MEIE <= _zz_238_[0];
|
||
|
|
CsrPlugin_mie_MTIE <= _zz_239_[0];
|
||
|
|
CsrPlugin_mie_MSIE <= _zz_240_[0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001101000010 : begin
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
if(iBus_cmd_ready)begin
|
||
|
|
_zz_158_ <= iBus_cmd_valid;
|
||
|
|
end
|
||
|
|
if(_zz_187_)begin
|
||
|
|
dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid;
|
||
|
|
dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid);
|
||
|
|
end else begin
|
||
|
|
dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready);
|
||
|
|
dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin
|
||
|
|
_zz_101_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc;
|
||
|
|
_zz_102_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error;
|
||
|
|
_zz_103_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst;
|
||
|
|
_zz_104_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_injector_decodeInput_ready)begin
|
||
|
|
IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst;
|
||
|
|
end
|
||
|
|
if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin
|
||
|
|
IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress;
|
||
|
|
IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess;
|
||
|
|
IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead;
|
||
|
|
IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite;
|
||
|
|
IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute;
|
||
|
|
IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception;
|
||
|
|
IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling;
|
||
|
|
end
|
||
|
|
if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin
|
||
|
|
$display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend");
|
||
|
|
end
|
||
|
|
if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin
|
||
|
|
$display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend");
|
||
|
|
end
|
||
|
|
if(_zz_164_)begin
|
||
|
|
if(_zz_167_)begin
|
||
|
|
execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001));
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(_zz_136_)begin
|
||
|
|
_zz_138_ <= _zz_48_[11 : 7];
|
||
|
|
end
|
||
|
|
CsrPlugin_mip_MEIP <= externalInterrupt;
|
||
|
|
CsrPlugin_mip_MTIP <= timerInterrupt;
|
||
|
|
CsrPlugin_mip_MSIP <= softwareInterrupt;
|
||
|
|
CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001));
|
||
|
|
if(writeBack_arbitration_isFiring)begin
|
||
|
|
CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001));
|
||
|
|
end
|
||
|
|
if(_zz_166_)begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_153_ ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_153_ ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
|
||
|
|
end
|
||
|
|
if(CsrPlugin_selfException_valid)begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code;
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr;
|
||
|
|
end
|
||
|
|
if(_zz_168_)begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_155_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code);
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_155_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr);
|
||
|
|
end
|
||
|
|
if(_zz_183_)begin
|
||
|
|
if(_zz_184_)begin
|
||
|
|
CsrPlugin_interrupt_code <= (4'b0111);
|
||
|
|
CsrPlugin_interrupt_targetPrivilege <= (2'b11);
|
||
|
|
end
|
||
|
|
if(_zz_185_)begin
|
||
|
|
CsrPlugin_interrupt_code <= (4'b0011);
|
||
|
|
CsrPlugin_interrupt_targetPrivilege <= (2'b11);
|
||
|
|
end
|
||
|
|
if(_zz_186_)begin
|
||
|
|
CsrPlugin_interrupt_code <= (4'b1011);
|
||
|
|
CsrPlugin_interrupt_targetPrivilege <= (2'b11);
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(_zz_169_)begin
|
||
|
|
case(CsrPlugin_targetPrivilege)
|
||
|
|
2'b11 : begin
|
||
|
|
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
|
||
|
|
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
|
||
|
|
CsrPlugin_mepc <= writeBack_PC;
|
||
|
|
if(CsrPlugin_hadException)begin
|
||
|
|
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
externalInterruptArray_regNext <= externalInterruptArray;
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_ALU_BITWISE_CTRL <= _zz_24_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_SHIFT_CTRL <= _zz_21_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_MMU_FAULT <= execute_MMU_FAULT;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress;
|
||
|
|
execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess;
|
||
|
|
execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead;
|
||
|
|
execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite;
|
||
|
|
execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute;
|
||
|
|
execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception;
|
||
|
|
execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_ALU_CTRL <= _zz_18_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_BRANCH_CTRL <= _zz_15_;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_SRC1_CTRL <= _zz_12_;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW;
|
||
|
|
end
|
||
|
|
if((! writeBack_arbitration_isStuck))begin
|
||
|
|
memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_ENV_CTRL <= _zz_9_;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_ENV_CTRL <= _zz_6_;
|
||
|
|
end
|
||
|
|
if((! writeBack_arbitration_isStuck))begin
|
||
|
|
memory_to_writeBack_ENV_CTRL <= _zz_4_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_RS2 <= decode_RS2;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_IS_CSR <= decode_IS_CSR;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
|
||
|
|
end
|
||
|
|
if((! writeBack_arbitration_isStuck))begin
|
||
|
|
memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE;
|
||
|
|
end
|
||
|
|
if((! writeBack_arbitration_isStuck))begin
|
||
|
|
memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_FORMAL_PC_NEXT <= _zz_85_;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT;
|
||
|
|
end
|
||
|
|
if((! writeBack_arbitration_isStuck))begin
|
||
|
|
memory_to_writeBack_FORMAL_PC_NEXT <= _zz_84_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
|
||
|
|
end
|
||
|
|
if((! writeBack_arbitration_isStuck))begin
|
||
|
|
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_PC <= decode_PC;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_PC <= _zz_39_;
|
||
|
|
end
|
||
|
|
if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin
|
||
|
|
memory_to_writeBack_PC <= memory_PC;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
|
||
|
|
end
|
||
|
|
if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin
|
||
|
|
execute_to_memory_REGFILE_WRITE_DATA <= _zz_34_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_SRC2_CTRL <= _zz_2_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_BRANCH_DO <= execute_BRANCH_DO;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_RS1 <= decode_RS1;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
|
||
|
|
end
|
||
|
|
if((! memory_arbitration_isStuck))begin
|
||
|
|
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
|
||
|
|
end
|
||
|
|
if((! writeBack_arbitration_isStuck))begin
|
||
|
|
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
|
||
|
|
end
|
||
|
|
case(execute_CsrPlugin_csrAddress)
|
||
|
|
12'b101111000000 : begin
|
||
|
|
end
|
||
|
|
12'b001100000000 : begin
|
||
|
|
end
|
||
|
|
12'b001101000001 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001100000101 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2];
|
||
|
|
CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001101000100 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
CsrPlugin_mip_MSIP <= _zz_237_[0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001101000011 : begin
|
||
|
|
end
|
||
|
|
12'b111111000000 : begin
|
||
|
|
end
|
||
|
|
12'b001100000100 : begin
|
||
|
|
end
|
||
|
|
12'b001101000010 : begin
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
if(iBus_cmd_ready)begin
|
||
|
|
_zz_159_ <= iBus_cmd_payload_pc;
|
||
|
|
end
|
||
|
|
if(_zz_187_)begin
|
||
|
|
dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr;
|
||
|
|
dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address;
|
||
|
|
dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data;
|
||
|
|
dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|