microwatt/sim-unisim/BUFG.vhdl

library IEEE;
use IEEE.std_logic_1164.all;

entity BUFG is
    port(I	: in std_logic;
	 O	: out std_logic
	 );
end BUFG;
architecture behaviour of BUFG is
begin
    O <= I;
end architecture behaviour;
Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs This adds a simple bus that can be mastered from an external system via JTAG, which will be used to hookup various debug modules. It's loosely based on the RiscV model (hence the DMI name). The module currently only supports hooking up to a Xilinx BSCANE2 but it shouldn't be too hard to adapt it to support different TAPs if necessary. The JTAG protocol proper is not exactly the RiscV one at this point, though I might still change it. This comes with some sim variants of Xilinx BSCANE2 and BUFG and a test bench. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`library IEEE;`
			`use IEEE.std_logic_1164.all;`

			`entity BUFG is`
			`port(I : in std_logic;`
			`O : out std_logic`
			`);`
			`end BUFG;`
			`architecture behaviour of BUFG is`
			`begin`
			`O <= I;`
			`end architecture behaviour;`