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222 lines
7.4 KiB
Python
222 lines
7.4 KiB
Python
from enum import Enum, unique
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from nmigen import Signal, Elaboratable, Module
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from nmigen_soc.wishbone import Interface as WishboneInterface
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from nmigen.back import verilog
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@unique
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class RegEnum(Enum):
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RXTX_DLL = 0
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IER_DLM = 1
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IIR_FCR = 2
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LCR = 3
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MCR = 4
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LSR = 5
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MSR = 6
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SCR = 7
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IER_ERBFI = 0
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IER_ETBEI = 1
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LCR_DLAB = 7
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class VUart(Elaboratable):
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"""
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Virtual UART. Presents a 16550 style interface over a wishbone slave
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and connects that to a read and write FIFO.
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Parameters
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----------
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Attributes
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----------
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"""
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def __init__(self):
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# Write port of FIFO A
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self.w_data = Signal(8)
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self.w_rdy = Signal()
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self.w_en = Signal()
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# Read port of FIFO B
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self.r_data = Signal(8)
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self.r_rdy = Signal()
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self.r_en = Signal()
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self.irq = Signal()
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# Wishbone slave
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self.wb = WishboneInterface(data_width=8, addr_width=3)
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def elaborate(self, platform):
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m = Module()
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# 16550 registers
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ier = Signal(4) # Interrupt enable register
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# ERBFI: enable RX interrupt
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# ETBEI: enable TX interrupt
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iir = Signal(4, reset=0b1) # Interrupt identification register
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# Interrupt pending
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# Interrupt ID
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fcr = Signal(8) # FIFO control register, ignore
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lcr = Signal(8) # Line control register, ignore all but DLAB bit
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mcr = Signal(5) # Modem control register, ignore
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lsr = Signal(8) # Line status register
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# DR: 1 when something in the fifo, reset to 0 when fifo empty
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# OE: RX fifo full and new character was attempted to add, need signal
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# from remote, not fifo full condition
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# THRE: always 1
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# TEMPT: always 1
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msr = Signal(8) # Modem status register, ignore
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scr = Signal(8) # Scratch register, ignore
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dll = Signal(8) # Divisor latch LS, ignore
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dlm = Signal(8) # Divisor latch MS, ignore
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# Some helpers
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is_write = Signal()
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is_read = Signal()
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m.d.comb += [
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is_write.eq(self.wb.stb & self.wb.cyc & self.wb.we),
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is_read.eq(self.wb.stb & self.wb.cyc & ~self.wb.we),
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]
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dlab = Signal()
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m.d.comb += dlab.eq(lcr[LCR_DLAB])
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# Don't read from an empty FIFO
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read_data = Signal(8)
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m.d.comb += read_data.eq(0)
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with m.If(self.r_rdy):
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m.d.comb += read_data.eq(self.r_data)
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m.d.sync += self.r_en.eq(0)
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m.d.sync += self.w_en.eq(0)
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# IRQ handling.
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#
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# On RX we raise an interrupt if there is anything in the RX FIFO. We
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# could optimise this by checking for a certain FIFO depth as well as
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# a timeout, similar to real 16550 hardware.
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#
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# For TX we can't assume the other end is consuming entries from the FIFO,
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# so we can't hook the interrupt, THRE and TEMPT bits to it. For now we
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# just always claim the TX FIFO is empty.
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m.d.comb += self.irq.eq(0)
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m.d.comb += iir.eq(0b0001) # IIR bit 0 is high for no IRQ
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# Lower priority is the TX interrupt. In this case we always raise an
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# interrupt if the enable bit is set
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with m.If(ier[IER_ETBEI]):
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m.d.comb += [
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self.irq.eq(1),
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iir.eq(0b0010),
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]
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# Highest priority is the RX interrupt. This overrides the TX interrupt
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# above.
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with m.If(ier[IER_ERBFI]):
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# Are there any entries in the RX FIFO?
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with m.If(self.r_rdy):
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m.d.comb += [
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self.irq.eq(1),
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iir.eq(0b0100),
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]
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with m.FSM():
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with m.State('IDLE'):
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# Write
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with m.If(is_write):
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with m.Switch(self.wb.adr):
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with m.Case(RegEnum.RXTX_DLL):
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with m.If(dlab):
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m.d.sync += dll.eq(self.wb.dat_w)
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with m.Else():
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m.d.sync += self.w_data.eq(self.wb.dat_w)
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with m.If(self.w_rdy):
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m.d.sync += self.w_en.eq(1)
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with m.Case(RegEnum.IER_DLM):
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with m.If(dlab):
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m.d.sync += dlm.eq(self.wb.dat_w)
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with m.Else():
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m.d.sync += ier.eq(self.wb.dat_w)
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with m.Case(RegEnum.IIR_FCR):
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m.d.sync += fcr.eq(self.wb.dat_w)
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with m.Case(RegEnum.LCR):
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m.d.sync += lcr.eq(self.wb.dat_w)
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with m.Case(RegEnum.MCR):
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m.d.sync += mcr.eq(self.wb.dat_w)
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with m.Case(RegEnum.MSR):
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m.d.sync += msr.eq(self.wb.dat_w)
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with m.Case(RegEnum.SCR):
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m.d.sync += scr.eq(self.wb.dat_w)
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m.d.sync += self.wb.ack.eq(1)
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m.next = 'ACK'
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# Read
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with m.Elif(is_read):
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with m.Switch(self.wb.adr):
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with m.Case(RegEnum.RXTX_DLL):
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with m.If(dlab):
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m.d.sync += self.wb.dat_r.eq(dll)
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with m.Else():
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m.d.sync += self.wb.dat_r.eq(read_data)
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with m.If(self.r_rdy):
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m.d.sync += self.r_en.eq(1)
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with m.Case(RegEnum.IER_DLM):
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with m.If(dlab):
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m.d.sync += self.wb.dat_r.eq(dlm)
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with m.Else():
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m.d.sync += self.wb.dat_r.eq(ier)
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with m.Case(RegEnum.IIR_FCR):
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m.d.sync += self.wb.dat_r.eq(iir)
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with m.Case(RegEnum.LCR):
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m.d.sync += self.wb.dat_r.eq(lcr)
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with m.Case(RegEnum.MCR):
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m.d.sync += self.wb.dat_r.eq(mcr)
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with m.Case(RegEnum.LSR):
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m.d.sync += [
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self.wb.dat_r.eq(0),
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self.wb.dat_r[0].eq(self.r_rdy),
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# Should we do something with the OE bit?
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self.wb.dat_r[1].eq(0),
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# Set THRE always to 1
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self.wb.dat_r[5].eq(1),
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# Set TEMT always to 1
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self.wb.dat_r[6].eq(1)
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]
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with m.Case(RegEnum.MSR):
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m.d.sync += self.wb.dat_r.eq(msr)
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with m.Case(RegEnum.SCR):
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m.d.sync += self.wb.dat_r.eq(scr)
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m.d.sync += self.wb.ack.eq(1)
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m.next = 'ACK'
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with m.State('ACK'):
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m.d.sync += self.wb.ack.eq(0)
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m.next = 'IDLE'
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return m
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if __name__ == "__main__":
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top = VUart()
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with open("vuart.v", "w") as f:
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f.write(verilog.convert(top))
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